JP2016225880A - Time synchronization device, time synchronization method, and time synchronization program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a time synchronization device and the like that can improve time precision in communication by a particular protocol.SOLUTION: A packet filter processing unit 100 corrects packet transmission time (t1) on the basis of the minimum value (minimum PDV) of time difference (t2'-t1) between the packet transmission time (t1) from a time master apparatus 600 and packet reception time (t2') stamped by a first clock 250, and corrects packet reception time (t4) on the basis of the minimum value (minimum PDV) of time difference (t4-t3') between packet transmission time (t3') stamped by the first clock 250 and the packet reception time (t4) at the time master apparatus 600.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a time synchronization apparatus suitable for a specific protocol (for example, IEEE1588v2). This type of technology is disclosed in Patent Documents 1 to 3, for example.

  FIG. 6 shows a time synchronization device 50 of the related technique 1. The time synchronizer 50 uses the IEEE 1588v2 protocol. Since IEEE1588v2 is generally called “PTP (Precision Time Protocol)”, it is unified with “PTP” in this specification.

  The time synchronizer 50 includes a t1 packet receiving unit 1, a follow-up packet receiving unit 2, a t3 packet transmitting unit 3, a t4 packet receiving unit 4, an XO (Crystal Oscillator) 10, a clock 11, a t2 stamping unit 20, and t2-t1. A calculation unit 21, an adder 22, a t3 marking unit 30, a t4-t3 calculation unit 31, a complementing unit 32, a PI (Proportional / Integrator) controller 40, and the like are provided.

  The t1 packet receiver 1 is “t1 (Sync. Message) Packet only”, the follow-up packet receiver 2 is “Follow-up Message Packet only”, the t3 packet transmitter 3 is “t3 (Delay Request) Packet only”, t4 The packet receiving unit 4 is “t4 (Delay Response) Packet only”, the clock 11 is “Servo PTP Epoch Counter”, the t2 stamping unit 20 is “t2 Time to stamp (for T / Servo)”, and the t2-t1 calculating unit 21 Is “t2-t1 cal. (MTSD)”, the adder 22 is “ADDER”, the t3 stamping unit 30 is “t3 Time to stamp (for T / Servo)”, and the t4-t3 calculating unit 31 is “t4-t3”. cal. (STMD) ”, the complementing unit 32 can be expressed as“ 2's Complement ”, and the PI controller 40 can be expressed as“ PI Controller ”.

  The operation of time synchronization by the time synchronization apparatus 50 is as follows. First, the timepiece 11 in the apparatus is constructed based on the reference oscillation source XO10 in the apparatus. Then, the time at which the t1 packet is received is stamped by the clock 11 at the t2 stamping unit 20 (the received packet arrival time is measured), and the time is defined as t2 time. Similarly, after receiving the t1 packet, the time at the time of transmitting the t3 packet is stamped by the t3 stamping unit 30, the time is inserted into the t3 packet, and transmitted from the t3 packet transmitting unit 3 to the time master device. Here, in order to synchronize the time, it may be t2-t1 (hereinafter also referred to as “MTSD (Master to Slave Delay)”) and t4-t3 (hereinafter referred to as “STMD (Slave to Master Delay)”). ), And PLL control may be performed so that the respective values are the same. For this purpose, the two's complement of STMD (-STMD) is calculated by the complementing unit 32, MTSD and -STMD are added by the adder 22, and the result is subjected to proportional / integral processing by the PI controller 40, and PI Based on the phase (time) data generated by the controller 40, a digital oscillator (DCO: Digitally Controlled Oscillator) in the timepiece 11 is controlled. The control signal can also be expressed as “Actuate to Digital Oscillator”. This series of processing is known as time servo processing in PTP. The t2 packet and the t4 packet are also known in the art.

JP 2014-027381 A JP 2010-212945 A JP 2014-147105 A

  In PTP, the delay between the MTSD direction (downstream) and the STMD direction (upstream) is not always the same, so a time difference occurs between the master and the slave. In order to avoid this, the delay in the MTSD direction (downlink) and the STMD direction (uplink) need only be always the same, but in the packet network, the uplink and downlink delays are never the same. Thus, since PTP is a protocol under the condition that the upstream and downstream delays are the same, if the delay condition is broken, the time accuracy deteriorates as it is. This is the biggest problem with PTP.

  In order to solve this problem, there is a technology in which Ethernet (registered trademark) is SyncE (Synchronous Ethernet), and frequency synchronization between master and slave is not performed, and only time synchronization is performed. However, in this case, since SyncE is essential, even if it can be applied in a new network, there is no merit in introducing it in an existing network.

  In addition, a technique for improving time accuracy by discarding a packet having a large delay time using a packet filter is also known (see, for example, Patent Document 2). However, even if the packet filter function is implemented in the related technique 1, the time servo-processed clock is used for the packet quality determination, and therefore the packet quality determination may not be performed normally due to a change in the network load. is there. The reason is that the time servo can extract only the clock synchronized with the network load fluctuation, and the fluctuation component is added to the clock used for determining the quality of the packet, so that the accurate time cannot be stamped.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a time synchronization apparatus and the like that can improve time accuracy in communication using a specific protocol.

The time synchronization apparatus according to the present invention is
In addition to having a first clock, the operation of the first clock is controlled so that the time difference between the packet transmission time from the time master device and the packet reception time stamped by the first clock is constant. A frequency synchronization unit;
Based on the minimum value of the time difference between the packet transmission time from the time master device and the packet reception time stamped by the first clock, the packet transmission time from the time master device is corrected, and the first A packet filter unit that corrects the packet reception time at the time master device based on the minimum value of the time difference between the packet transmission time stamped by the clock and the packet reception time at the time master device;
Having a second clock, calculating a downstream delay time from a packet transmission time from the time master device corrected by the packet filter unit and a packet reception time stamped by the second clock, Calculating an upstream delay time from a packet transmission time stamped by a second clock and a packet reception time at the time master device corrected by the packet filter unit, and the downstream delay time and the upstream delay time, A time synchronizer that controls the operation of the second timepiece so that
It is equipped with.

The time synchronization method according to the present invention includes:
A frequency synchronization step for controlling the operation of the first clock so that the time difference between the packet transmission time from the time master device and the packet reception time stamped by the first clock is constant;
Based on the minimum value of the time difference between the packet transmission time from the time master device and the packet reception time stamped by the first clock, the packet transmission time from the time master device is corrected, and the first A packet filter step for correcting the packet reception time at the time master device based on the minimum value of the time difference between the packet transmission time stamped by the clock and the packet reception time at the time master device;
Calculates a downstream delay time from the packet transmission time from the time master device corrected in the packet filter step and the packet reception time stamped by a second clock, and packet transmission stamped by the second clock An uplink delay time is calculated from the time and the packet reception time at the time master device corrected in the packet filter step, and the second delay time and the second delay time are made equal to each other. A time synchronization step for controlling the operation of the clock;
Is included.

The time synchronization program according to the present invention is:
Frequency synchronization means for controlling the operation of the first clock so that the time difference between the packet transmission time from the time master device and the packet reception time stamped by the first clock is constant;
Based on the minimum value of the time difference between the packet transmission time from the time master device and the packet reception time stamped by the first clock, the packet transmission time from the time master device is corrected, and the first Packet filter means for correcting the packet reception time at the time master device based on the minimum value of the time difference between the packet transmission time stamped by the clock and the packet reception time at the time master device;
Calculates a downstream delay time from the packet transmission time from the time master device corrected by the packet filter means and the packet reception time stamped by a second clock, and packet transmission stamped by the second clock An upstream delay time is calculated from the time and the packet reception time at the time master device corrected by the packet filter means, and the second delay time and the upstream delay time are made equal to each other. Time synchronization means for controlling the operation of the watch;
Is to make the computer function.

  According to the present invention, the packet transmission time and the packet reception time can be accurately corrected by operating the packet filter using a frequency synchronization clock equivalent to SyncE instead of a time synchronization clock. Time accuracy can be improved in communication.

It is a block diagram which shows the time synchronizer of Embodiment 1. FIG. FIG. 3 is a block diagram illustrating an IIR filter in the time synchronization apparatus of the first embodiment. 6 is a graph showing a relationship between a load time and a time offset in the time synchronization apparatus of Comparative Example 1; It is a graph which shows the relationship between the load time and the time offset in the time synchronizer of Embodiment 1. It is a graph which shows the relationship (expansion) of the load time and time offset in the time synchronizer of Embodiment 1. It is a block diagram which shows the time synchronizer of related technology 1.

  Hereinafter, modes for carrying out the present invention (hereinafter referred to as “embodiments”) will be described. First, the outline | summary of this Embodiment 1 is demonstrated.

  In order to solve the above-mentioned problem when the packet filter function is implemented in Related Technology 1, a frequency servo independent of the time servo is provided, a clock equivalent to SyncE is generated by the frequency servo, and the clock is used for packet pass / fail judgment. Use it. However, even if the frequency servo is made independent, in the test cases 13 and 14 defined in ITU-T G.8261, the load fluctuation is not constant, and there may be an overload or no load. . In this case, the frequency servo can eventually generate a stable clock if the time constant of the averaging filter is increased, but the time synchronization pull-in within 30 minutes after the power-on, which is a standard specific to the base station device, is possible. It becomes difficult to be satisfied. Even in this case, the first embodiment enables high-precision time synchronization even in a short time by calculating and correcting the frequency deviation after that based on the average value of a certain section.

  In the first embodiment, when the test case 13 (traffic model 2), which is a load model on the packet network defined in ITU-T G.8261, is applied, the time accuracy can be within ± 200 ns. It is what. The first embodiment can be realized with a very simple circuit configuration because the IEEE1588v2 protocol itself does not need to be changed and an external software algorithm for stabilizing the time accuracy is also unnecessary. Furthermore, in the first embodiment, highly accurate time synchronization is possible without using SyncE.

  The first embodiment is a slave system for stabilizing time synchronization when synchronization between wireless base stations is realized by IEEE 1588v2, such as LTE (Long Term Evolution). Specifically, only an ideal time packet is used. It is characterized by being capable of highly accurate time synchronization.

  Next, details of the first embodiment will be described with reference to the drawings. FIG. 1 is a block diagram illustrating a time synchronization apparatus according to the first embodiment. FIG. 2 is a block diagram showing an IIR filter in the time synchronization apparatus of the first embodiment.

  The time synchronization apparatus 400 according to the first embodiment includes a packet filter processing unit 100, a PTP frequency synchronization unit 200, and a PTP time synchronization unit 300. The PTP frequency synchronization unit 200 can be expressed as “PTP Frequency Servo”, and the PTP time synchronization unit 300 can be expressed as “PTP Time Servo”.

  The packet filter processing unit 100 includes a t1 packet receiving unit 111, a follow-up packet receiving unit 112, a t3 packet transmitting unit 113, a t4 packet receiving unit 114, a t2 ′ stamping unit 130, a t2′-t1 calculating unit 131, and a t2′−. t1 minimum time selection unit 132, t2'-t1 correction unit 133, t1 correction value update unit 134, t3 'stamping unit 140, t4-t3' calculation unit 141, t4-t3 'minimum time selection unit 142, t4-t3 'A correction unit 143 and a t4 correction value update unit 144 are provided. The t2 'stamping unit 130 is "t2' Time to stamp (for Packet Filter)", the t2'-t1 minimum time selecting unit 132 is "t2'-t1 min. PDV (Packet Delay Variation) Search & Keephold", t2 ' -T1 correction unit 133 is "t2'-t1 Correction", t1 correction value update unit 134 is "Update to PTP t1 Correction Field", t3 'stamping unit 140 is "t3' Time to stamp (for Packet Filter)", The t4-t3 ′ minimum time selection unit 142 is “t4-t3 ′ min. PDV Search & Keephold”, the t4-t3 ′ correction unit 143 is “t4-t3 ′ Correction”, and the t4 correction value update unit 144 is “Update to PTP”. t4 Correction Field "can also be written.

  The PTP frequency synchronization unit 200 includes a t2 ′ stamping unit 210, a phase comparator 220, an IIR (Infinite Impulse Response) filter 230, a PI controller 240, a first clock 250, and the like. The t2 ′ stamping section 210 is “t2 ′ Time to stamp (for F / Servo)”, the phase comparator 220 is “PD (Phase Detector) (for F / Servo)”, and the IIR filter 230 is “IIR Filter W / Smoothing”. The “Algorithm” and the first clock 250 can be written as “Servo 1 Epoch Counter”, respectively. The local time output from the first clock 250 to the t2 ′ stamping unit 210 can also be expressed as “t1 time (recovered)”.

  The IIR filter 230 includes a filter unit 510 and a dithering unit 520. The filter unit 510 includes an adder 511, a frequency divider 512, an adder 513, and an integrator 514. The dithering unit 520 includes a maximum time selection unit 521, a data output unit 522, a dithering processing unit 523, and an adder 524. The frequency divider 512 is “Divider (1 / N) N-Average”, the integrator 514 is “Integrator (Z ^ -1)”, the maximum time selection unit 521 is “MAX Time Search & Keephold”, and the data output unit 522 is “= N Count Filter data Keephold,> N Count Filter data”, and the dithering processing unit 523 can also be expressed as “Dithering (x−∞) / abs (MAX Time)”.

  The PTP time synchronization unit 300 includes an OCXO (Oven Controlled Crystal Oscillator) 310, a second clock 311, a t2 stamping unit 320, a t2-t1 calculation unit 321, an adder 322, a t3 stamping unit 330, and a t4-t3 calculation unit. 331, a complementing unit 332, a PI controller 340, and the like.

  The PTP time synchronization unit 300, and the t1 packet reception unit 111, the follow-up packet reception unit 112, the t3 packet transmission unit 113, and the t4 packet reception unit 114 of the packet filter processing unit 100 are time synchronization of the related technique 1 illustrated in FIG. According to the configuration of the device 50. The time master device 600 has a general configuration.

  Next, features of the time synchronization apparatus 400 according to the first embodiment will be described. As described above, the time synchronization apparatus 400 includes the packet filter processing unit 100, the PTP frequency synchronization unit 200, and the PTP time synchronization unit 300.

  The PTP frequency synchronization unit 200 includes a first clock 250 and a time difference between the packet transmission time (t1) from the time master device 600 and the packet reception time (t2 ′) stamped by the first clock 250 ( The operation of the first timepiece 250 is controlled so that t2′−t1) is constant. That is, the PTP frequency synchronization unit 200 synchronizes the frequency of the output signal (time) of the first timepiece 250 with the frequency of the output signal (time) of the time master device 600.

  The packet filter processing unit 100 determines the minimum value (t2′−t1) of the time difference (t2′−t1) between the packet transmission time (t1) from the time master device 600 and the packet reception time (t2 ′) stamped by the first clock 250. Based on the minimum PDV), the packet transmission time (t1) is corrected, and the time difference between the packet transmission time (t3 ′) stamped by the first clock 250 and the packet reception time (t4) at the time master device 600 Based on the minimum value (minimum PDV) of (t4-t3 ′), the packet reception time (t4) is corrected. Here, “correcting” includes adding a correction value to the correction field of each packet.

  The PTP time synchronization unit 300 includes a second clock 311, and from the packet transmission time (t 1) corrected by the packet filter processing unit 100 and the packet reception time (t 2) stamped by the second clock 311. The downstream delay time (t2−t1) is calculated and the upstream delay is calculated from the packet transmission time (t3) stamped by the second clock 311 and the packet reception time (t4) corrected by the packet filter processing unit 100. The time (t4-t3) is calculated, and the operation of the second timepiece 311 is controlled so that the downstream delay time (t4-t3) is equal to the upstream delay time (t2-t1). That is, the PTP time synchronization unit 300 synchronizes the output signal (time) of the second timepiece 311 with the output signal (time) of the time master device 600.

  The packet transmission time (t1) is included in the reception packet (follow-up packet), the packet reception time (t2 ′) corresponds to the reception packet (t1 packet), and the packet transmission time (t3 ′) is the transmission packet (t3 packet). And the packet reception time (t4) is included in the received packet (t4 packet).

  According to the first embodiment, the packet transmission processing unit 100 is operated by using the frequency synchronization clock 250 equivalent to SyncE instead of the time synchronization clock 311, so that the packet transmission time (t 1) and the packet reception time ( Since t4) can be accurately corrected, time accuracy can be improved in communication using a specific protocol.

  In addition, the time synchronization apparatus 400 according to the first embodiment can be paraphrased as follows.

  The time synchronization apparatus 400 is a time synchronization apparatus using the IEEE 1588 precision time protocol, and includes a packet filter processing unit 100, a PTP frequency synchronization unit 200, and a PTP time synchronization unit 300.

  The PTP frequency synchronization unit 200 includes the first clock 250, and the time difference t2′−t1 between the packet transmission time t1 from the time master device 600 and the packet reception time t2 ′ stamped by the first clock 250 is PLL control is executed on the first timepiece 250 so as to be constant.

  The packet filter processing unit 100 adds the correction value to the correction field for the packet transmission time t1 based on the minimum value of the time difference t2′−t1 between the packet transmission time t1 and the packet reception time t2 ′, and the first clock Based on the minimum value of the time difference t4-t3 ′ between the packet transmission time t3 ′ stamped by 250 and the packet reception time t4 at the time master device 600, the correction value is added to the correction field for the packet reception time t4.

  The PTP time synchronization unit 300 includes a second clock 311, a packet transmission time t 1 in which the correction value is added to the correction field by the packet filter processing unit 100, and a packet reception time t 2 stamped by the second clock 311. Is calculated from the packet transmission time t3 stamped by the second clock 311 and the packet reception time t4 in which the correction value is added to the correction field by the packet filter processing unit 100. Time t4-t3 is calculated, and PLL control is performed on the second timepiece 311 so that the downlink delay time t2-t1 and the uplink delay time t4-t3 are equal.

  More specifically, in Related Art 1, since the time servo unit has a function equivalent to a frequency servo, only the clock synchronized with the fluctuation in the network load can be extracted. Therefore, the clock to which the fluctuation component is added is used for the packet pass / fail judgment. When trying to do so, the exact time cannot be stamped. On the other hand, according to the first embodiment, by providing the frequency servo unit (PTP frequency synchronization unit 200) independent of the time servo unit (PTP time synchronization unit 300), it is possible to accurately avoid the influence of fluctuations in network load. Since the clock can be extracted, the accurate time can be stamped by using this clock for the packet pass / fail judgment.

  In addition, the PTP frequency synchronization unit 200 determines the time difference (t2′−t1) between the packet transmission time (t1) from the time master device 600 and the packet reception time (t2 ′) stamped by the first clock 250. , N is a natural number of 2 or more and a constant, M is a natural number and a variable that increases from 1 to 1, and data based on the average value of the first to Nth sampling data is used as a reference value, and Mth to N + Mth The control signal may be output to the first timepiece 250 so that the detection value is the data based on the average value of the sampling data up to the detection value and the detection value becomes equal to the reference value. In this case, highly accurate time synchronization is possible even in a short time by calculating and correcting the subsequent frequency deviation based on the average value of a certain section.

  Further, the PTP frequency synchronization unit 200 determines the time difference (t2′−t1) between the packet transmission time (t1) from the time master device 600 and the packet reception time (t2 ′) stamped by the first clock 250. The maximum value may be detected, and the control signal may be corrected so that the change in the frequency of the first timepiece 250 decreases as the maximum value increases. In this case, the frequency of the first timepiece 250 can be stabilized even when the time difference (t2'-t1) varies greatly.

  Next, the time synchronization apparatus 400 according to the first embodiment will be described in more detail.

  The PTP frequency synchronization unit 200 and the PTP time synchronization unit 300 are provided with independent first and second clocks (PTP Epoch Counters) 250 and 311, respectively. The reason why each has an independent clock is that the usage of each clock is different. As described above, the first clock 250 of the PTP frequency synchronization unit 200 is a clock for determining the quality of a received packet, and is generated based on a jitter / wander-free clean clock output from the OCXO 310. As the name suggests, the second clock 311 of the PTP time synchronization unit 300 is a clock for setting the same time as the master time. The second timepiece 311 is a so-called time synchronization timepiece, which is a timepiece in the apparatus.

  The packet filter processing unit 100 transmits and receives four types of messages for time synchronization. First, the t1 packet receiving unit 111 receives a t1 (Sync message) packet from the time master device 600. The t2 'stamping unit 130 stamps the received time as the t2' time according to the local time of the first clock 250 generated by the PTP frequency synchronization unit 200. The t2'-t1 calculation unit 131 calculates the difference between the t2 'time and the t1 time.

  In the first embodiment, IEEE 1588v2 describes a general 2STEP method, and therefore, a value included in a t2 (Follow-up Message) packet obtained by the follow-up packet receiving unit 112 is a time t1. The first embodiment can employ either the 1STEP method or the 2STEP method. The 1 STEP method is the same as the 2 STEP method except that the t1 time information is included in the t1 packet.

  The t2'-t1 minimum time selection unit 132 searches for the minimum time from the time difference calculated by the t2'-t1 calculation unit 131 and holds it. That is, the t2'-t1 minimum time selection unit 132 has a function of holding the minimum time and a function of separating other than the minimum time. The t2'-t1 correction unit 133 generates a correction value for the downlink time based on the result of the t2'-t1 minimum time selection unit 132. The t1 correction value update unit 134 adds the correction value to the Correction Field of the t1 packet.

  For example, it is assumed that the minimum PDV (min. PDV) is “2”. Since this is the standard, PDVs of “3” or more are handled as other PDVs (other min.PDV). That is, when the other PDV (other min. PDV) is “3”, “3-2 = 1” is added to the correction field. However, subtraction is not possible. This is because, when the minimum PDV (min. PDV) becomes “1”, the previous minimum PDV “2” becomes another PDV (other min. PDV).

  In the upstream direction, with respect to the t3 packet transmitted from the PTP time synchronization unit 300, the t3 ′ stamping unit 140 uses the local time of the first clock 250 generated by the PTP frequency synchronization unit 200 in the same manner as in the downstream direction. Stamps the transmission time. The stamped t3 'time is used only by the packet filter processing unit 100, and is not used for overwriting the t3 time in the original t3 packet. Therefore, the t3 packet transmission unit 113 transmits a t3 (Delay Request Message) packet to the time master device 600 as it is. The t4 packet receiving unit 114 receives a t4 (Delay Response Message) packet transmitted from the time master device 600. The t4-t3 'calculating unit 141 calculates the time difference between the t4 time and the t3' time.

  The t4-t3 ′ minimum time selection unit 142 finds the minimum time from the time difference calculated by the t4-t3 ′ calculation unit 141 and holds it. That is, the t4-t3 ′ minimum time selection unit 142 has a function of holding the minimum time and a function of separating other than the minimum time. The t4-t3 ′ correction unit 143 generates an upward time correction value based on the result of the t4-t3 ′ minimum time selection unit 142. The t4 correction value updating unit 144 adds the correction value to the Correction Field of the t4 packet.

  As described above, by acquiring the minimum time packet and correcting the time based on the packet, the difference in upstream and downstream delays can be minimized, and as a result, high time accuracy can be obtained. Is possible. Furthermore, since the minimum time packet is constantly updated, the time accuracy does not deteriorate from the previous time, and in the first embodiment, the accuracy is always in the direction of improving the accuracy. Here, when the minimum time packet is acquired, the reason why the uplink / downlink delay difference is minimized is that an accurate network propagation delay is reflected in the minimum time packet.

  From the above description, the t2 'stamping unit 130 and the t3' stamping unit 140 of the packet filter processing unit 100 require a clock that is frequency-synchronized with the time master device 600 and that is jitter-wander-free. The reason is that if the frequency is not synchronized, there will be an error in the time of each time. If there is jitter wander, the time will be imprinted even if the frequency is synchronized. This is because the minimum time packet cannot be obtained accurately and does not function normally as a packet filter.

  Such a problem can be solved by using SyncE, but it is not feasible because the entire network needs to be replaced with SyncE. Therefore, the first embodiment employs a frequency synchronization method based on Async Ethernet instead of SyncE.

  Specifically, by implementing the PTP frequency synchronization unit 200, frequency synchronization with the time master device 600 and jitter / wander-free clock recovery are realized. More specifically, first, the t2 'stamping unit 210 stamps the time at which the t1 packet receiving unit 111 receives the t1 packet with the clock 250, and sets this as the t2' time. Subsequently, the phase comparator 220 extracts the t1 time from the follow-up message received by the follow-up packet receiving unit 112, and compares the t1 time with the t2 'time (that is, phase comparison). The difference signal, which is the comparison result, is filtered by the IIR filter 230 to be a smoothed difference signal from which jitter and noise have been removed. Then, the smoothed difference signal is subjected to proportional / integral processing by the PI controller 240 to be output to the DCO in the timepiece 250 as a control signal for finally converging the difference signal to be constant. Thereby, frequency synchronization is performed.

  Note that the clock CLK used by the DCO in the watch 250 is the external OCXO 310. The reason for using OCXO is that the DC loop gain of the PTP frequency synchronization unit 200 can be lowered by reducing the frequency drift of the DCO as much as possible, so that a highly accurate clock can be reproduced. Here, the reason why the DCO is used, why the PI control is necessary, and the PI control method for the DCO are the same as those of a normal digital PLL. The feature of the first embodiment is that the PTP frequency synchronization unit 200 is essential for the reference clock of the packet filter processing unit 100, not the PTP frequency synchronization unit 200 itself, and further described in the next section.

  A detailed block diagram of the IIR filter 230 is shown in FIG. The inside of the IIR filter 230 is roughly composed of a filter unit 510 and a dithering unit 520. Since the filter unit 510 is a general IIR filter except for the frequency divider 512, only the frequency divider 512 will be described. Since the denominator N set in the frequency divider 512 is a user settable, it can be changed by external control. This N value becomes the learning time of the PTP frequency synchronization unit 200. When the delay distribution of the packet network is a normal distribution, the denominator N may be reduced. However, when the distribution is not constant, it is necessary to increase the N value for accurate frequency averaging. It is desirable that the N value is actually a value suitable for the packet network by the packet network operator. Also, depending on the packet network, there may be a case where the load fluctuates suddenly or the load increases or decreases step by step. In these cases, the problem can be solved by increasing the N value. However, since the base station and the like need to be synchronized in time within 30 minutes after the power is turned on, the N value cannot be increased so much. In such a case, the dithering unit 520 is effective.

  The dithering unit 520 detects the maximum value of the comparison result output from the phase comparator 220 in the PTP frequency synchronization unit 200, holds the maximum value (maximum time selection unit 521), and the filter unit 510 counts N. This result is retained for reference (data output block 522). The result of N <count is the maximum time at which “N count value (reference value) −N <count value” is calculated in the sampling period unit of the filter unit 510 and the result is held in the maximum time selection unit 521. Divide by the difference (dithering processing unit 523).

  Basically, the operation may be performed only by “N count value (reference value) −N <count value”. However, in such a case, normal frequency synchronization cannot be performed when the time changes in the time master device 600 (first problem) or when the PTP frequency synchronization unit 200 operates in the dead zone (second problem). There is a fear. Therefore, the adder 524 adds the complement of “(N count value (reference value) −N <count value) / maximum time difference” to the N count result from the filter unit 510 to solve the above two problems. It has been solved.

  Next, the effectiveness of the dithering unit 520 will be described with reference to FIGS. 3 to 5 show simulation results when the test case TC13_TM2 shown in ITU-T G.8261 is applied with respect to the presence or absence of the dithering unit 520. FIG.

  FIG. 3 is a fluctuation graph of the time offset amount when the dithering unit 520 is not mounted (Comparative Example 1). In the first comparative example, the filter unit 510 is mounted, and N = 300 s. As can be seen from FIG. 3, the moving average data (gray point) transitions almost in accordance with the raw data (black point) of the time offset. In this state, it becomes difficult to use the local time from the PTP frequency synchronization unit 200 as the reference clock of the packet filter processing unit 100. This is because the packet filter processing unit 100 tends to malfunction when the fluctuation of the time offset is about ± 10 μs.

  FIG. 4 shows a time offset result when the dithering unit 520 is mounted (the first embodiment). From this result, it can be seen that the time offset converges to approximately 4 μs. As can be seen from FIG. 5 in which FIG. 4 is enlarged, strictly speaking, the fluctuation of the time offset is about ± 200 ns or less and satisfies the LTE-A standard of ± 500 ns or less. Thus, it is considered that the effect of the dithering unit 520 is sufficient.

  As described above, according to the first embodiment, when test case 13 (traffic model 2), which is a load model on the packet network defined in ITU-T G.8261, is applied, time accuracy is improved. Can be done within ± 200ns. The first embodiment can be realized with a very simple circuit configuration because the IEEE1588v2 protocol itself does not need to be changed and an external software algorithm for stabilizing the time accuracy is also unnecessary. There is also no need for SyncE.

  Next, a time synchronization method and a time synchronization program according to the first embodiment will be described.

  The time synchronization method according to the first embodiment captures the operation of the time synchronization apparatus 400 according to the first embodiment as a method invention. That is, the time synchronization method of the first embodiment includes a packet filter processing step, a PTP frequency synchronization step, and a PTP time synchronization step.

  In the PTP frequency synchronization step, the time difference (t2′−t1) between the packet transmission time (t1) from the time master device 600 and the packet reception time (t2 ′) stamped by the first clock 250 is constant. In addition, the operation of the first timepiece 250 is controlled.

  In the packet filter processing step, the minimum value (minimum) of the time difference (t2′−t1) between the packet transmission time (t1) from the time master device 600 and the packet reception time (t2 ′) stamped by the first clock 250. PDV), the packet transmission time (t1) is corrected, and the time difference between the packet transmission time (t3 ′) stamped by the first clock 250 and the packet reception time (t4) at the time master device 600 ( Based on the minimum value (minimum PDV) of t4−t3 ′), the packet reception time (t4) is corrected.

  In the PTP time synchronization step, a downstream time difference (t2−t1) is calculated from the packet transmission time (t1) corrected in the packet filter processing step and the packet reception time (t2) stamped by the second clock 311. The upstream time difference (t4−t3) is calculated from the packet transmission time (t3) stamped by the second clock 311 and the packet reception time (t4) corrected in the packet filtering step, and the downstream time difference is calculated. The operation of the second timepiece 311 is controlled so that (t4−t3) and the time difference in the upward direction (t2−t1) are equal.

  The time synchronization program of the first embodiment is for causing a computer to function each unit (each unit) of the time synchronization apparatus 400 of the first embodiment. That is, the time synchronization method of the first embodiment includes a packet filter processing unit (100), a PTP frequency synchronization unit (200), and a PTP time synchronization unit (300).

  The PTP frequency synchronization means (200) has a constant time difference (t2′−t1) between the packet transmission time (t1) from the time master device 600 and the packet reception time (t2 ′) stamped by the first clock 250. The operation of the first timepiece 250 is controlled so that

  The packet filter processing means (100) determines the minimum time difference (t2′−t1) between the packet transmission time (t1) from the time master device 600 and the packet reception time (t2 ′) stamped by the first clock 250. The packet transmission time (t1) is corrected based on the value (minimum PDV), and the packet transmission time (t3 ′) stamped by the first clock 250 and the packet reception time (t4) at the time master device 600 are The packet reception time (t4) is corrected based on the minimum value (minimum PDV) of the time difference (t4−t3 ′).

  The PTP time synchronization means (300) calculates the downstream delay time (t2−) from the packet transmission time (t1) corrected by the packet filter means (100) and the packet reception time (t2) stamped by the second clock 311. t1) is calculated, and the upstream delay time (t4-t3) is calculated from the packet transmission time (t3) stamped by the second clock 311 and the packet reception time (t4) corrected by the packet filter means (100). Then, the operation of the second timepiece 311 is controlled so that the downstream delay time (t4-t3) and the upstream delay time (t2-t1) are equal.

  The program may be recorded on a non-transitory storage medium, such as an optical disk or a semiconductor memory. In this case, the program is read from the recording medium by a computer and executed.

  Other configurations, operations, and effects of the time synchronization method and the time synchronization program of the first embodiment are the same as those of the time synchronization apparatus 400 of the first embodiment.

  The present invention has been described above with reference to the above embodiment, but the present invention is not limited to the above embodiment. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention. Moreover, although part or all of said embodiment may be described also as the following additional remarks, this invention is not limited to the following structures.

[Supplementary Note 1] The first clock has a first clock, and the time difference between the packet transmission time from the time master device and the packet reception time stamped by the first clock is constant. A frequency synchronization unit for controlling the operation;
Based on the minimum value of the time difference between the packet transmission time from the time master device and the packet reception time stamped by the first clock, the packet transmission time from the time master device is corrected, and the first A packet filter unit that corrects the packet reception time at the time master device based on the minimum value of the time difference between the packet transmission time stamped by the clock and the packet reception time at the time master device;
Having a second clock, calculating a downstream delay time from a packet transmission time from the time master device corrected by the packet filter unit and a packet reception time stamped by the second clock, Calculating an upstream delay time from a packet transmission time stamped by a second clock and a packet reception time at the time master device corrected by the packet filter unit, and the downstream delay time and the upstream delay time, A time synchronizer that controls the operation of the second timepiece so that
A time synchronizer comprising:

[Supplementary Note 2] The frequency synchronization unit includes:
About the time difference between the packet transmission time from the time master device and the packet reception time stamped by the first clock,
When N is a natural number of 2 or more and a constant, and M is a natural number and a variable increasing from 1 to 1,
The data based on the average value of the first to Nth sampling data is used as a reference value, and the data based on the average value of the Mth to N + Mth sampling data is used as a detection value.
Outputting a control signal to the first timepiece so that the detected value is equal to the reference value;
The time synchronizer according to appendix 1.

[Supplementary Note 3] The frequency synchronization unit includes:
Detecting the maximum value of the time difference between the packet transmission time from the time master device and the packet reception time stamped by the first clock,
The control signal is corrected so that the change in the frequency of the first watch decreases as the maximum value increases.
The time synchronizer according to appendix 2.

[Supplementary Note 4] A time synchronization device using the IEEE 1588 Precision Time Protocol,
The first clock is provided, and the time difference t2′−t1 between the packet transmission time t1 from the time master device and the packet reception time t2 ′ stamped by the first clock is constant. A frequency synchronization unit that performs PLL control on the clock of
Based on the minimum value of the time difference t2′−t1 between the packet transmission time t1 and the packet reception time t2 ′, a correction value is added to the correction field for the packet transmission time t1, and the first clock watches the time stamp. A packet filter unit that adds a correction value to the correction field for the packet reception time t4 based on the minimum value of the time difference t4-t3 ′ between the packet transmission time t3 ′ and the packet reception time t4 at the time master device;
A second delay time t2 from a packet transmission time t1 when the correction value is added to the correction field by the packet filter unit and a packet reception time t2 stamped by the second clock. -T1 is calculated, and the upstream delay time t4-t3 is calculated from the packet transmission time t3 stamped by the second clock and the packet reception time t4 obtained by adding the correction value to the correction field by the packet filter unit. A time synchronization unit that calculates and executes PLL control on the second clock so that the downstream delay time t2-t1 and the upstream delay time t4-t3 are equal to each other;
A time synchronizer comprising:

[Supplementary Note 5] A frequency synchronization step for controlling the operation of the first clock so that the time difference between the packet transmission time from the time master device and the packet reception time stamped by the first clock is constant;
Based on the minimum value of the time difference between the packet transmission time from the time master device and the packet reception time stamped by the first clock, the packet transmission time from the time master device is corrected, and the first A packet filter step for correcting the packet reception time at the time master device based on the minimum value of the time difference between the packet transmission time stamped by the clock and the packet reception time at the time master device;
Calculates a downstream delay time from the packet transmission time from the time master device corrected in the packet filter step and the packet reception time stamped by a second clock, and packet transmission stamped by the second clock An uplink delay time is calculated from the time and the packet reception time at the time master device corrected in the packet filter step, and the second delay time and the second delay time are made equal to each other. A time synchronization step for controlling the operation of the clock;
Time synchronization method including

[Appendix 6] Frequency synchronization means for controlling the operation of the first clock so that the time difference between the packet transmission time from the time master device and the packet reception time stamped by the first clock is constant;
Based on the minimum value of the time difference between the packet transmission time from the time master device and the packet reception time stamped by the first clock, the packet transmission time from the time master device is corrected, and the first Packet filter means for correcting the packet reception time at the time master device based on the minimum value of the time difference between the packet transmission time stamped by the clock and the packet reception time at the time master device;
Calculates a downstream delay time from the packet transmission time from the time master device corrected by the packet filter means and the packet reception time stamped by a second clock, and packet transmission stamped by the second clock An upstream delay time is calculated from the time and the packet reception time at the time master device corrected by the packet filter means, and the second delay time and the upstream delay time are made equal to each other. Time synchronization means for controlling the operation of the watch;
Time synchronization program to make the computer function.

  The present invention can be used, for example, in a slave system between wireless base stations.

<Embodiment 1>
400 Time synchronization device 100 Packet filter processing unit (packet filter unit)
111 t1 packet receiving unit 112 follow-up packet receiving unit 113 t3 packet transmitting unit 114 t4 packet receiving unit 130 t2 'stamping unit 131 t2'-t1 calculating unit 132 t2'-t1 minimum time selecting unit 133 t2'-t1 correcting unit 134 t1 correction value update unit 140 t3 'stamping unit 141 t4-t3' calculation unit 142 t4-t3 'minimum time selection unit 143 t4-t3' correction unit 144 t4 correction value update unit 200 PTP frequency synchronization unit (frequency synchronization unit) )
210 t2 ′ stamping unit 220 phase comparator 230 IIR filter 510 filter unit
511 Adder
512 divider
513 Adder
514 Integrator 520 Dithering section
521 Maximum time selector
522 Data output part
523 Dithering processing part
524 adder 240 PI controller 250 first clock 300 PTP time synchronization unit (time synchronization unit)
310 OCXO
311 Second clock 320 t2 stamping unit 321 t2-t1 calculating unit 322 adder 330 t3 stamping unit 331 t4-t3 calculating unit 332 complementing unit 340 PI controller 600 time master device

<Related technology 1>
50 Time synchronizer 1 t1 packet receiver 2 follow-up packet receiver 3 t3 packet transmitter 4 t4 packet receiver 10 XO
11 Clock 20 t2 stamping part 21 t2-t1 calculating part 22 Adder 30 t3 stamping part 31 t4-t3 calculating part 32 Complementing part 40 PI controller

Claims (6)

In addition to having a first clock, the operation of the first clock is controlled so that the time difference between the packet transmission time from the time master device and the packet reception time stamped by the first clock is constant. A frequency synchronization unit;
Based on the minimum value of the time difference between the packet transmission time from the time master device and the packet reception time stamped by the first clock, the packet transmission time from the time master device is corrected, and the first A packet filter unit that corrects the packet reception time at the time master device based on the minimum value of the time difference between the packet transmission time stamped by the clock and the packet reception time at the time master device;
Having a second clock, calculating a downstream delay time from a packet transmission time from the time master device corrected by the packet filter unit and a packet reception time stamped by the second clock, Calculating an upstream delay time from a packet transmission time stamped by a second clock and a packet reception time at the time master device corrected by the packet filter unit, and the downstream delay time and the upstream delay time, A time synchronizer that controls the operation of the second timepiece so that
A time synchronizer comprising: The frequency synchronization unit is
About the time difference between the packet transmission time from the time master device and the packet reception time stamped by the first clock,
When N is a natural number of 2 or more and a constant, and M is a natural number and a variable increasing from 1 to 1,
The data based on the average value of the first to Nth sampling data is used as a reference value, and the data based on the average value of the Mth to N + Mth sampling data is used as a detection value.
Outputting a control signal to the first timepiece so that the detected value is equal to the reference value;
The time synchronization apparatus according to claim 1. The frequency synchronization unit is
Detecting the maximum value of the time difference between the packet transmission time from the time master device and the packet reception time stamped by the first clock,
The control signal is corrected so that the change in the frequency of the first watch decreases as the maximum value increases.
The time synchronizer of Claim 2. A time synchronization device using an IEEE 1588 precision time protocol,
The first clock is provided, and the time difference t2′−t1 between the packet transmission time t1 from the time master device and the packet reception time t2 ′ stamped by the first clock is constant. A frequency synchronization unit that performs PLL control on the clock of
Based on the minimum value of the time difference t2′−t1 between the packet transmission time t1 and the packet reception time t2 ′, a correction value is added to the correction field for the packet transmission time t1, and the first clock watches the time stamp. A packet filter unit that adds a correction value to the correction field for the packet reception time t4 based on the minimum value of the time difference t4-t3 ′ between the packet transmission time t3 ′ and the packet reception time t4 at the time master device;
A second delay time t2 from a packet transmission time t1 when the correction value is added to the correction field by the packet filter unit and a packet reception time t2 stamped by the second clock. -T1 is calculated, and the upstream delay time t4-t3 is calculated from the packet transmission time t3 stamped by the second clock and the packet reception time t4 obtained by adding the correction value to the correction field by the packet filter unit. A time synchronization unit that calculates and executes PLL control on the second clock so that the downstream delay time t2-t1 and the upstream delay time t4-t3 are equal to each other;
A time synchronizer comprising: A frequency synchronization step for controlling the operation of the first clock so that the time difference between the packet transmission time from the time master device and the packet reception time stamped by the first clock is constant;
Based on the minimum value of the time difference between the packet transmission time from the time master device and the packet reception time stamped by the first clock, the packet transmission time from the time master device is corrected, and the first A packet filter step for correcting the packet reception time at the time master device based on the minimum value of the time difference between the packet transmission time stamped by the clock and the packet reception time at the time master device;
Calculates a downstream delay time from the packet transmission time from the time master device corrected in the packet filter step and the packet reception time stamped by a second clock, and packet transmission stamped by the second clock An uplink delay time is calculated from the time and the packet reception time at the time master device corrected in the packet filter step, and the second delay time and the second delay time are made equal to each other. A time synchronization step for controlling the operation of the clock;
Time synchronization method including Frequency synchronization means for controlling the operation of the first clock so that the time difference between the packet transmission time from the time master device and the packet reception time stamped by the first clock is constant;
Based on the minimum value of the time difference between the packet transmission time from the time master device and the packet reception time stamped by the first clock, the packet transmission time from the time master device is corrected, and the first Packet filter means for correcting the packet reception time at the time master device based on the minimum value of the time difference between the packet transmission time stamped by the clock and the packet reception time at the time master device;
Calculates a downstream delay time from the packet transmission time from the time master device corrected by the packet filter means and the packet reception time stamped by a second clock, and packet transmission stamped by the second clock An upstream delay time is calculated from the time and the packet reception time at the time master device corrected by the packet filter means, and the second delay time and the upstream delay time are made equal to each other. Time synchronization means for controlling the operation of the watch;
Time synchronization program to make the computer function.

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