JP2006100616A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the in-process charge-up protection performance of a MOS-type transistor element by protecting a gate insulation film on the source-drain diffusion layer of the MOS transistor element. <P>SOLUTION: The semiconductor device comprises a MOS transistor element which contains a first gate insulation film 5 and a gate electrode 7, and is formed between source and drain diffusion layers in a p-type well 2; a first MOS diode element which contains a second gate insulation film 6 and the gate electrode 7, and is formed in the p-type well 2; and a second MOS semiconductor element which contains the second gate insulation film 6 and the gate electrode 7, and is formed in an n-type well 3. The breakdown voltage of the second gate insulation film 6 is set lower than that of the first gate insulation film 5, and the gate electrodes 7 of individual elements are electrically connected to one another. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device that reduces charge-up damage during an insulating film process.

  In recent years, the gate insulating film of a MOS transistor has been thinned in accordance with high integration, high functionality, and high speed of a semiconductor integrated circuit device. However, there is a concern that the gate insulating film is destroyed due to charge-up damage during the diffusion process.

  Therefore, there is a method for preventing charge-up damage during the diffusion process by connecting a MOS diode element having a gate insulating film thinner than the gate insulating film of the MOS transistor element to be protected to the gate electrode of the MOS transistor. Proposed.

  Hereinafter, the method disclosed in Patent Document 1 will be described with reference to FIGS. 4 and 5.

  As shown in FIG. 4, in the conventional example, a P-type well 2 and an element isolation film 4 are formed on a P-type semiconductor substrate 1, and an NMOS transistor element including a first gate insulating film 5 and a gate electrode 7; An NMOS diode element composed of the second gate insulating film 6 and the gate electrode 7 is formed.

  Here, the film thickness of the second gate insulating film 6 is set to be thinner (about half) than the film thickness of the first gate insulating film 5. Therefore, as shown in FIG. 5, the breakdown voltage (dotted line) of the second gate insulating film 6 used for the NMOS diode element is higher than the breakdown voltage (solid line) of the first gate insulating film 5 used for the NMOS transistor element. Low. Due to this characteristic difference, when a charge-up occurs during the diffusion process, the charge-up is performed from the second gate insulating film 6 of the NMOS diode element before the first gate insulating film 5 of the NMOS transistor reaches the breakdown voltage. Since the generated charge escapes, the first gate insulating film 5 of the NMOS transistor can be prevented from being broken.

  In FIG. 5, in the case of NMOS, the positive gate insulating film withstand voltage is higher than the negative withstand voltage when the positive voltage is applied to the gate electrode 7 and the P-type well 2 and the first gate. This is because the interface of the insulating film 5 is depleted. On the other hand, when a negative voltage is applied to the gate electrode 7, holes are accumulated at the interface between the P-type well 2 and the first gate insulating film 5.

  By the way, the breakdown voltage of the first gate insulating film 5 in the positive direction is increased because depletion occurs at the interface between the P-type well 2 and the first gate insulating film 5, and the source / drain diffusion layer 8 (FIG. Note that since the depletion does not occur between 6) and the gate electrode 7, the breakdown voltage does not increase.

  In general, the diffusion layer type diode element prevents charge-up damage during the diffusion process, but the use of the MOS type diode element has two advantages. The first point is that the breakdown voltage can be easily set low, and the second point is that the MOS type transistor element and the MOS type diode element can be electrically connected in the gate electrode forming step, and the steps after the gate electrode forming step. It is possible to prevent charge-up damage during the diffusion process.

On the other hand, in the case of using the diffusion layer type diode element, the gate electrode 7 of the MOS type transistor element and the diffusion layer type diode element cannot be electrically connected until the first layer metal wiring process. Since charge-up damage during the diffusion process cannot be prevented until the first-layer metal wiring process, it may be a fatal problem depending on the device.
JP-A-5-67777

  However, in the above-described conventional example, since the withstand voltage on the positive voltage side of the first gate insulating film 5 is high, the gate insulating film on the source / drain diffusion layer cannot be protected.

  Accordingly, in view of the above, an object of the present invention is to provide a semiconductor device having high charge-up protection performance during the process of a MOS transistor element by protecting the gate insulating film on the source / drain diffusion layer of the MOS transistor element. It is to be.

  In order to solve the above problems, a semiconductor device according to a first aspect of the present invention includes a semiconductor element such as a CMOS diode element. Specifically, the first conductivity type first well region, the first conductivity type second well region, and the second conductivity region formed on the semiconductor substrate are electrically insulated and separated from each other. A third well region of the type, a MOS transistor element having a source / drain diffusion layer, a first gate insulating film and a first gate electrode formed in the first well region, and the second A first MOS type semiconductor element having a second gate insulating film and a second gate electrode formed in the well region, and a third gate insulating film formed in the third well region And a second MOS type semiconductor element having a third gate electrode, the withstand voltage of the second and third gate insulating films is set lower than the withstand voltage of the first gate insulating film, , Second and third gates They are electrically connected to each other.

  According to a second aspect of the present invention, a second conductivity type first well region, a first conductivity type second well region, and a second conductivity region are formed on a semiconductor substrate and are electrically insulated from each other. A third well region of conductivity type; a MOS transistor element having a source / drain diffusion layer, a first gate insulating film and a first gate electrode formed in the first well region; A first MOS type semiconductor device having a second gate insulating film and a second gate electrode formed in the second well region, and a third gate insulating formed in the third well region. A second MOS type semiconductor element having a film and a third gate electrode, wherein the withstand voltage of the second and third gate insulating films is set lower than the withstand voltage of the first gate insulating film, 1, 2 and 3 Over gate electrode are electrically connected to each other.

  The semiconductor device according to claim 3 is the semiconductor device according to claim 1 or 2, wherein the first gate insulating film has a trap characteristic, and includes the first gate insulating film and the first gate electrode. The MOS type transistor is a charge trap type memory element.

  According to the first aspect of the present invention, the MOS transistor element formed in the first conductivity type first well region and the first conductivity type second well region are formed. A first MOS type semiconductor element and a second MOS type semiconductor element formed in a second well type third well region, and the second and second MOS type semiconductor elements of the first and second MOS type semiconductor elements. 3 is set lower than that of the first gate insulating film of the MOS transistor element, and the first, second and third gate electrodes are electrically connected to each other. The voltage applied to the gate insulating film on the source / drain diffusion layer of the MOS transistor element can be relaxed. That is, when a positive voltage is applied to the gate electrode of the NMOS transistor element, the breakdown voltage of the gate insulating film of the PMOS semiconductor element is the lowest, so that a current flows between the gate electrode of the PMOS semiconductor element and the N-type well, The gate electrode of the NMOS transistor element and the first gate insulating film between the source / drain diffusion layers are protected from charge-up breakdown. Therefore, it is possible to prevent the gate insulating film from being broken on the source / drain diffusion layer due to charge-up during the process.

  According to the semiconductor device of the second aspect of the present invention, the MOS transistor element formed in the second well type first well region and the first conductive type second well region are formed. A first MOS type semiconductor element and a second MOS type semiconductor element formed in a second well type third well region, and the second and second MOS type semiconductor elements of the first and second MOS type semiconductor elements. 3 is set lower than that of the first gate insulating film of the MOS transistor element, and the first, second and third gate electrodes are electrically connected to each other. The voltage applied to the gate insulating film on the source / drain diffusion layer of the MOS transistor element can be relaxed. That is, when a negative voltage is applied to the gate electrode of the PMOS transistor element, the breakdown voltage of the NMOS diode element is the lowest, so that a current flows between the gate electrode of the NMOS diode element and the P well, and the PMOS transistor element The first gate insulating film between the gate electrode and the source / drain diffusion layer is protected from charge-up breakdown. Therefore, it is possible to prevent the gate insulating film from being broken on the source / drain diffusion layer due to charge-up during the process.

  According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the first gate insulating film has a trap characteristic, and the MOS transistor having the first gate insulating film and the first gate electrode is A charge trap memory element is preferred.

  Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a current characteristic diagram of a gate insulating film.

  First, as shown in FIG. 1, in the semiconductor device of this embodiment, a P-type well 2 and an N-type well 3 that are electrically isolated from each other are formed on a P-type semiconductor substrate 1. An NMOS type transistor element composed of the first gate insulating film 5 and the gate electrode 7 is formed thereon, and an NMOS type diode element composed of the second gate insulating film 6 and the gate electrode 7 is formed on the P type well 2. On the N-type well 3, a PMOS-type diode element composed of the second gate insulating film 6 and the gate electrode 7 is formed. The film thickness of the second gate insulating film 6 is set to be thinner (about half) than the film thickness of the first gate insulating film 5. For this reason, the breakdown voltage of the second gate insulating film 6 is set lower than the breakdown voltage of the first gate insulating film 5.

  As described above, the present embodiment is characterized in that the gate electrode 7 of the NMOS transistor element is electrically connected to the gate electrode 7 of the NMOS diode element and the PMOS diode element.

  Hereinafter, as an example, the semiconductor device according to the present embodiment will be specifically described with reference to FIG.

  In the case of a 0.18 μm level CMOS device, the first gate insulating film 5 has a thickness of about 3.5 nm and the second gate insulating film 6 has a thickness of about 1.8 nm with respect to a power supply voltage of 1.8 V. Is set.

  Here, when a positive charge-up occurs during the manufacturing process, since the withstand voltage (one-dot chain line) of the PMOS diode element is the lowest, a current flows between the gate electrode 7 of the PMOS diode element and the N-type well 3. The first gate insulating film 5 between the gate electrode 7 of the NMOS transistor element and the source / drain diffusion layer 8 (FIG. 6) is protected from charge-up breakdown.

  In the case of PMOS, when a positive voltage is applied to the gate electrode 7, electrons are accumulated at the interface between the N-type well 3 and the first gate insulating film 5.

  Further, when a negative charge-up occurs during the manufacturing process, since the breakdown voltage (dotted line) of the NMOS diode element is the lowest, a current flows between the gate electrode 7 of the NMOS diode element and the P-type well 2, First gate insulating film 5 between gate electrode 7 of NMOS transistor element and source / drain diffusion layer 8 (FIG. 6) and first gate insulation between gate electrode 7 of NMOS transistor element and P type well 2 Film 5 is protected from charge-up destruction.

  As described above, since the CMOS type diode elements are connected, it is possible to sufficiently protect against both charge-up breakdown in both the positive direction and the negative direction.

  Hereinafter, a second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a cross-sectional view of the semiconductor device according to the second embodiment of the present invention.

  First, as shown in FIG. 3, in the semiconductor device of this embodiment, a P-type well 2 and an N-type well 3 that are electrically isolated from each other are formed on a P-type semiconductor substrate 1. A PMOS transistor element composed of the first gate insulating film 5 and the gate electrode 7 is formed thereon, and an NMOS diode element composed of the second gate insulating film 6 and the gate electrode 7 is formed on the P type well 2. On the N-type well 3, a PMOS-type diode element composed of the second gate insulating film 6 and the gate electrode 7 is formed. The film thickness of the second gate insulating film 6 is set to be thinner (about half) than the film thickness of the first gate insulating film 5. For this reason, the breakdown voltage of the second gate insulating film 6 is set lower than the breakdown voltage of the first gate insulating film 5.

  As described above, the present embodiment is characterized in that the gate electrode 7 of the PMOS transistor element is electrically connected to the gate electrode 7 of the NMOS diode element and the PMOS diode element.

  Also in this case, since the CMOS type diode element is connected, as in the case of the example described in the first embodiment, if a positive charge-up occurs during the manufacturing process, the PMOS type diode element 2 has the lowest withstand voltage (dashed line) (FIG. 2), a current flows between the gate electrode 7 of the PMOS diode element and the N-type well 3, and the gate electrode 7 of the PMOS transistor element and the source / drain diffusion layer 8 ( The first gate insulating film 5 during FIG. 6) is protected from charge-up breakdown.

  In the case of PMOS, when a positive voltage is applied to the gate electrode 7, electrons are accumulated at the interface between the N-type well 3 and the first gate insulating film 5.

  Also, when negative charge-up occurs during the manufacturing process, the NMOS diode element has the lowest withstand voltage (dotted line), so that a current flows between the gate electrode 7 of the NMOS diode element and the P-type well 2, A first gate insulating film 5 between the gate electrode 7 of the PMOS transistor element and the source / drain diffusion layer 8 (FIG. 6) and a first gate insulation between the gate electrode 7 of the PMOS transistor element and the P type well 2 Film 5 is protected from charge-up destruction.

  As described above, since the CMOS type diode elements are connected, it is possible to sufficiently protect against both charge-up breakdown in both the positive direction and the negative direction.

  In the first and second embodiments described above, the MOS transistor element to be protected has been described using a normal gate insulating film. However, the protected MOS transistor element has a trap characteristic. A charge trap type memory element using a gate insulating film having the above may be used. In this case, the gate insulating film breakdown voltage of the charge trap memory element is defined by a voltage at which charge starts to be trapped.

  In the first and second embodiments described above, the gate electrodes of the NMOS type diode element and the PMOS type diode element are described as being formed from the same conductive film. It doesn't matter.

  Further, the gate electrodes of the MOS transistor element and the MOS diode element may be connected not in the gate electrode formation process but in the metal wiring process.

  Further, the MOS type diode element may be a MOS type transistor element having a source / drain diffusion layer.

  In the first and second embodiments described above, it has been described that the gate insulating films of the NMOS diode element and the PMOS diode element are formed from the same insulating film. 2 gate insulating film and third gate insulating film).

  Further, the gate insulating films of the NMOS diode element and the PMOS diode element may have different film thicknesses as long as they are thinner than the gate insulating film of the MOS transistor element to be protected.

  In the first embodiment, the NMOS diode element is another P-type well (second well region electrically isolated from the first well region) that is electrically insulated from the NMOS transistor element. ) Or in a deep N-type well.

  According to the semiconductor device of the present invention, the semiconductor device of the present invention can relieve the voltage applied to the gate insulating film on the source / drain diffusion layer of the MOS transistor element, and the source / drain diffusion by charge-up during the process. It is possible to prevent the gate insulating film on the layer from being broken, and is useful for a semiconductor device or the like that reduces charge-up damage during the process.

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a current characteristic diagram of a gate insulating film corresponding to FIG. 1. It is sectional drawing of the semiconductor device of the 2nd Embodiment of this invention. It is sectional drawing of the semiconductor device of a prior art example. FIG. 5 is a current characteristic diagram of the gate insulating film corresponding to FIG. 4. It is a gate length direction sectional view of a MOS transistor.

Explanation of symbols

1 P-type semiconductor substrate 2 P-type well 3 N-type well 4 Element isolation film 5 First gate insulating film 6 Second gate insulating film 7 Gate electrode 8 Source / drain diffusion layer

Claims (3)

A first conductivity type first well region, a first conductivity type second well region, and a second conductivity type third electrically isolated from each other and formed on the semiconductor substrate. The well region,
A MOS transistor element having a source / drain diffusion layer, a first gate insulating film and a first gate electrode formed in the first well region;
A first MOS type semiconductor element having a second gate insulating film and a second gate electrode formed in the second well region;
A second MOS type semiconductor element having a third gate insulating film and a third gate electrode formed in the third well region;
The withstand voltage of the second and third gate insulating films is set lower than the withstand voltage of the first gate insulating film;
The semiconductor device, wherein the first, second and third gate electrodes are electrically connected to each other. A second conductivity type first well region, a first conductivity type second well region and a second conductivity type third well region which are formed on a semiconductor substrate and are electrically isolated from each other;
A MOS transistor element having a source / drain diffusion layer, a first gate insulating film and a first gate electrode formed in the first well region;
A first MOS type semiconductor element having a second gate insulating film and a second gate electrode formed in the second well region;
A second MOS type semiconductor element having a third gate insulating film and a third gate electrode formed in the third well region;
The withstand voltage of the second and third gate insulating films is set lower than the withstand voltage of the first gate insulating film;
The semiconductor device, wherein the first, second and third gate electrodes are electrically connected to each other.   3. The semiconductor device according to claim 1, wherein the first gate insulating film has a trap characteristic, and the MOS transistor having the first gate insulating film and the first gate electrode is a charge trap memory element. .

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