JP2009278031A - Production process of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a production process of a semiconductor device for restricting an inverse short channel effect and reducing a threshold voltage of a transistor. <P>SOLUTION: In the production process of the semiconductor device, a base 1 having a p-type semiconductor region 2 with nitrogen implanted in the upper face thereof is prepared, and a gate insulating film 5 and a gate electrode 6 are laminated in order sequentially on the base 1. Then, with the gate electrode 6 as a mask of, a pair of n-type source and drain regions 10 is formed in a pair of p-type pocket implantation regions 7 and out of the pocket implantation regions 7 on the upper face of the base 1. Then, a stress film 11, which applies stress to the base 1 under the gate insulating film 5 by covering the upper portion of the base 1, is laminated. After activating the source and drain region 10 by applying annealing to the base 1, the laminated stress film 11 is removed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a MOS transistor.

  Conventionally used MOS (Metal Oxide semiconductor) transistors having a gate electrode made of silicon have a problem that effective capacitance is reduced due to carrier depletion at the interface with the insulating film. For this reason, a metal gate transistor structure has been proposed in order to avoid depletion of the gate.

  However, when a metal gate such as a fully silicided (FUSI) gate is used, the work function (WF: Work Function) of the electrode material becomes near the center of the Si band gap after a high temperature process. . As a result, the threshold voltage (Vth) becomes a high value, which is an obstacle in manufacturing a high-performance transistor.

  In contrast to the above problem that the threshold voltage becomes higher than a practical level, in the conventional NMOS, the threshold voltage is reduced by implanting nitrogen into the substrate. This is because when the nitrogen distributed in the gate insulating film replaces part of the oxygen in the gate insulating film, donor-type levels are generated in the vicinity of the interface between the gate insulating film and the silicon substrate. Is considered to be positively charged. A technique related to the above-described content is disclosed in Non-Patent Document 1 below.

Y. Okayama et al, “Symp. On VLSI tech”, 2006, “Suppression effects of threshold voltage variation with NiFUSI gate electrode for 45 nm node and beyond LSTP and SRAM devices”, pp. 118-119

  However, when the threshold voltage (Vth) is reduced by implanting nitrogen into the substrate, the reverse short channel effect (a phenomenon in which the threshold voltage increases once before the short channel effect becomes significant) increases. . Therefore, when the threshold voltage is adjusted with the gate length (Lg) of the target with the reverse short channel effect increased, the threshold voltage becomes too high in the region where Lg is large, thereby reducing the circuit operation margin. There was a problem that.

  The reason why the reverse short channel characteristic becomes large is that Vth in the region where Lg is small is Pocket injection (impurity of the same type as that of the channel impurity obliquely with respect to the gate electrode) to suppress the depletion layer from protruding from the drain. This is because Vth does not decrease compared to a region where Lg is large.

  Accordingly, the present invention has been made to solve such a problem, and an object of the present invention is to obtain a method for manufacturing a semiconductor device capable of suppressing the reverse short channel effect and reducing the threshold voltage of the transistor. To do.

  In one embodiment of the present invention, a method of manufacturing a semiconductor device includes preparing a base having a p-type semiconductor region into which nitrogen is implanted into an upper surface, and laminating a gate insulating film and a gate electrode on the base in this order. Form. Next, using the gate electrode as a mask, a pair of p-type pocket implantation regions and a pair of n-type source / drain regions outside the pocket implantation region are formed in the upper surface of the base. Next, a stress film is applied to cover the base and apply stress to the base under the gate insulating film. Next, after heat-treating the base to activate the source / drain regions, the stacked stress film is removed.

  According to the method for manufacturing a semiconductor device in one embodiment of the present invention, by applying stress to the Pocket injection layer using the SMT technique, segregation of channel impurities during activation annealing is suppressed, and a remarkable reverse of NMOS is achieved. Short channel characteristics can be avoided.

<Embodiment 1>
FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor device according to the first embodiment of the present invention. A method for manufacturing a semiconductor device in the present embodiment will be described below with reference to FIG.

  First, a semiconductor substrate 1 having an NMOS transistor formation region (hereinafter referred to as an NMOS region) is prepared, and well implantation is performed in the semiconductor substrate 1 in the NMOS region to form a p-type well 2. Next, nitrogen is implanted into the p-type well 2 to form a nitrogen implanted layer 3. Similarly, a p-type impurity (boron (B) is used in this embodiment) is implanted into the p-type well 2 to form the channel injection layer 4 (FIG. 1A).

  Next, a gate insulating film 5 and a metal electrode 6 (gate electrode) are stacked in this order on the upper surface of the semiconductor substrate 1. Next, using the metal electrode 6 as a mask, a p-type impurity (boron is used in the present embodiment) is implanted into the p-type well 2 from an oblique direction with respect to the metal electrode 6 to form the Pocket injection layer 7. Further, an extension region 8 is formed by implanting n-type impurities. Next, a side wall 9 is formed on the side surface of the metal electrode 6, and an n-type impurity is implanted into the p-type well 2 using the metal electrode 6 and the side wall 9 as a mask to form source / drain regions 10 ( FIG. 1 (b)).

  Next, a tensile stress film using an SMT (Stress Memorization Technique) technique is formed in order to apply stress to the semiconductor substrate 1 and suppress diffusion of the Pocket injection layer 7. Specifically, an oxide film 11 (stress film) is deposited several nanometers to several hundred nanometers so as to cover the semiconductor substrate 1, the gate electrode 6, and the sidewalls 9, and then activation annealing such as RTA is performed (FIG. 1 ( c)).

  Here, FIG. 2 shows the activity when the tensile stress film (oxide film 11) is not formed (FIG. 2A) and when the tensile stress film (oxide film 11) is formed (FIG. 2B). It is the figure which compared the mode of the spreading | diffusion of the Pocket injection | pouring layer 7 after a heat treatment annealing. As shown in FIG. 2, by performing the activation annealing process after forming the tensile stress film (oxide film 11), the stress is applied to the Pocket injection layer 7, and the diffusion generated during the activation annealing can be suppressed.

  Next, the oxide film 11 is removed, and silicide treatment is performed on the source / drain regions 10 to form silicide 12 (FIG. 1D). After that, the transistor is formed by a normal flow, and the description is omitted.

  3 is a graph comparing the threshold voltage characteristics of the gate length in the conventional transistor (Tr. 2) without nitrogen implantation and the transistor (Tr. 1) with nitrogen implantation. Here, Tr. 1, Tr. In both cases, the SMT process described above is not performed. As shown in FIG. 3, it can be seen that the threshold voltage can be reduced by performing nitrogen implantation under the gate insulating film 5 to form the nitrogen implanted layer 3.

  However, as shown in FIG. In the case of 1, the threshold voltage increase (threshold voltage difference between Lg1 and Lg2: ΔVt1) before the short channel effect becomes significant when the gate length is shortened is Tr. It can be seen that the threshold voltage increase (ΔVt2) in the case of 2 is large, that is, the reverse short channel effect is large. Therefore, if the threshold voltage is matched with the gate length (Lg1) of the Target in this state, the threshold voltage becomes too high in a region where Lg is large, thereby reducing the circuit operation margin.

  On the other hand, FIG. 1 and Tr. 1 is a graph comparing threshold voltage characteristics in terms of gate length in a transistor (Tr. 3) using SMT technology. As shown in the figure, it can be seen that the increase in threshold voltage (ΔVt3) before the short channel effect becomes significant is decreased with respect to ΔVt1. That is, reverse short channel characteristics can be suppressed by applying stress using the SMT technique and suppressing diffusion of the Pocket injection layer 7.

  As described above, according to the method of manufacturing a semiconductor device in the present embodiment, by applying stress to the Pocket injection layer 7 using the SMT technique, segregation of channel impurities during activation annealing is suppressed, and the NMOS becomes prominent. A reverse short channel characteristic can be avoided.

<Embodiment 2>
FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device in the second embodiment of the present invention. With reference to FIG. 5, a method of manufacturing a semiconductor device in the present embodiment will be described. First, the process up to the step of forming the silicide 12 in the source / drain region 10 (FIG. 5A) is the same as the manufacturing process of FIG. However, in this embodiment, the poly electrode 21 is used as the gate electrode. Further, when the silicide 12 is formed in the source / drain region 10, a hard mask 22 is formed on the poly electrode 21 in order to protect it from silicidation.

  Next, the insulating film 23 between the contact layers is deposited (FIG. 5B). Thereafter, the insulating film 23 is removed by CMP or the like until the surface of the poly electrode 21 is exposed, and a metal film 24 (Ni is used in this embodiment) is sputtered on the upper surface (FIG. 5C). Next, the poly electrode 21 is fully silicided by performing heat treatment by RTA, and the FUSI electrode 25 is formed. Thereafter, excess Ni is removed (FIG. 5D). After that, the transistor is formed by a normal flow, and the description is omitted.

  As described above, according to the method of manufacturing a semiconductor device in the present embodiment, even when the FUSI electrode 25 is used, stress is applied to the Pocket injection layer 7 using the SMT technique, as in the first embodiment. As a result, segregation of channel impurities during activation annealing is suppressed, and remarkable reverse short channel characteristics of NMOS can be avoided.

<Embodiment 3>
FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the third embodiment of the present invention. With reference to FIG. 6, the manufacturing method of the semiconductor device in the present embodiment will be described. First, the process up to the step of forming the source / drain region 10 (FIG. 6A) is the same as the manufacturing process up to FIG. Here, in the present embodiment, the poly electrode 21 is used as the gate electrode, but the metal electrode 6 may be used.

  Next, a tensile stress film using an SMT technique is formed in order to suppress diffusion of the Pocket injection layer 7. Specifically, an oxide film 31 is deposited from several nm to several hundred nm so as to cover the semiconductor substrate 1, the poly electrode 21, and the sidewall 9, and then several tens of plasma nitride films 32 (stress films) are formed on the oxide film 31. Deposits from nm to several hundred nm. Thereafter, activation annealing such as RTA is performed (FIG. 6B). Here, since oxide film 31 is used not as a stress film but as a stopper film, a film thinner than oxide film 11 of the first and second embodiments is formed. After that, the same processing as in the second embodiment is performed to form a semiconductor device having the FUSI electrode 25 (FIG. 6C).

  As described above, according to the method of manufacturing a semiconductor device in the present embodiment, the stress applied to the Pocket injection layer 7 using the SMT technique is applied to the plasma nitride film 32 as the stress film, as compared with the case of the first embodiment. Can also increase. Therefore, segregation of channel impurities during activation annealing is further suppressed, and the remarkable reverse short channel characteristics of NMOS can be avoided.

<Embodiment 4>
FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device in the fourth embodiment of the present invention. Hereinafter, a method for manufacturing a semiconductor device according to the present embodiment will be described with reference to FIG.

  First, the element isolation region 41 is formed in the surface of the semiconductor substrate 1 to partition the NMOS region and the PMOS region. Thereafter, the process up to the step of forming the source / drain region 10 in the NMOS region is the same as in the first to third embodiments, and thus the description thereof is omitted. On the other hand, the same processing as in the NMOS region is performed in the PMOS region. However, the injection layer 43 formed in the n-type well 42 is formed by implanting, for example, a halogen element. The extension region 49 and the source / drain region 51 are formed by implanting p-type impurities. The channel injection layer 44 and the Pocket injection layer 48 are formed by implanting n-type impurities (FIG. 7A).

  Next, a tensile stress film using an SMT technique is formed in order to suppress diffusion of the Pocket injection layer 7 in the NMOS region. However, when the SMT process is applied to the PMOS region, there is a phenomenon in which the edge component of the gate leak increases due to the application of stress to the gate edge portion. Therefore, the SMT process is used only in the NMOS region. Specifically, an oxide film 52 is deposited on the semiconductor substrate 1, the poly electrodes 21 and 46, and the side walls 9 and 50 so as to cover several nanometers to several hundred nanometers. ) Several tens nm to several hundreds nm (FIG. 7B). Next, the plasma nitride film 53 in the PMOS region is removed, and activation annealing such as RTA is performed (FIG. 7C). Here, since oxide film 52 is used not as a stress film but as a stopper film, a film thinner than oxide film 11 of the first and second embodiments is formed. Thereafter, the same processing as in the second embodiment is performed to form a semiconductor device having the FUSI electrodes 25 and 54 (FIG. 7D).

  As described above, the same effects as in the third embodiment can be obtained, and adverse effects on the PMOS region such as an increase in gate leakage caused by using the SMT process can be avoided.

It is sectional drawing which showed the manufacturing process of the semiconductor device in Embodiment 1 of this invention. It is the figure which showed the mode of the spreading | diffusion of the Pocket injection | pouring layer after activation annealing treatment in this invention and the conventional semiconductor device. It is a figure which showed the characteristic of the threshold voltage in gate length in the semiconductor device which performs nitrogen implantation, and the semiconductor device which does not perform nitrogen implantation. FIG. 11 is a diagram showing threshold voltage characteristics in gate lengths in the present invention and the conventional semiconductor device. It is sectional drawing which showed the manufacturing process of the semiconductor device in Embodiment 2 of this invention. It is sectional drawing which showed the manufacturing process of the semiconductor device in Embodiment 3 of this invention. It is sectional drawing which showed the manufacturing process of the semiconductor device in Embodiment 4 of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 p-type well, 3 Nitrogen injection layer, 4,44 Channel injection layer, 5,45 Gate insulating film, 6 Metal electrode, 7,48 Pocket injection layer, 8,49 extension region, 9,50 Side wall 10, 51 source / drain region, 11, 31, 52 oxide film, 12 silicide, 21, 46 poly electrode, 22, 47 hard mask, 23 insulating film, 24, 54 FUSI electrode, 32, 53 plasma nitride film, 41 Element isolation region, 42 n-type well, 43 implantation layer.

Claims (5)

(A) preparing a base having a p-type semiconductor region implanted with nitrogen in the upper surface;
(B) forming a gate insulating film and a gate electrode by stacking in this order on the base;
(C) using the gate electrode as a mask, forming a pair of p-type pocket implantation regions and a pair of n-type source / drain regions outside the pocket implantation region in the upper surface of the base;
(D) After the step (c), laminating a stress film that covers the base and applies stress to the base under the gate insulating film;
(E) after the step (d), heat-treating the base to activate the source / drain regions;
(F) After the step (e), a step of removing the laminated stress film is provided.   The method of manufacturing a semiconductor device according to claim 1, wherein in the step (d), an oxide film is stacked as the stress film. (G) The method further includes a step of laminating an oxide film covering the base between the step (c) and the step (d),
In the step (d), a plasma nitride film is laminated as the stress film,
The method of manufacturing a semiconductor device according to claim 1, wherein the step (f) removes the stacked oxide film and plasma nitride film.   The method of manufacturing a semiconductor device according to claim 1, wherein in the step (b), a metal gate electrode is stacked as the gate electrode. In the step (b), a poly gate electrode is stacked as the gate electrode,
(H) After the step (f), a step of laminating a metal film on the semiconductor substrate;
4. The method of manufacturing a semiconductor device according to claim 1, further comprising: (i) reacting the metal film with the gate electrode to silicidize the entire region of the poly gate electrode. 5.

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