JP2006093504A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To decrease a man-hour and to suppress electric field concentration by forming trenches in the same step as that of an element area when an MOSFET has the element region in trench structure. <P>SOLUTION: Trenches 7 and 8 are provided at ends of a channel layer 4, trench internal walls are coated with insulating film, and polysilicon is charged. Consequently, the need for a guard ring is eliminated and the curvature of a depletion layer at the channel layer end part is reduced to suppress electric field concentration. The trenches 7 and 8 at the channel layer end part are as deep as or deeper than a trench of a cell part for effective suppression of electric field concentration, and the opening width in trench formation is made wider than the element area to form the trenches 7 and 8 deeper than the element area through the same trench forming step. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device that eliminates a guard ring and alleviates electric field concentration at an end portion of a channel layer and a manufacturing method thereof.

  FIG. 8 shows a cross-sectional view of the vicinity of the peripheral region of a conventional semiconductor device. The semiconductor device is, for example, a MOSFET having an element region 51 in which a number of trench-structure transistor cells 52 are provided in a channel layer 34.

  The channel layer 34 is a region in which an n− type semiconductor layer 32 is provided on an n + type semiconductor substrate 31 and p-type impurities are diffused on the surface thereof. A guard ring 33 is provided at the end of the channel layer 34.

  The guard ring 33 is a region of the same conductivity type as that of the channel layer 34 deeper than the channel layer 34, and relaxes electric field concentration at the end of the channel layer 34 (see, for example, Patent Document 1).

  A conventional method for manufacturing a semiconductor device will be described with reference to FIGS. The MOSFET includes a drain region 32 made of an n− type epitaxial layer on an n + type silicon semiconductor substrate 31. A mask 35s having an opening at the end of the channel layer is provided, and high-concentration p-type impurities are implanted and diffused to form the guard ring 33 (FIG. 9A). Next, a new mask 35s having an opening in the formation region of the channel layer is provided, and a channel layer 34 is formed by ion implantation and diffusion of p-type impurities (FIG. 9B). Thereafter, a trench 37 that penetrates the channel layer 34 and reaches the drain region 32 is formed (FIG. 9C).

Further, the inner wall of the trench 37 is covered with a gate oxide film 41, and a gate electrode 43 made of polysilicon filled in the trench 37 is provided. An N ⁺ -type source region 45 is formed on the surface of the channel layer 34 adjacent to the trench 37. A P ⁺ -type body region 44 is provided on the surface of the channel layer 34 between the source regions 45 of two adjacent cells and on the outer periphery of the element region (FIG. 10A).

The gate electrode 43 is covered with an interlayer insulating film 46, a source electrode 47 that contacts the source region 45 and the body region 44 is provided, and an element region 51 in which a large number of cells 52 of MOS transistors are arranged is formed. Further, the gate connection electrode 48 is formed when the source electrode 47 is formed (FIG. 10B).
JP 2004-31386 A (FIG. 4)

  In the MOSFET having the trench structure, the trench 37 is formed to the minimum necessary depth in order to reduce the capacitance. That is, the channel layer 34 is also formed to a depth corresponding to the trench 37. However, since the channel layer 34 is a diffusion region, the curvature at the end of the channel layer 34 becomes tight if the depth is small. Further, the curvature of the depletion layer extending from the channel layer 34 becomes tight, and electric field concentration is likely to occur.

  Therefore, as shown in FIG. 8, in the conventional MOSFET, the guard ring 33 is formed to reduce the curvature of the depletion layer at the end of the channel layer 34 in order to reduce the electric field concentration at the end of the channel layer 34. However, in order to relax the curvature, it is desirable to form the guard ring 33 deeper than the channel layer 34, and it is necessary to form the deep guard ring 33 before forming the channel layer 34 as described above.

  For this reason, a guard ring 33 forming step is required before the element region 51 is formed, and a mask is also required separately.

  The present invention has been made in view of the above problems. First, a reverse conductivity type semiconductor layer provided on one conductivity type semiconductor substrate, a plurality of transistor cells provided in the reverse conductivity type semiconductor layer, and the reverse polarity A trench provided through the opposite conductivity type semiconductor layer at an end of the conductivity type semiconductor layer, an insulating film provided along the trench, and a conductive material embedded in the trench, The problem is solved by applying a voltage to the conductive material.

  Second, a reverse conductivity type channel layer provided on one conductivity type semiconductor substrate, a number of MOS transistor cells provided in the channel layer, and an end of the channel layer penetrating the channel layer. And solving by applying a gate voltage of the MOS transistor to the conductive material, comprising a trench provided along the trench, an insulating film provided along the trench, and a conductive material embedded in the trench It is.

  Third, a reverse conductivity type channel layer provided on the one conductivity type semiconductor substrate, a first trench provided through the channel layer at an end of the channel layer, and along the first trench An insulating film provided in the first trench, a conductive material embedded in the first trench, and a MOS transistor cell configured by providing a plurality of second trenches in the channel layer. This is solved by applying a gate voltage of

  Further, the first trench has a depth equal to or greater than that of the second trench.

  Fourth, there is provided a method of manufacturing a semiconductor device in which a reverse conductivity type channel layer is formed on the surface of a one conductivity type semiconductor substrate, and a plurality of MOS transistor cells are formed in the channel layer. A step of forming a trench penetrating the channel layer, a step of forming an insulating film on the inner wall of the trench, a step of embedding a conductive material in the trench, and electrically connecting the conductive material and the gate electrode of the MOS transistor And a step of connecting to the device.

  Fifth, a step of forming a reverse conductivity type channel layer on the surface of the one conductivity type semiconductor substrate, a first trench is formed at an end of the channel layer, and a number of the channel layers surrounded by the first trench are formed. Forming a second trench, forming an insulating film on the inner walls of the first trench and the second trench, burying a conductive material in the first trench and the second trench, and the second trench A step of diffusing predetermined impurities in the periphery to form a MOS transistor cell; and a step of electrically connecting the conductive material embedded in the first trench and the gate electrode of the MOS transistor. It is a solution.

  The opening width of the first trench may be equal to or wider than the opening of the second trench.

  According to the structure of the present invention, the curvature of the depletion layer at the channel layer end can be relaxed and the electric field concentration can be suppressed by the trench provided at the channel layer end. Therefore, since the guard ring which is a wide diffusion region is not necessary, it contributes to the expansion of the operation area and the on-resistance can be reduced. In addition, a guard ring mask is not required, and costs can be reduced.

  Moreover, according to the manufacturing method of the present invention, the guard ring forming step is not required. By eliminating the step of forming a guard ring that is a deep diffusion region, throughput is improved. In particular, when the element region is a MOSFET having a trench structure, it can be formed in the same process as the element region. Therefore, it is possible to provide a method for manufacturing a semiconductor device that reduces the number of processes and suppresses electric field concentration.

  Furthermore, electric field concentration can be further reduced by making the trench part deeper than the MOS transistor cell in the element region. In this case, by making the mask opening width for forming the first trench constituting the trench portion wider than the mask opening width for forming the second trench constituting the MOS transistor, the first trench deeper than the second trench is formed in the same process. Can be formed.

  The embodiment of the present invention will be described in detail by taking as an example the case where an n-channel trench MOSFET is formed in an element region.

  FIG. 1 shows a structure of a semiconductor device of the present invention. 1A is a plan view of the chip, and FIG. 1B is a cross-sectional view taken along the line AA. 1B is a plan view of the corresponding portion.

  A large number of MOS transistor cells 25 are arranged in the element region 21. The source electrode 17 is provided in connection with the source region of each cell 25 on the element region 21. The gate connection electrode 18 is connected to the gate electrode 13 b and is disposed around the element region 21. The gate connection electrode 18 is connected to the gate pad electrode 18p.

  As shown in the cross-sectional view of FIG. 1B, the MOSFET cell 25 is formed in the p-type channel layer 4 provided on the surface of the n + type silicon layer 1 provided with the n− type epitaxial layer 2 serving as the drain region. The A trench portion 23 surrounding the outer periphery of the element region 21 is provided at the end of the channel layer 4 (details will be described in detail). The gate electrode 13 b of each cell 25 is drawn out of the element region 21 by the connecting portion 13 c and connected to the gate connecting electrode 18. The gate connection electrode 18 is connected to the gate pad electrode 18p and applies a gate voltage to each cell 25.

  Each MOSFET cell 25 includes semiconductor substrates 1 and 2, a channel layer 4, a second trench 8, a gate insulating film 11 b, a gate electrode 13 b, a source region 15, and a body region 14.

  The semiconductor substrate is obtained by laminating an n− type epitaxial layer that becomes the drain region 2 on an n + type silicon semiconductor substrate 1. The channel layer 4 is a diffusion region in which p-type boron or the like is selectively implanted into the surface of the drain region 2.

  The second trench 8 passes through the channel layer 4 and reaches the drain region 2. Generally, patterning is performed on a semiconductor substrate in a lattice shape or a stripe shape.

  The gate oxide film 11b is provided at least on the inner wall of the second trench 8 in contact with the channel layer 4 to a thickness of several hundreds of inches according to the driving voltage. Since the gate oxide film 11b is an insulating film, it has a MOS structure sandwiched between the gate electrode 13b provided in the second trench 8 and the semiconductor substrate.

  The gate electrode 13 b is formed by burying a conductive material in the second trench 8. The conductive material is, for example, polysilicon, and n-type impurities, for example, are introduced into the polysilicon in order to reduce the resistance. The gate electrode 13 is drawn out onto the substrate by the connecting portion 13c and extends to the gate connecting electrode 18 surrounding the periphery of the semiconductor substrate, and the gate pad electrode 18p provided on the semiconductor substrate (see FIG. 1A). Connected to Moreover, as long as it is a conductive material, it is not limited to polysilicon into which impurities are introduced, but may be metal or the like.

  The source region 15 is a diffusion region in which an n + type impurity is implanted into the surface of the channel layer 4 adjacent to the second trench 8, and is in contact with a metal source electrode 17 covering the element region 21. Further, a body region 14 that is a diffusion region of p + -type impurities is provided on the surface of the channel layer 4 between the adjacent source regions 15 and the surface of the channel layer 4 on the outer periphery of the element region 21 to stabilize the substrate potential. As a result, a portion surrounded by the adjacent second trenches 8 becomes one cell 25 of the MOSFET, and a large number of them constitute a device region 21.

  The source electrode 17 is a metal electrode that is patterned into a desired shape by sputtering aluminum or the like through the interlayer insulating film 16, covers the element region 21, and contacts the source region 15 and the body region 14.

  The trench portion 23 includes the first trench 7, the insulating film 11a, and the conductive material 13a. The first trench 7 is formed so as to penetrate the channel layer 4 and reach the drain region 2, and the inside of the first trench 7 is covered with an oxide film 11a. The internal oxide film 11a is a thin film of about 300 to 700 mm. A polysilicon 13a doped with an impurity is embedded in the first trench 7, and the polysilicon 13a is connected to a connecting portion 13c extending above the polysilicon 13a. That is, an MIS or MOS structure is formed at the end of the channel layer 4. As will be described later, the trench portion 23 is formed in the same process as the MOS transistor in the element region 21. That is, the polysilicon 13a and the oxide film 11a in the trench portion 23 are the same films as the gate electrode 13b and the gate oxide film 11b of the MOS transistor.

  By connecting the polysilicon 13a to the connecting portion 13c, the polysilicon 13a is electrically connected to the gate electrode of the MOS transistor and has the same potential. As a result, when the gate voltage is applied, the depletion layer 50 spreads around the trench portion 23 as shown by the broken line in the figure. That is, the depletion layer 50 is pushed downward below the trench portion 23, and the curvature of the depletion layer 50 at the end of the channel layer 4 is relaxed. Therefore, electric field concentration can be suppressed without providing a guard ring.

  Here, in order to relieve the curvature of the depletion layer 50, the trench 23 is preferably deeper. For example, when the second trench 8 of the cell 25 is about 0.5 μm, the first trench of the trench portion 23 is preferably about 0.7 μm.

  The trench portion 23 is provided away from the side surface of the end portion of the channel layer 4 by a predetermined distance according to the withstand voltage. Specifically, the distance x1 from the interface between the side surface of the channel layer 4 end and the epitaxial layer 2 to the end of the trench 23 is larger than the depth d1 of the first trench 7. As a result, the breakdown voltage can be ensured as in the prior art.

  The polysilicon 13a of the trench portion 23 may be a conductive material such as metal. Further, when the MOSFET 25 and the trench portion 23 are formed in the same process, the conductive material is the same material, but different conductive materials may be used as long as they are formed in different processes. The oxide film 11a may be another insulating film.

  Further, the element region 21 is not limited to the MOSFET 25, and can be similarly implemented if it is a so-called discrete device. In particular, an element having an insulated gate trench structure such as an IGBT is preferable because the trench portion 23 can be formed by the same process as the element region 21 as described later. For example, in the case of a bipolar transistor, the trench portion 23 may be provided at the end of the base region.

  Next, a method for manufacturing a semiconductor device according to the present invention is shown in FIGS. 2 to 7 by taking an n-channel MOSFET as an example.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming a reverse conductivity type channel layer on the surface of one conductivity type semiconductor substrate, a first trench formed at an end of the channel layer, and a channel surrounded by the first trench. Forming a plurality of second trenches in the layer; forming an insulating film on the inner walls of the first and second trenches; burying a conductive material in the first and second trenches; The method includes a step of diffusing a predetermined impurity around the periphery to form a cell of the MOS transistor, and a step of electrically connecting the conductive material embedded in the first trench and the gate electrode of the MOS transistor.

  First step (FIG. 2): a step of forming a reverse conductivity type channel layer on the surface of one conductivity type semiconductor substrate.

A drain region 2 is formed by laminating an n− type epitaxial layer on the n + type silicon semiconductor substrate 1. After the thermal oxide film 5s is formed on the surface, the oxide film in the portion of the planned channel layer 4 is etched. For example, boron is implanted over the entire surface with a dose of 1.0 × 10 ¹³ cm ⁻² , and then diffused to form a P-type channel layer 4. In this embodiment, a guard ring is not necessary. Since the guard ring is a deep diffusion region, a long heat treatment time is required. In other words, if the guard ring forming process is unnecessary, the time required for the entire manufacturing process can be shortened, and the throughput can be improved. Further, since a guard ring mask is not required, the cost can be reduced.

  Second step (FIG. 3): a step of forming a first trench at the end of the channel layer and forming a number of second trenches in the channel layer surrounded by the first trench.

  A CVD oxide film 5 of NSG (Non-doped Silicate Glass) is formed on the entire surface by CVD. Thereafter, a resist mask is applied except for the opening portions of the first and second trenches. The CVD oxide film 5 is provided to cover the thermal oxide film 5s around the substrate. The CVD oxide film 5 is partially removed by dry etching to form trench openings 6b and 6a in which the channel region 4 is exposed. At this time, the trench opening 6a at the end of the channel layer 4 is formed to be equal to or wider than the inner trench opening 6b (w1 ≧ w2) (FIG. 3A). Thereafter, the resist is removed.

  Thereafter, using the CVD oxide film 5 as a mask, the silicon semiconductor substrate in the trench openings 6a and 6b is dry-etched with CF-based gas and HBr-based gas to penetrate the channel layer 4 and reach the drain region 2 and the second trenches 7 and 2 A trench 8 is formed. By making the opening width w1 of the trench opening 6a larger than the opening width w2 of the trench opening 6b, the first trench 7 depth (d1) is made deeper than the second trench 8 depth (d2) in the same etching step. It can be formed (FIG. 3B).

  One first trench 7 is provided at the end of the channel layer 4 and constitutes a trench portion 23. A large number of second trenches 8 are provided in the element region 21 to constitute a MOSFET cell 25.

  The first trench 7 is provided at a sufficient distance from the end of the side surface of the channel layer 4 in order to ensure a breakdown voltage during reverse bias. Specifically, the distance x1 from the interface between the side surface of the channel layer 4 end and the epitaxial layer 2 to the end of the trench 23 is larger than the depth d1 of the first trench 7.

  Third step (FIG. 4): a step of forming an insulating film on the inner walls of the first trench and the second trench.

  Dummy oxidation is performed to form an oxide film (not shown) on the inner walls of the first trench 7 and the second trench and the surface of the channel layer 4 to remove etching damage during dry etching. The film 5 is removed by etching.

  Further, the entire surface is oxidized to form a gate oxide film 11b on the inner wall of the second trench 8 with a thickness of about 300 to 700 mm, for example, according to the driving voltage. At the same time, an oxide film 11a is also formed on the inner wall of the first trench 7. The thermal oxide film 5s is also oxidized and fused with the thermal oxide film 5s.

  Fourth step (FIG. 5): a step of burying a conductive material in the first trench and the second trench.

  A polysilicon layer is attached to the entire surface, a mask having a predetermined pattern is provided, and dry etching is performed. The polysilicon layer may be a layer in which polysilicon containing impurities is deposited, or may be a layer in which impurities are introduced after depositing non-doped polysilicon. As a result, the gate electrode 13 b embedded in the second trench 8 is formed, and at the same time, the polysilicon 13 a is embedded in the first trench 7. The polysilicon 13a is in contact with the connecting portion 13c extending on the upper portion thereof.

  The first trench 7 at the end of the channel layer 4 becomes a trench portion 23 having a MIS (or MOS) structure by the oxide film 11a and the polysilicon 13a. The first trench 7 and the second trench 8 are not limited to polysilicon, and a conductive material such as metal may be embedded.

  Fifth step (FIG. 6): A step of forming a MOS transistor cell by diffusing a predetermined impurity around the second trench.

First, in order to stabilize the potential of the substrate, a mask made of a resist film (not shown) that exposes a portion serving as a body region is provided, and boron is selectively applied at a dose of 2.0 × 10 ¹⁵ cm ⁻² , for example. Ion implantation. A mask made of a new resist film (not shown) is provided, and arsenic is ion-implanted into the planned source region 15 at a dose of about 5.0 × 10 ¹⁵ cm ⁻² , for example.

  NSG or PSG (not shown) and BPSG (Boron Phosphorus Silicate Glass) layer 16a are deposited on the entire surface by CVD and reflowed.

As a result, the body region 14 is formed on the N ⁺ -type source region 15 and the surface of the channel layer 4 adjacent to the source region 15. A region surrounded by the second trench 8 becomes a MOSFET cell 25, and an element region 21 in which a large number of cells 25 are arranged is formed.

  The order of impurity implantation in the body region 14 and the source region 15 may be changed.

  Sixth step (FIG. 7): a step of electrically connecting the conductive material embedded in the first trench and the gate electrode of the MOS transistor.

  A mask made of a resist film is provided on the BPSG layer 16, the gate electrode 13 b of the MOS transistor is masked, a mask is provided so that a part of the gate electrode 13 c around the element region 21 is exposed, and etching is performed. Form.

  Thereafter, aluminum or the like is deposited on the entire surface by a sputtering apparatus to cover the entire surface of the element region 21 and form a source electrode 17 that contacts the source region 15 and the body region 14. At the same time, the gate connection electrode 18 is formed.

  Thereby, the polysilicon 13a of the trench portion 23 is electrically connected to the gate electrode of the MOS transistor by the gate connection electrode 18. When a gate voltage is applied to the element region 21, the depletion layer 50 spreads around the trench portion 23. The depletion layer 50 is pushed downward by the trench portion 23, whereby the curvature of the depletion layer 50 at the end of the channel layer 4 can be relaxed (see FIG. 1B).

  As described above, the embodiment of the present invention has been described by taking the n-channel MOSFET as an example. However, the present invention can be similarly applied to a MOS transistor having a conductivity type reversed.

In addition, not only MOSFET but also an insulated gate semiconductor element such as IGBT, the trench part 23 and the element region 21 can be formed at the same time, and the same effect can be obtained.

It is (A) top view and (B) sectional drawing of the semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device of this invention. It is sectional drawing explaining the conventional semiconductor device. It is sectional drawing explaining the manufacturing method of the conventional semiconductor device. It is sectional drawing explaining the manufacturing method of the conventional semiconductor device.

Explanation of symbols

1 n + type silicon semiconductor substrate 2 drain region 4 channel layer 5 CVD oxide film 5s thermal oxide film 6a, 6b trench opening 7 first trench 8 second trench 11a oxide film 11b gate oxide film 13a polysilicon 13b gate electrode 13c connecting part
DESCRIPTION OF SYMBOLS 14 Body region 15 Source region 16 Interlayer insulation film 17 Source electrode 18 Gate connection electrode 21 Element region 23 Trench part 25 Cell 31 N + type silicon semiconductor substrate 32 Drain region 33 Guard ring 34 Channel layer 37 Trench 41 Gate oxide film 43 Gate electrode 44 Body region 45 Source region 46 Interlayer insulating film 48 Gate connection electrode 51 Element region 52 Cell

Claims (7)

A reverse conductivity type semiconductor layer provided on the one conductivity type semiconductor substrate;
A plurality of transistor cells provided in the reverse conductivity type semiconductor layer;
A trench provided through the reverse conductivity type semiconductor layer at an end of the reverse conductivity type semiconductor layer;
An insulating film provided along the trench;
A conductive material embedded in the trench,
A semiconductor device, wherein a voltage is applied to the conductive material. A reverse conductivity type channel layer provided on a one conductivity type semiconductor substrate;
A plurality of MOS transistor cells provided in the channel layer;
A trench provided through the channel layer at an end of the channel layer;
An insulating film provided along the trench;
A conductive material embedded in the trench,
A semiconductor device, wherein a gate voltage of the MOS transistor is applied to the conductive material. A reverse conductivity type channel layer provided on a one conductivity type semiconductor substrate;
A first trench provided through the channel layer at an end of the channel layer;
An insulating film provided along the first trench;
A conductive material embedded in the first trench;
A MOS transistor cell configured by providing a plurality of second trenches in the channel layer;
A semiconductor device, wherein a gate voltage of the MOS transistor is applied to the conductive material.   The semiconductor device according to claim 3, wherein the first trench has a depth equal to or greater than that of the second trench. A method of manufacturing a semiconductor device, wherein a channel layer of opposite conductivity type is formed on a surface of a semiconductor substrate of one conductivity type, and a plurality of MOS transistor cells are formed in the channel layer,
Forming a trench penetrating the channel layer at an end of the channel layer;
Forming an insulating film on the inner wall of the trench;
Burying a conductive material in the trench;
And a step of electrically connecting the conductive material and the gate electrode of the MOS transistor. Forming a reverse conductivity type channel layer on the surface of one conductivity type semiconductor substrate;
Forming a first trench at an end of the channel layer, and forming a plurality of second trenches in the channel layer surrounded by the first trench;
Forming an insulating film on the inner walls of the first trench and the second trench;
Burying a conductive material in the first trench and the second trench;
Diffusing a predetermined impurity around the second trench to form a MOS transistor cell;
A method of manufacturing a semiconductor device, comprising: electrically connecting the conductive material embedded in the first trench and a gate electrode of the MOS transistor.   The method of manufacturing a semiconductor device according to claim 6, wherein the opening width of the first trench is formed to be equal to or wider than the opening of the second trench.

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