JP2006086492A - Method to form surface equivalent to semiconductor substrate in terms of specific crystallography - Google Patents

Method to form surface equivalent to semiconductor substrate in terms of specific crystallography Download PDF

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JP2006086492A
JP2006086492A JP2005036761A JP2005036761A JP2006086492A JP 2006086492 A JP2006086492 A JP 2006086492A JP 2005036761 A JP2005036761 A JP 2005036761A JP 2005036761 A JP2005036761 A JP 2005036761A JP 2006086492 A JP2006086492 A JP 2006086492A
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▲温▼安農
Annong Wen
Junrui Li
李俊叡
Maoren Wu
伍茂仁
Gunbun Cho
張郡文
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Neostones MicroFabrication Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method to form a 45-degree surface of a semiconductor substrate having excellent surface smoothness to be used as a reflecting surface for optical source. <P>SOLUTION: The method to form a crystallographically equivalent surface to the ä110} surface or ä100} surface of a semiconductor substrate include the following steps. First, a semiconductor substrate having a top surface crystallographically equivalent to the ä110} surface or ä100} surface is prepared. Then, an etching mask with an etching window is formed on the surface crystallographically equivalent to the ä110} surface or ä100} surface. The etching window has a sidewall having a certain degree of a tilt angle with a direction crystallographically equivalent to the <100> direction or <110> direction of the semiconductor substrate. The tilt angle is greater than 0 degree and smaller than 90 degrees, and not equal to 45 degrees. After that, selective anisotropic etching treatment is performed using the etching window, thereby forming the equivalent surface to the ä110} surface or ä100} surface on the semiconductor substrate. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は特定方位の面を形成する方法に関するものであり、特に、半導体基板の{110}面又は{100}面と結晶学的に等価な面を形成する方法に関する。   The present invention relates to a method for forming a plane with a specific orientation, and more particularly to a method for forming a crystallographically equivalent plane with a {110} plane or a {100} plane of a semiconductor substrate.

図1(a)及び図1(b)を参照すると、光ピックアップに用いられる単一のレーザモジュールのパッケージ構造が概略的に示されている。このレーザモジュールは、レーザダイオード102と2つの受光器103とが基板100上に配置された構成となっている。レーザダイオード102から発されたレーザ光104は、レーザモジュールの上方に配置されたレンズ(図示せず)を介して読み取ろうとするディスクに送られる。その後、ディスクで反射された光は、受光器103によって受光され、続く手順でさらに処理される。レンズはレーザ光の進路に位置していないため、従来、レーザ光を上方に導くためのマイクロプリズムがレーザ光の進路に取り付けられる。あるいは、より有利な方法として、図1(a)及び図1(b)に示されるように、基板100の45度面101を利用して、マイクロプリズムを要さずに同様の目的を達成している。図示されるように、レーザダイオード102から発されたレーザ光104は、面101に入射し、面101で反射されてレンズを通過する。この方法によると、マイクロプリズムが不要となり、レーザモジュールの製造コストを削減できるとともに、製造工程を間単にすることができる。   Referring to FIGS. 1A and 1B, a package structure of a single laser module used for an optical pickup is schematically shown. This laser module has a configuration in which a laser diode 102 and two light receivers 103 are arranged on a substrate 100. Laser light 104 emitted from the laser diode 102 is sent to a disk to be read through a lens (not shown) disposed above the laser module. Thereafter, the light reflected by the disc is received by the light receiver 103 and further processed in a subsequent procedure. Since the lens is not positioned in the path of the laser beam, conventionally, a microprism for guiding the laser beam upward is attached to the path of the laser beam. Alternatively, as a more advantageous method, as shown in FIGS. 1 (a) and 1 (b), the 45-degree surface 101 of the substrate 100 is used to achieve the same object without the need for a microprism. ing. As shown in the figure, the laser beam 104 emitted from the laser diode 102 is incident on the surface 101, is reflected by the surface 101, and passes through the lens. According to this method, the microprism is not required, and the manufacturing cost of the laser module can be reduced and the manufacturing process can be simplified.

レーザ光をレンズの方に適切に反射するには、面101は正確に45度の反射面でなければならない。基板100に45度面101を形成するための工程を示した図2(a)から図2(c)を参照いただきたい。図2(a)は、上面が{100}面と結晶学的に等価な面である円柱状の結晶棒200の概略側面図である。円柱状の結晶棒200は、{100}面と結晶学的に等価な面である上面に対して平行な破線面に沿って切断され、{100}面と結晶学的に等価な面及び<100>方向と結晶学的に等価な方位を各々有する複数のシリコンウェーハ201が得られる。その後、図2(b)に示されるように、少なくとも一つのエッチング窓299を有するエッチングマスク290(一部を図示)がシリコンウェーハ201の{100}面と結晶学的に等価な面に形成される。エッチング窓299の側壁298は、シリコンウェーハ201の<100>方向と結晶学的に等価な方向に対して45度の傾斜角度をなす向きになっている。次に、エッチングマスク290を設けた状態でKOH−イソプロパノールエッチング液を用いて異方性エッチング処理を行うことにより、図2(c)の断面図に示されるように、45度面101すなわち{110}面と結晶学的に等価な面がシリコンウェーハ201のエッチング窓部分に形成される。   In order to properly reflect the laser light back toward the lens, the surface 101 must be an accurate 45 degree reflective surface. Please refer to FIG. 2A to FIG. 2C showing a process for forming the 45-degree surface 101 on the substrate 100. FIG. 2A is a schematic side view of a cylindrical crystal rod 200 whose upper surface is a crystallographically equivalent surface to the {100} plane. The cylindrical crystal rod 200 is cut along a broken line parallel to the upper surface, which is a crystallographically equivalent surface to the {100} surface, and a surface that is crystallographically equivalent to the {100} surface and < A plurality of silicon wafers 201 each having an orientation crystallographically equivalent to the 100> direction are obtained. Thereafter, as shown in FIG. 2B, an etching mask 290 (partially shown) having at least one etching window 299 is formed on a surface that is crystallographically equivalent to the {100} plane of the silicon wafer 201. The The side wall 298 of the etching window 299 is oriented at an inclination angle of 45 degrees with respect to a crystallographically equivalent direction to the <100> direction of the silicon wafer 201. Next, an anisotropic etching process is performed using a KOH-isopropanol etching solution in a state where the etching mask 290 is provided, so that a 45-degree plane 101, that is, {110, as shown in the sectional view of FIG. } A plane crystallographically equivalent to the plane is formed in the etching window portion of the silicon wafer 201.

しかしながら、実際には、結果として生じる面101の平均表面粗度は所望されるほど低くはなく、通常200nm程度となることが分かっている。面101が滑らかでないのは、{110}面と結晶学的に等価な面と共に{111}面と結晶学的に等価な微小な面が多く存在するためであり、これについては、Sensors Actuators A 第48巻 229−238頁(1995) Irena Barycka及びIrena Zubelの“Silicon anisotropic etching in KOH−isopropanol etchant”で論じられている。理由は、{111}面と結晶学的に等価な面は{110}面と結晶学的に等価な面よりも安定しており、よって、エッチング処理中に誘発されやすいためである。   In practice, however, it has been found that the average surface roughness of the resulting surface 101 is not as low as desired and is typically on the order of 200 nm. The reason why the surface 101 is not smooth is that there are many microscopic surfaces crystallographically equivalent to the {111} plane as well as surfaces that are crystallographically equivalent to the {110} plane, and this is related to Sensors Actuators A. Vol. 48, pages 229-238 (1995), discussed in “Silicon anisotropic etching in KOH-isopropanol etchant” by Irena Barrycka and Irena Zubel. The reason is that the plane that is crystallographically equivalent to the {111} plane is more stable than the plane that is crystallographically equivalent to the {110} plane, and is therefore more likely to be induced during the etching process.

光通信に用いられる光源の波長は通常、可視線から赤外線の範囲にあり、光記憶装置に用いられるレーザ波長も同様にかなり限定されているため、反射面の表面粗度は優れた結像特性を確保する上で重要である。例えば、平均表面粗度は入射光の波長の10分の1未満である必要があり、さもないと、入射光の著しい分散損失が生じる恐れがある。一方、記憶密度が高まるにつれて、光記憶装置の光源の動作波長が制限される。従って、200nmの平均表面粗度はそのような用途に適しておらず、よって、表面品質を向上させる必要がある。上述したように、{111}面と結晶学的に等価な面は{110}面と結晶学的に等価な面よりも安定している。つまり、エッチング窓299の側壁298とシリコンウェーハ201の<100>方向と結晶学的に等価な方向との傾斜角度を54.74度にして、図2(b)に示されるシリコンウェーハ201の異方性エッチング処理を行うと、図2(d)に示されるように、十分な滑らかさを有する54.74度の{111}面と結晶学的に等価な面199が形成される。従って、別の従来技術は、安定していて滑らかな{111}面と結晶学的に等価な面を利用して、望ましい45度の{111}面と結晶学的に等価な面を得ているが、以下、これについて説明を述べる。   The wavelength of the light source used in optical communication is usually in the range from visible to infrared, and the laser wavelength used in optical storage devices is also quite limited, so the surface roughness of the reflective surface is excellent imaging characteristics It is important to secure For example, the average surface roughness needs to be less than one-tenth of the wavelength of the incident light, otherwise significant dispersion loss of the incident light can occur. On the other hand, as the storage density increases, the operating wavelength of the light source of the optical storage device is limited. Therefore, an average surface roughness of 200 nm is not suitable for such applications, and therefore surface quality needs to be improved. As described above, a plane that is crystallographically equivalent to the {111} plane is more stable than a plane that is crystallographically equivalent to the {110} plane. That is, the inclination angle between the side wall 298 of the etching window 299 and the <100> direction of the silicon wafer 201 and the crystallographically equivalent direction is set to 54.74 degrees, and the difference of the silicon wafer 201 shown in FIG. When the isotropic etching process is performed, as shown in FIG. 2D, a surface 199 crystallographically equivalent to the 54.74 degree {111} plane having sufficient smoothness is formed. Therefore, another prior art utilizes a stable and smooth {111} plane and a crystallographic equivalent plane to obtain a desired 45 degree {111} plane and a crystallographic equivalent plane. This will be explained below.

図3(a)から図3(c)を参照いただきたい。{100}面と結晶学的に等価な上面を有する円柱状の結晶棒300は、上面に対して9.74度傾いた破線面に沿って切断され、シリコンウェーハ301が形成される。その後、図3(b)に示されるように、少なくとも一つのエッチング窓399を有するエッチングマスク390(一部を図示)がシリコンウェーハ301の表面に形成される。エッチング窓399の側壁398は、シリコンウェーハ301の<100>方向と結晶学的に等価な方向に対して略0度の向きになっている。次に、図3(c)に示されるように、KOH−イソプロパノールエッチング液を用いて異方性エッチング処理を行うことにより、45度の{110}面と結晶学的に等価な面401がシリコンウェーハ301に形成される。このようにして形成された45度面401の平均表面平滑度は十分に改善されている。しかしながら、この工程の適用には制限がある。このシリコンウェーハは結晶棒を傾斜した角度で特別に切断することにより得られるため、シリコンウェーハを特別に注文する必要がある。さらに、図3(c)に示されるように、45度面401に加えて、シリコンウェーハ301自体の特定の結晶学的に等価な方位により、面401の反対側に64.4度の面380が形成される。   Please refer to FIG. 3 (a) to FIG. 3 (c). A cylindrical crystal rod 300 having an upper surface crystallographically equivalent to the {100} plane is cut along a broken line surface inclined by 9.74 degrees with respect to the upper surface to form a silicon wafer 301. Thereafter, as shown in FIG. 3B, an etching mask 390 (partially shown) having at least one etching window 399 is formed on the surface of the silicon wafer 301. The sidewall 398 of the etching window 399 is oriented at approximately 0 degrees with respect to a crystallographically equivalent direction to the <100> direction of the silicon wafer 301. Next, as shown in FIG. 3C, by performing an anisotropic etching process using a KOH-isopropanol etching solution, a surface 401 crystallographically equivalent to the 45-degree {110} plane is silicon. Formed on wafer 301. The average surface smoothness of the 45-degree surface 401 formed in this way is sufficiently improved. However, application of this process is limited. Since this silicon wafer is obtained by specially cutting the crystal rod at an inclined angle, the silicon wafer needs to be specially ordered. Further, as shown in FIG. 3 (c), in addition to the 45 degree plane 401, a plane 380 of 64.4 degrees on the opposite side of the plane 401 due to the specific crystallographic equivalent orientation of the silicon wafer 301 itself. Is formed.

本発明は、光源の反射面として用いられる、優れた表面平滑度を有する半導体基板の45度面を形成するための方法を提供する。   The present invention provides a method for forming a 45 degree surface of a semiconductor substrate having excellent surface smoothness used as a reflective surface of a light source.

また、本発明は、各エッチング窓に、対向する45度面を同時に形成するための方法を提供する。   The present invention also provides a method for simultaneously forming opposing 45 degree faces in each etching window.

本発明の第1の側面によると、半導体基板の{110}面と結晶学的に等価な面を形成する方法が提供される。まず、{100}面と結晶学的に等価な面を有する半導体基板を用意する。次に、エッチング窓を有するエッチングマスクを、{100}面と結晶学的に等価な面に形成する。エッチング窓は、半導体基板の<100>方向と結晶学的に等価な方向に対してある傾斜角度をなす向きの側壁を有する。傾斜角度は、0度より大きくて90度より小さく、且つ45度に等しくない角度である。その後、エッチング窓を用いて選択的な異方性エッチング処理を行い、半導体基板に{110}面と結晶学的に等価な面を形成する。   According to a first aspect of the present invention, a method is provided for forming a crystallographically equivalent plane to the {110} plane of a semiconductor substrate. First, a semiconductor substrate having a plane that is crystallographically equivalent to the {100} plane is prepared. Next, an etching mask having an etching window is formed on a plane that is crystallographically equivalent to the {100} plane. The etching window has side walls oriented at an inclination angle with respect to a crystallographically equivalent direction to the <100> direction of the semiconductor substrate. The tilt angle is an angle greater than 0 degree, less than 90 degrees, and not equal to 45 degrees. Thereafter, selective anisotropic etching is performed using the etching window to form a crystallographically equivalent surface to the {110} plane on the semiconductor substrate.

半導体基板は、ダイアモンド構造の結晶構造を有することが好ましい。   The semiconductor substrate preferably has a diamond structure crystal structure.

半導体基板は、シリコン基板であることが好ましい。   The semiconductor substrate is preferably a silicon substrate.

一実施形態においては、選択的な異方性エッチング処理は、エッチング液で行われるウェットエッチング処理である。   In one embodiment, the selective anisotropic etching process is a wet etching process performed with an etchant.

一実施形態においては、エッチング液は水酸化カリウム、水及びイソプロパノールの混合液である。   In one embodiment, the etchant is a mixture of potassium hydroxide, water and isopropanol.

一実施形態においては、選択的な異方性エッチング処理は、エッチング液の温度を60度から95度にして、攪拌しながら行われる。   In one embodiment, the selective anisotropic etching process is performed while stirring at a temperature of 60 to 95 degrees.

傾斜角度は、22度以上45度未満であることが好ましい。   The tilt angle is preferably 22 degrees or more and less than 45 degrees.

傾斜角度は、45度より大きく68度以下であることが好ましい。   The inclination angle is preferably greater than 45 degrees and 68 degrees or less.

本発明の第2の側面によると、半導体基板の{100}面と結晶学的に等価な面を形成する方法が提供される。まず、{110}面と結晶学的に等価な面を有する半導体基板を用意する。次に、エッチング窓を有するエッチングマスクを、{110}面と結晶学的に等価な面に形成する。エッチング窓は、半導体基板の<110>方向と結晶学的に等価な方向に対してある傾斜角度をなす向きの側壁を有する。傾斜角度は、0度より大きくて90度より小さく、且つ45度に等しくない角度である。その後、エッチング窓を用いて選択的な異方性エッチング処理を行い、半導体基板に{100}面と結晶学的に等価な面を形成する。   According to a second aspect of the present invention, a method is provided for forming a crystallographically equivalent plane to the {100} plane of a semiconductor substrate. First, a semiconductor substrate having a plane that is crystallographically equivalent to the {110} plane is prepared. Next, an etching mask having an etching window is formed on a plane that is crystallographically equivalent to the {110} plane. The etching window has sidewalls oriented at an inclination angle with respect to a crystallographically equivalent direction to the <110> direction of the semiconductor substrate. The tilt angle is an angle greater than 0 degree, less than 90 degrees, and not equal to 45 degrees. Thereafter, selective anisotropic etching is performed using the etching window to form a crystallographically equivalent surface to the {100} plane on the semiconductor substrate.

本発明の第3の側面によると、半導体発光装置の反射面を形成する方法が提供される。まず、第1の特定の結晶面を有する半導体基板を用意する。次に、エッチング窓を有するエッチングマスクを、第1の特定の結晶面に形成する。エッチング窓は、第1の特定の結晶面に対応する結晶方位に対してある傾斜角度をなす向きの側壁を有する。傾斜角度は、0度より大きくて90度より小さく、且つ45度に等しくない角度である。その後、エッチング窓を用いて半導体基板に選択的な異方性エッチング処理を行い、第2の特定の結晶面として知られる反射面を形成する。第1及び第2の特定の結晶面は略45度の鋭角をなす。   According to a third aspect of the present invention, a method for forming a reflective surface of a semiconductor light emitting device is provided. First, a semiconductor substrate having a first specific crystal plane is prepared. Next, an etching mask having an etching window is formed on the first specific crystal plane. The etching window has side walls oriented at an inclination angle with respect to the crystal orientation corresponding to the first specific crystal plane. The tilt angle is an angle greater than 0 degree, less than 90 degrees, and not equal to 45 degrees. Thereafter, a selective anisotropic etching process is performed on the semiconductor substrate using the etching window to form a reflective surface known as a second specific crystal plane. The first and second specific crystal planes form an acute angle of about 45 degrees.

一実施形態においては、第1及び第2の特定の結晶面は、ダイアモンド構造の{100}面及び{110}面と結晶学的に等価な面である。   In one embodiment, the first and second specific crystal faces are crystallographically equivalent faces to the {100} face and {110} face of the diamond structure.

本発明の上述の内容は、以下の詳細な説明及び添付図面を検討頂ければ、当業者にはより容易に理解されるであろう。   The foregoing description of the present invention will become more readily apparent to those of ordinary skill in the art upon reviewing the following detailed description and the accompanying drawings.

半導体基板に一又は複数の安定した滑らかな45度面をエッチングにより形成するため、本発明によると、半導体基板上に形成されるエッチング窓の半導体基板の結晶方位に対する傾斜角度が選択される。以下、例を挙げて説明する。   In order to form one or a plurality of stable and smooth 45-degree surfaces on a semiconductor substrate by etching, according to the present invention, the inclination angle of the etching window formed on the semiconductor substrate with respect to the crystal orientation of the semiconductor substrate is selected. Hereinafter, an example will be described.

図4(a)を参照すると、ダイアモンド構造の結晶構造を有するシリコンから成る半導体基板500が示されている。半導体基板500は、{100}面と結晶学的に等価な上面及び<100>方向と結晶学的に等価な方位を有し、結晶棒(図示せず)を該結晶棒の{100}面と結晶学的に等価な上面に対して平行な面に沿って切断することにより得られる。半導体基板500の{100}面と結晶学的に等価な面に、一つのエッチング窓540を有するエッチングマスク530が形成される。エッチング窓540は、パターンを形成し、エッチングマスク530をドライエッチング処理によりエッチングすることによって得られる。エッチング窓540の側壁541は、半導体基板500の<100>方向と結晶学的に等価な方向に対して傾斜角度αの向きになっている。   Referring to FIG. 4A, a semiconductor substrate 500 made of silicon having a diamond structure crystal structure is shown. The semiconductor substrate 500 has an upper surface crystallographically equivalent to the {100} plane and an orientation crystallographically equivalent to the <100> direction, and a crystal rod (not shown) is the {100} plane of the crystal rod. Obtained by cutting along a plane parallel to the top surface which is crystallographically equivalent. An etching mask 530 having one etching window 540 is formed on a surface that is crystallographically equivalent to the {100} plane of the semiconductor substrate 500. The etching window 540 is obtained by forming a pattern and etching the etching mask 530 by a dry etching process. The side wall 541 of the etching window 540 is oriented at an inclination angle α with respect to a crystallographically equivalent direction to the <100> direction of the semiconductor substrate 500.

上述したように、{110}面と結晶学的に等価な面と共に{111}面と結晶学的に等価な微小な面が多数存在すると、反射面の表面平滑度の低下をまねくため、45度の傾斜角度は正確な45度面を形成するのに適さない。一方、本発明の発明者が研究したところによると、傾斜角度αを0度より大きくて45度より小さい、又は45度より大きくて90度より小さい角度にすると、滑らかな45度面が得られる。   As described above, if there are many microscopic surfaces crystallographically equivalent to the {111} plane as well as surfaces that are crystallographically equivalent to the {110} plane, the surface smoothness of the reflecting surface is lowered. A tilt angle of degrees is not suitable for forming an accurate 45 degree surface. On the other hand, according to a study by the inventors of the present invention, when the inclination angle α is greater than 0 degree and less than 45 degrees, or greater than 45 degrees and less than 90 degrees, a smooth 45 degree surface is obtained. .

図4(a)に示される実施形態においては、傾斜角度αは0度より大きく45度より小さくなるように選択され、例えば22度とする。22度の傾斜角度を有するエッチング窓540をエッチングマスク530に形成した後、60度から95度の温度のエッチング液で選択的な異方性エッチング処理を行う。その結果、図4(a)のそれぞれD−D’断面図及びE−E’断面図である図4(b)及び図4(c)に示されるように、四方の45度面550が半導体基板500のエッチング窓部分に形成される。選択的な異方性エッチング処理に用いられるエッチング液は、水酸化カリウム、水及びイソプロパノールの混合液等である。当該混合液における各成分の比率は、所望のエッチング速度によって決まる。選択的な異方性エッチング処理中においては、45度反射面に容易に付着して表面平滑度に悪影響を与える気泡を除去するため、エッチング液を継続的に攪拌する必要がある。   In the embodiment shown in FIG. 4A, the inclination angle α is selected to be larger than 0 degree and smaller than 45 degrees, for example, 22 degrees. After the etching window 540 having an inclination angle of 22 degrees is formed on the etching mask 530, a selective anisotropic etching process is performed with an etching solution having a temperature of 60 to 95 degrees. As a result, as shown in FIGS. 4 (b) and 4 (c), which are DD ′ and EE ′ sectional views of FIG. It is formed in the etching window portion of the substrate 500. An etching solution used for the selective anisotropic etching treatment is a mixed solution of potassium hydroxide, water, and isopropanol. The ratio of each component in the liquid mixture depends on the desired etching rate. During the selective anisotropic etching process, it is necessary to continuously stir the etching solution in order to remove bubbles that easily adhere to the 45 ° reflection surface and adversely affect the surface smoothness.

図5(a)を参照して、半導体基板の{110}面と結晶学的に等価な面を形成する別の実施形態を説明する。本実施形態において、半導体基板500を形成するステップ及び選択的な異方性エッチング処理を行うステップが含まれるが、これらのステップは図4(a)に示したものと同様であり、ここでは重ねて説明を行わない。本実施形態においては、エッチングマスク530のエッチング窓542は、シリコンウェーハの<100>方向と結晶学的に等価な方向と側壁543との傾斜角度αが45度より大きく90度より小さい角度、例えば68度、になるように形成される。選択的な異方性エッチング処理が行われると、図5(a)のそれぞれF−F’断面図及びG−G’断面図である図5(b)及び図5(c)に示されるように、四方の45度面552が半導体基板500のエッチング窓部分に形成される。   With reference to FIG. 5A, another embodiment for forming a crystallographically equivalent plane to the {110} plane of the semiconductor substrate will be described. In the present embodiment, a step of forming the semiconductor substrate 500 and a step of performing a selective anisotropic etching process are included. These steps are the same as those shown in FIG. Will not be described. In this embodiment, the etching window 542 of the etching mask 530 has an inclination angle α between the <100> direction of the silicon wafer and a crystallographically equivalent direction and the side wall 543 greater than 45 degrees and smaller than 90 degrees, for example, It is formed to be 68 degrees. When the selective anisotropic etching process is performed, as shown in FIG. 5B and FIG. 5C, which are the FF ′ sectional view and the GG ′ sectional view of FIG. 5A, respectively. In addition, four-sided 45 degree surfaces 552 are formed in the etching window portion of the semiconductor substrate 500.

図6(a)を参照すると、複数のエッチング窓548及び549が半導体基板500上のエッチングマスク530に形成されている。選択的な異方性エッチング処理が行われると、図6(a)のH−H’断面図である図6(b)に示されるように、2組の四方45度面554及び555が半導体基板500のエッチング窓部分に形成される。このような方法によると、レーザモジュールの反射面加工における複雑さが大いに緩和されるとともにコストが大幅に削減される。   Referring to FIG. 6A, a plurality of etching windows 548 and 549 are formed in the etching mask 530 on the semiconductor substrate 500. When the selective anisotropic etching process is performed, as shown in FIG. 6B, which is a cross-sectional view taken along the line HH ′ of FIG. It is formed in the etching window portion of the substrate 500. According to such a method, the complexity of processing the reflecting surface of the laser module is greatly reduced and the cost is greatly reduced.

上記の各実施形態において、本発明に用いられるエッチングマスク530は二酸化珪素(SiO)又は窒化珪素(Si)から成り、これらは、選択的な異方性エッチング処理を行った後に、フッ化水素酸を用いて除去することができる。本発明によると、{100}面と結晶学的に等価な面と{110}面と結晶学的に等価な面とがなす鋭角が、軽微なずれはあるが、略45度になるように、傾斜角度αが調整される。本発明の発明者の研究によると、傾斜角度αが45度から外れるほど、結果として生じる45度面の平均表面平滑度は高くなる。一方、傾斜角度αが45度に近くなるほど、正確な45度面からの角度のずれが小さくなる。この選択は製造者に委ねられ、実際の必要条件によって決められる。例えば、許容し得るずれを±1度として、45度の{110}面と結晶学的に等価な面を得ることが求められるとき、傾斜角度αは22−45度又は45−68度の範囲に調整される必要がある。 In each of the above-described embodiments, the etching mask 530 used in the present invention is made of silicon dioxide (SiO 2 ) or silicon nitride (Si 3 N 4 ), and after these are subjected to selective anisotropic etching treatment, It can be removed using hydrofluoric acid. According to the present invention, the acute angle formed by the {100} plane and the crystallographically equivalent plane and the {110} plane and the crystallographically equivalent plane is approximately 45 degrees with slight deviation. The inclination angle α is adjusted. According to the study of the inventors of the present invention, the average surface smoothness of the resulting 45 degree plane increases as the tilt angle α deviates from 45 degrees. On the other hand, the closer the inclination angle α is to 45 degrees, the smaller the angle deviation from the accurate 45-degree surface. This choice is left to the manufacturer and is determined by actual requirements. For example, when it is required to obtain a plane that is crystallographically equivalent to the {110} plane of 45 degrees, where the allowable deviation is ± 1 degree, the inclination angle α is in the range of 22-45 degrees or 45-68 degrees. Need to be adjusted.

ここまでは半導体基板の{110}面と結晶学的に等価な面を形成するための方法に言及することによって本発明を説明してきたが、本発明はその他の結晶学的に等価な面を形成するための別の方法にも適用することができる。例えば、本発明によると、{110}面と結晶学的に等価な上面及び<110>方向と結晶学的に等価な方位を有する半導体基板を用いて、45度の{100}面と結晶学的に等価な面を形成することができる。図7(a)及び図7(b)に示されるように、0度より大きくて90度より小さい、且つ45度に等しくない傾斜各度範囲αがここでも同様に目的達成のために適用される。さらに、本発明は、マイクロメカトロニクスシステム(MEMS)及び光通信においても同様に利用することができる。   So far, the present invention has been described by referring to a method for forming a crystallographically equivalent plane to the {110} plane of a semiconductor substrate, but the present invention is not limited to other crystallographically equivalent planes. It can also be applied to other methods for forming. For example, according to the present invention, using a semiconductor substrate having a top surface that is crystallographically equivalent to the {110} plane and a crystallographically equivalent orientation to the <110> direction, Equivalent planes can be formed. As shown in FIG. 7 (a) and FIG. 7 (b), a tilt degree range α that is greater than 0 degree, less than 90 degrees, and not equal to 45 degrees is again applied to achieve the objective. The Furthermore, the present invention can be similarly used in a micro mechatronics system (MEMS) and optical communication.

以上、現在において最も実用的で好ましいと考えられる実施形態について本発明を説明してきたが、本発明は、開示された実施形態に限定されるものではなく、付記される請求項の最広義な解釈による趣旨及び範囲内における種々の変更及び同様の配置をも含むものであり、そのような変更及び同様の構造全てを包含する。   Although the present invention has been described above with respect to the most practical and preferred embodiments at present, the present invention is not limited to the disclosed embodiments, but is the broadest interpretation of the appended claims. It is intended to include various modifications and similar arrangements within the spirit and scope of the invention, and include all such modifications and similar structures.

(a)は光ピックアップヘッドに用いられるレーザモジュールのパッケージ構造の概略斜視図、(b)は(a)のA−A’断面図。(A) is a schematic perspective view of the package structure of the laser module used for an optical pick-up head, (b) is A-A 'sectional drawing of (a). (a)から(c)は、先行技術によるシリコンウェーハにおける45度の{110}面と結晶学的に等価な面を形成する工程を示した概略図、(d)は、先行技術によるシリコンウェーハにおける、45度の{111}面と結晶学的に等価な面の形成に応用される十分に滑らかな54.74度の{111}面と結晶学的に等価な面を示した概略図。(A) to (c) are schematic views showing a process of forming a crystallographically equivalent surface to a 45-degree {110} plane in a silicon wafer according to the prior art, and (d) is a silicon wafer according to the prior art. Schematic showing a sufficiently smooth 54.74 degree {111} plane and a crystallographic equivalent plane applied to the formation of a 45 degree {111} plane and a crystallographic equivalent plane. (a)から(c)は、先行技術によるシリコンウェーハにおける45度の{111}面と結晶学的に等価な面を形成する別の工程を示した概略図。(A)-(c) is the schematic which showed another process of forming a crystallographically equivalent surface with the 45-degree {111} plane in the silicon wafer by a prior art. (a)は本発明の一実施形態による、エッチング処理を行うためにエッチング窓が形成されたシリコンウェーハの一部分を概略的に示す上方から見た斜視図、(b)は(a)のD−D’断面図であり、エッチング処理後に生じた45度の{110}面と結晶学的に等価な面を概略的に示す図、(c)は(a)のE−E’断面図であり、エッチング処理後に生じた45度の{110}面と結晶学的に等価な面を概略的に示す図。(A) is the perspective view seen from the upper side which shows roughly a part of silicon wafer in which the etching window was formed in order to perform an etching process by one Embodiment of this invention, (b) is D- of (a). It is D 'sectional drawing, and is a figure which shows roughly the surface which is crystallographically equivalent to 45 degree {110} plane which arises after the etching process, (c) is EE' sectional drawing of (a). The figure which shows roughly the crystallographically equivalent surface with the {110} surface of 45 degree | times produced after the etching process. (a)は本発明の別の実施形態による、エッチング処理を行うためにエッチング窓が形成されたシリコンウェーハの一部分を概略的に示す上方から見た斜視図、(b)は(a)のF−F’断面図であり、エッチング処理後に生じた45度の{110}面と結晶学的に等価な面を概略的に示す図、(c)は(a)のG−G’断面図であり、エッチング処理後に生じた45度の{110}面と結晶学的に等価な面を概略的に示す図。(A) is the perspective view seen from the upper side which shows schematically a part of silicon wafer in which the etching window was formed in order to perform an etching process by another embodiment of this invention, (b) is F of (a). -F 'cross-sectional view schematically showing a plane that is crystallographically equivalent to the 45-degree {110} plane generated after the etching process, and (c) is a GG' cross-sectional view of (a). FIG. 4 is a diagram schematically showing a plane that is crystallographically equivalent to a 45-degree {110} plane that occurs after etching. (a)は本発明のさらに別の実施形態による、エッチング処理を行うために2つのエッチング窓が形成されたシリコンウェーハの一部分を概略的に示す上方から見た斜視図、(b)は(a)のH−H’断面図であり、エッチング処理後に生じた45度の{110}面と結晶学的に等価な面を概略的に示す図。(A) is the perspective view seen from the top which shows roughly a part of silicon wafer in which two etching windows were formed in order to perform etching processing by another embodiment of the present invention, and (b) (a) ) Is a cross-sectional view taken along the line HH 'of FIG. 4 and schematically shows a crystallographically equivalent plane to the 45-degree {110} plane generated after the etching process. (a)は本発明の一実施形態による、45度の{100}面と結晶学的に等価な面を得るためにエッチング窓が形成されたシリコンウェーハの一部分を概略的に示す上方から見た斜視図、(b)は本発明の別の実施形態による、45度の{100}面と結晶学的に等価な面を得るためにエッチング窓が形成されたシリコンウェーハを概略的に示す上方から見た斜視図。(A) is a top view schematically illustrating a portion of a silicon wafer having an etching window formed to obtain a crystallographically equivalent surface to a 45 degree {100} plane according to one embodiment of the present invention. A perspective view, (b) from above schematically shows a silicon wafer having an etching window formed to obtain a crystallographically equivalent surface to a 45 degree {100} plane according to another embodiment of the present invention. FIG.

符号の説明Explanation of symbols

500 半導体基板
530 エッチングマスク
540 エッチング窓
541 側壁
550 45度面


500 Semiconductor substrate
530 Etching mask 540 Etching window 541 Side wall 550 45 degree surface


Claims (10)

半導体基板の{110}面と結晶学的に等価な面を形成する方法であって、
{100}面と結晶学的に等価な面を有する半導体基板を用意するステップと、
前記半導体基板の<100>方向と結晶学的に等価な方向に対して0度より大きくて90度より小さく且つ45度に等しくない傾斜角度をなすように向けられた側壁を有するエッチング窓を持つエッチングマスクを、前記{100}面と結晶学的に等価な面に形成するステップと、
前記エッチング窓を用いて選択的な異方性エッチング処理を行い、前記半導体基板に{110}面と結晶学的に等価な面を形成するステップとを備えたことを特徴とする方法。
A method of forming a crystallographically equivalent plane with a {110} plane of a semiconductor substrate,
Providing a semiconductor substrate having a crystallographically equivalent plane to the {100} plane;
An etching window having sidewalls oriented at an inclination angle greater than 0 degrees, less than 90 degrees and not equal to 45 degrees relative to a crystallographically equivalent direction of the <100> direction of the semiconductor substrate; Forming an etching mask on a plane crystallographically equivalent to the {100} plane;
Performing a selective anisotropic etching process using the etching window to form a crystallographically equivalent plane to the {110} plane on the semiconductor substrate.
前記半導体基板は、結晶構造がダイアモンド構造のシリコン基板であることを特徴とする請求項1に記載の方法。   The method according to claim 1, wherein the semiconductor substrate is a silicon substrate having a diamond structure. 前記選択的な異方性エッチング処理は、60度から95度の温度のエッチング液で攪拌しながら行われるウェットエッチング処理であることを特徴とする請求項1に記載の方法。   The method according to claim 1, wherein the selective anisotropic etching process is a wet etching process performed while stirring with an etching solution having a temperature of 60 to 95 degrees. 前記傾斜角度は、22度以上45度未満であることを特徴とする請求項1に記載の方法。   The method according to claim 1, wherein the tilt angle is not less than 22 degrees and less than 45 degrees. 前記傾斜角度は、45度より大きく68度以下であることを特徴とする請求項1に記載の方法。   The method of claim 1, wherein the tilt angle is greater than 45 degrees and less than or equal to 68 degrees. 半導体基板の{100}面と結晶学的に等価な面を形成する方法であって、
{110}面と結晶学的に等価な面を有する半導体基板を用意するステップと、
前記半導体基板の<110>方向と結晶学的に等価な方向に対して0度より大きくて90度より小さく且つ45度に等しくない傾斜角度をなすように向けられた側壁を有するエッチング窓を持つエッチングマスクを、前記{110}面と結晶学的に等価な面に形成するステップと、
前記エッチング窓を用いて選択的な異方性エッチング処理を行い、前記半導体基板に{100}面と結晶学的に等価な面を形成するステップとを備えたことを特徴とする方法。
A method of forming a crystallographically equivalent plane with a {100} plane of a semiconductor substrate,
Providing a semiconductor substrate having a crystallographically equivalent plane to the {110} plane;
An etching window having sidewalls oriented to form an inclination angle greater than 0 degrees, less than 90 degrees and not equal to 45 degrees relative to a crystallographically equivalent direction of the <110> direction of the semiconductor substrate; Forming an etching mask on a plane crystallographically equivalent to the {110} plane;
Performing a selective anisotropic etching process using the etching window to form a crystallographically equivalent plane to the {100} plane on the semiconductor substrate.
前記傾斜角度は22度以上45度未満である、又は前記傾斜角度は45度より大きく68度以下であることを特徴とする請求項6に記載の方法。   The method according to claim 6, wherein the inclination angle is 22 degrees or more and less than 45 degrees, or the inclination angle is greater than 45 degrees and 68 degrees or less. 半導体発光装置の反射面を形成する方法であって、
第1の特定の結晶面を有する半導体基板を用意するステップと、
前記第1の特定の結晶面に対応する結晶方位に対して0度より大きくて90度より小さく且つ45度に等しくない傾斜角度をなすように向けられた側壁を有するエッチング窓を持つエッチングマスクを、前記第1の特定の結晶面に形成するステップと、
前記エッチング窓を用いて前記半導体基板に選択的な異方性エッチング処理を行い、第2の特定の結晶面である前記反射面を形成するステップとを備え、
前記第1及び第2の特定の結晶面は略45度の鋭角をなすことを特徴とする方法。
A method of forming a reflective surface of a semiconductor light emitting device,
Providing a semiconductor substrate having a first specific crystal plane;
An etching mask having an etching window having sidewalls oriented to form an inclination angle greater than 0 degrees, less than 90 degrees, and not equal to 45 degrees with respect to a crystal orientation corresponding to the first specific crystal plane; Forming on the first specific crystal plane;
Performing a selective anisotropic etching process on the semiconductor substrate using the etching window to form the reflective surface which is a second specific crystal plane, and
The first and second specific crystal planes have an acute angle of about 45 degrees.
前記第1及び第2の特定の結晶面は、ダイアモンド構造の{100}面及び{110}面と結晶学的に等価な面であることを特徴とする請求項8に記載の方法。   9. The method according to claim 8, wherein the first and second specific crystal faces are crystallographically equivalent faces to the {100} face and {110} face of the diamond structure. 前記傾斜角度は22度以上45度未満である、又は前記傾斜角度は45度より大きく68度以下であることを特徴とする請求項8に記載の方法。   The method according to claim 8, wherein the inclination angle is 22 degrees or more and less than 45 degrees, or the inclination angle is greater than 45 degrees and 68 degrees or less.
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JP2011049562A (en) * 2009-08-27 2011-03-10 National Central Univ Package base, and method of molding the same
US10122147B2 (en) 2015-07-29 2018-11-06 Nichia Corporation Method for manufacturing optical member and method for manufacturing semiconductor laser device
US10581219B2 (en) 2015-07-29 2020-03-03 Nichia Corporation Semiconductor laser device
US10320144B2 (en) 2015-08-25 2019-06-11 Nichi Corporation Method for manufacturing an optical member and method for manufacturing a semiconductor laser device
US10594107B2 (en) 2015-08-25 2020-03-17 Nichia Corporation Semiconductor laser device
CN106990461A (en) * 2016-01-20 2017-07-28 上海新微技术研发中心有限公司 Silicon echelle grating with right angle and vertex angle and manufacturing method thereof
CN106990461B (en) * 2016-01-20 2020-05-15 安徽中科米微电子技术有限公司 Silicon echelle grating with right angle and vertex angle and manufacturing method thereof
JP2018011080A (en) * 2017-09-26 2018-01-18 日亜化学工業株式会社 Method for manufacturing optical member, method for manufacturing semiconductor laser device, and semiconductor laser device

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