JP2006086407A - Solid imaging device - Google Patents

Solid imaging device Download PDF

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JP2006086407A
JP2006086407A JP2004271113A JP2004271113A JP2006086407A JP 2006086407 A JP2006086407 A JP 2006086407A JP 2004271113 A JP2004271113 A JP 2004271113A JP 2004271113 A JP2004271113 A JP 2004271113A JP 2006086407 A JP2006086407 A JP 2006086407A
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shield electrode
well region
contact
type well
imaging device
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JP4599960B2 (en
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Atsushi Masagaki
敦 正垣
Ikuo Yoshihara
郁夫 吉原
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Sony Corp
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Sony Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To attain the miniaturization of a pixel and to improve an image pick-up property by reducing an arranging area of a contact when forming a contact for a shield electrode and a contact for a p-type well region in the same pixel. <P>SOLUTION: The contact for the shield electrode and the contact for the p-type well region in the same pixel are formed of a common contact. More concretely, an insulating layer of an element isolating portion and an embedded shield electrode are prepared in an upper portion of the p-type well region in which a photo diode of a silicon substrate is prepared, a part of the shield electrode is made to touch with a high density diffusing region prepared on the upper face of the p-type well region through an opening formed at the bottom face of the insulating layer, the shield electrode and the p-type well region are conductively formed, and a plug of the common contact portion is prepared in an upper portion of the element isolating portion. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、光電変換部を含む画素内の素子分離に絶縁層中にシールド電極を埋設して形成される素子分離部を用いた固体撮像素子に関し、特に画素内の電位安定化を図るためのコンタクト構造の改良に関するものである。   The present invention relates to a solid-state imaging device using an element isolation portion formed by embedding a shield electrode in an insulating layer for element isolation in a pixel including a photoelectric conversion portion, and particularly for stabilizing the potential in the pixel. The present invention relates to improvement of the contact structure.

従来のＣＭＯＳイメージセンサにおいて、フォトダイオード（光電変換部）ＰＤを含む画素内の素子分離部としては特許文献１に開示される酸化膜分離層が用いられていた。また、半導体基板上に設けた絶縁層中にシールド電極を埋設した素子分離部を用いる方法が知られている。
図３はこのような素子分離部の構造を示す図であり、図３（Ａ）はフォトダイオード周辺の平面図、図３（Ｂ）は図３（Ａ）のＢ−Ｂ´線断面図である。
一般に、イメージセンサのフォトダイオード２０は、シリコン基板１０に形成したＰ型ウェル領域１１中にＮ型不純物注入による電子蓄積領域を設け、その上面に高濃度のＰ型不純物注入による正孔蓄積領域を設けた構成が採用されている。
また、フォトダイオード２０によって蓄積された電子は、読み出しトランジスタのドレイン部２１に転送される構成となっており、フォトダイオード２０とドレイン部（ＦＤ）２１との間には、ゲート絶縁膜２２を介して転送電極２３が配置されている。
そして、図示の例では、フォトダイオード２０とドレイン部２１を包囲する状態で素子分離部３０が形成されている。この素子分離部３０は、絶縁層３１の内部に導電層よりなるシールド電極３２を埋設したものであり、フォトダイオード２０とドレイン部２１を隣接する素子から分離している。なお、転送電極２３の一部が絶縁層３１の上に乗り上げる状態で配置されている。
（例えば特許文献１参照）。
特開２００４−１９３５００号公報 In a conventional CMOS image sensor, an oxide film isolation layer disclosed in Patent Document 1 is used as an element isolation part in a pixel including a photodiode (photoelectric conversion part) PD. In addition, a method using an element isolation part in which a shield electrode is embedded in an insulating layer provided on a semiconductor substrate is known.
3A and 3B are diagrams showing the structure of such an element isolation portion. FIG. 3A is a plan view around the photodiode, and FIG. 3B is a cross-sectional view taken along the line BB ′ of FIG. is there.
In general, the photodiode 20 of the image sensor is provided with an electron accumulation region by N-type impurity implantation in a P-type well region 11 formed in the silicon substrate 10 and a hole accumulation region by high-concentration P-type impurity implantation on its upper surface. The provided configuration is adopted.
Further, electrons accumulated by the photodiode 20 are transferred to the drain portion 21 of the reading transistor, and a gate insulating film 22 is interposed between the photodiode 20 and the drain portion (FD) 21. The transfer electrode 23 is arranged.
In the illustrated example, the element isolation portion 30 is formed so as to surround the photodiode 20 and the drain portion 21. The element isolation part 30 is a part in which a shield electrode 32 made of a conductive layer is embedded in an insulating layer 31, and separates the photodiode 20 and the drain part 21 from adjacent elements. Note that a part of the transfer electrode 23 is disposed on the insulating layer 31.
(For example, refer to Patent Document 1).
JP 2004-193500 A

ところで、上述のような素子分離部では、確実な素子分離状態を得るために、シールド電極３２の電位を安定させる必要があり、そのためのコンタクト部を設けることが必要となっている。
図４はこのシールド電極用のコンタクト部の例を示す図であり、図４（Ａ）はフォトダイオード周辺の平面図、図４（Ｂ）は図４（Ａ）のＣ−Ｃ´線断面図である。
図示のように、コンタクト部のプラグ４１は絶縁層３１の上面からシールド電極３２に接触する状態で配置され、シールド電極３２の電位を安定化している。
また、フォトダイオード２０の安定した特性を得るためには、Ｐ型ウェル領域１１の電位を安定化する必要があり、そのためのコンタクト部を設けることが必要となっている。
さらに、上述した正孔蓄積領域用のＰ型層２０Ｂによる正孔のアキュミレーションを安定して行うためにはＰ型層２０Ｂの電位を供給する必要もある。
図５はこのＰ型ウェル領域用のコンタクト部の例を示す図であり、図５（Ａ）はフォトダイオード周辺の平面図、図５（Ｂ）は断面図である。
図示のように、フォトダイオード２０は、上述した電子蓄積領域用のＮ型層２０Ａと正孔蓄積領域用のＰ型層２０Ｂとを有しており、コンタクト部のプラグ５１はフォトダイオード２０のＰ型層２０Ｂに接触し、このＰ型層２０Ｂを介してＰ型ウェル領域１１に接続され、Ｐ型層２０ＢとＰ型ウェル領域１１の電位を安定化している。 By the way, in the element isolation part as described above, it is necessary to stabilize the potential of the shield electrode 32 in order to obtain a reliable element isolation state, and it is necessary to provide a contact part therefor.
FIG. 4 is a view showing an example of the contact portion for the shield electrode. FIG. 4A is a plan view around the photodiode, and FIG. 4B is a cross-sectional view taken along the line CC 'in FIG. It is.
As shown in the figure, the plug 41 in the contact portion is disposed in contact with the shield electrode 32 from the upper surface of the insulating layer 31, and stabilizes the potential of the shield electrode 32.
In addition, in order to obtain stable characteristics of the photodiode 20, it is necessary to stabilize the potential of the P-type well region 11, and it is necessary to provide a contact portion therefor.
Furthermore, in order to stably perform hole accumulation by the P-type layer 20B for the hole accumulation region described above, it is necessary to supply the potential of the P-type layer 20B.
FIG. 5 is a diagram showing an example of the contact portion for the P-type well region. FIG. 5A is a plan view around the photodiode, and FIG. 5B is a cross-sectional view.
As shown in the figure, the photodiode 20 has the above-described N-type layer 20A for the electron storage region and P-type layer 20B for the hole storage region, and the plug 51 in the contact portion is the P-type of the photodiode 20. It contacts the mold layer 20B and is connected to the P-type well region 11 through the P-type layer 20B, and stabilizes the potentials of the P-type layer 20B and the P-type well region 11.

そして、以上のようなシールド電極用のコンタクト部とＰ型ウェル領域用のコンタクト部は、画素の外部に設けることも可能であるが、所望の特性を得るために、同一の画素内に設けることも必要となる場合がある。
図６は同一画素内にシールド電極用のコンタクト部とＰ型ウェル領域用のコンタクト部を設けた場合の例を示す図であり、図６（Ａ）はフォトダイオード周辺の平面図、図６（Ｂ）は断面図である。
図示のように、シールド電極用のコンタクト部のプラグ４２は絶縁層３１の上面からシールド電極３２に接触する状態で配置され、シールド電極３２の電位を安定化している。
また、Ｐ型ウェル領域用のコンタクト部のプラグ５２はフォトダイオード２０のＰ型層２０Ｂに接触し、このＰ型層２０Ｂを介してＰ型ウェル領域１１に接続され、Ｐ型ウェル領域１１の電位を安定化している。 The shield electrode contact portion and the P-type well region contact portion as described above can be provided outside the pixel. However, in order to obtain desired characteristics, they are provided in the same pixel. May also be required.
FIG. 6 is a diagram showing an example in which a shield electrode contact portion and a P-type well region contact portion are provided in the same pixel. FIG. 6A is a plan view of the periphery of the photodiode, and FIG. B) is a cross-sectional view.
As shown in the figure, the plug 42 of the contact portion for the shield electrode is disposed in contact with the shield electrode 32 from the upper surface of the insulating layer 31, and stabilizes the potential of the shield electrode 32.
Further, the plug 52 in the contact portion for the P-type well region is in contact with the P-type layer 20B of the photodiode 20, and is connected to the P-type well region 11 through the P-type layer 20B. Is stabilizing.

しかしながら、このように同一画素内にシールド電極用のコンタクト部とＰ型ウェル領域用のコンタクト部を設けた場合、画素内に２つのコンタクト部が必要となり、画素の微細化においてコンタクト部の配置面積がフォトダイオードの開口率を下げる原因となり、感度の低下等、微細化に伴う撮像特性の悪化を助長するという問題がある。
また、シールド電極は、６０ｎｍ前後の薄膜ポリシリコン等によって形成するため、コンタクト形成時にシールド電極を突き抜けてしまう危険性があり、安定したコンタクト抵抗を得ることが難しいという課題もある。
さらに、Ｐ型ウェル領域に安定したコンタクトを形成するためにはＰ型ウェル領域用のコンタクト部のプラグ５２の直下の基板表面領域にＰ＋拡散層５３を形成する必要がある。この際、フォトダイオードのＮ層２０とＰ＋拡散層５３との電界は十分に小さくしないと、画素のノイズの原因になるという課題もある。 However, when the contact portion for the shield electrode and the contact portion for the P-type well region are provided in the same pixel as described above, two contact portions are required in the pixel, and the arrangement area of the contact portion is required for pixel miniaturization. However, this causes a reduction in the aperture ratio of the photodiode, and promotes deterioration of imaging characteristics accompanying miniaturization, such as a reduction in sensitivity.
In addition, since the shield electrode is formed of thin film polysilicon or the like having a thickness of about 60 nm, there is a risk that the shield electrode may be penetrated during contact formation, and it is difficult to obtain a stable contact resistance.
Further, in order to form a stable contact in the P-type well region, it is necessary to form a P + diffusion layer 53 in the substrate surface region immediately below the plug 52 in the contact portion for the P-type well region. At this time, there is also a problem that if the electric field between the N layer 20 and the P + diffusion layer 53 of the photodiode is not sufficiently reduced, it causes pixel noise.

そこで本発明は、同一画素内のシールド電極用のコンタクト部とＰ型ウェル領域用のコンタクト部を形成する場合にコンタクト部の配置面積を縮小できるとともに、適正なコンタクト部の形成を容易化でき、画素の微細化や撮像特性の改善に寄与できる固体撮像素子を提供することを目的とする。   Therefore, the present invention can reduce the arrangement area of the contact portion when forming the contact portion for the shield electrode and the contact portion for the P-type well region in the same pixel, and can facilitate the formation of an appropriate contact portion, An object of the present invention is to provide a solid-state imaging device that can contribute to pixel miniaturization and improvement of imaging characteristics.

上述の目的を達成するため、本発明の固体撮像素子は、半導体基板に設けられたウェル領域中に形成される光電変換部と、前記半導体基板上に設けられた絶縁層中にシールド電極を埋設して形成される素子分離部と、前記ウェル領域と前記シールド電極の電位安定化を行う共用コンタクト部とを有することを特徴とする。   In order to achieve the above object, a solid-state imaging device according to the present invention includes a photoelectric conversion unit formed in a well region provided on a semiconductor substrate and a shield electrode embedded in an insulating layer provided on the semiconductor substrate. And a common contact portion for stabilizing the potential of the well region and the shield electrode.

本発明の固体撮像素子によれば、光電変換部を設けたウェル領域の電位安定化と素子分離部の絶縁層に埋設されたシールド電極の電位安定化を行う共用コンタクト部を設けたことから、例えば同一画素内のウェル領域とシールド電極の電位安定化のためのコンタクトを１本の共用コンタクト部で実現でき、コンタクト部の形成箇所の削減によって配置面積を縮小でき、画素の微細化や撮像特性の改善に寄与できる。また、コンタクト部の形成箇所を削減することで、適正なコンタクト部の形成を容易化でき、この点からも特性の安定化に寄与できる。   According to the solid-state imaging device of the present invention, since the common contact portion for stabilizing the potential of the well region provided with the photoelectric conversion portion and stabilizing the potential of the shield electrode embedded in the insulating layer of the element isolation portion is provided, For example, the contact for stabilizing the potential of the well region and the shield electrode in the same pixel can be realized by one common contact part, and the arrangement area can be reduced by reducing the formation part of the contact part. Can contribute to the improvement. Further, by reducing the number of locations where the contact portion is formed, it is possible to facilitate the formation of an appropriate contact portion, which also contributes to the stabilization of characteristics.

本発明の実施の形態では、同一画素内のシールド電極用のコンタクト部とＰ型ウェル領域用のコンタクト部を共用コンタクト部によって形成する。具体的には、シリコン基板のフォトダイオードを設けたＰ型ウェル領域の上部に素子分離部の絶縁層及び埋め込みシールド電極を設け、絶縁層の底面に形成した開口部を通してシールド電極の一部がＰ型ウェル領域の上面に設けた高濃度拡散領域に接触するようにし、シールド電極とＰ型ウェル領域とが導通した状態に形成し、この素子分離部の上部に共用コンタクト部のプラグを設ける。この場合、プラグをシールド電極だけに接触した状態で形成し、シールド電極を介してＰ型ウェル領域に接続した構造としてもよいし、プラグをシールド電極に貫通させてＰ型ウェル領域まで直接接触した構造としてもよい。   In the embodiment of the present invention, the contact portion for the shield electrode and the contact portion for the P-type well region in the same pixel are formed by the common contact portion. Specifically, the insulating layer and buried shield electrode of the element isolation portion are provided on the P-type well region provided with the photodiode of the silicon substrate, and a part of the shield electrode is formed through the opening formed on the bottom surface of the insulating layer. The shield electrode and the P-type well region are formed in a conductive state so as to be in contact with the high-concentration diffusion region provided on the upper surface of the type well region, and a common contact portion plug is provided above the element isolation portion. In this case, the plug may be formed in contact with only the shield electrode and connected to the P-type well region via the shield electrode, or the plug may be directly contacted to the P-type well region through the shield electrode. It is good also as a structure.

図１は本発明の実施例による固体撮像素子の要部の構造を示す図であり、図１（Ａ）はフォトダイオード周辺の平面図、図１（Ｂ）は図１（Ａ）のＡ−Ａ´線断面図である。
図示のように、フォトダイオード１２０と読み出しトランジスタのドレイン部（ＦＤ）１２１が、シリコン基板１１０に形成したＰ型ウェル領域１１１に形成されており、フォトダイオード１２０とドレイン部１２１との間に、ゲート絶縁膜１２２を介して転送電極１２３が配置されている。
また、フォトダイオード１２０とドレイン部１２１を包囲する状態で素子分離部１３０が形成されている。この素子分離部１３０は、絶縁層１３１の内部に導電層よりなるシールド電極１３２を埋設したものであり、フォトダイオード１２０とドレイン部１２１を隣接する素子から分離している。 FIG. 1 is a diagram showing the structure of the main part of a solid-state imaging device according to an embodiment of the present invention. FIG. 1 (A) is a plan view around a photodiode, and FIG. 1 (B) is an A- It is A 'line sectional drawing.
As shown in the figure, a photodiode 120 and a drain portion (FD) 121 of the readout transistor are formed in a P-type well region 111 formed in the silicon substrate 110, and a gate is provided between the photodiode 120 and the drain portion 121. A transfer electrode 123 is disposed with an insulating film 122 interposed therebetween.
Further, the element isolation part 130 is formed so as to surround the photodiode 120 and the drain part 121. The element isolation part 130 is an insulating layer 131 having a shield electrode 132 made of a conductive layer embedded therein, and separates the photodiode 120 and the drain part 121 from adjacent elements.

そして、このような画素内の素子構造において、シリコン基板１１０のＰ型ウェル領域１１１の電位安定化と素子分離部１３０のシールド電極１３２の電位安定化を行う共用コンタクト部１４０が設けられている。
以下、本実施例の共用コンタクト構造について説明する。
まず、図１（Ｂ）に示すように、シリコン基板１１０のＰ型ウェル領域１１１の一部は、素子分離部１３０の下部に配置されており、素子分離部１３０の絶縁層１３１の下面にはＰ型ウェル領域１１１の上面に臨む状態で開口部１３３が形成されており、この開口部１３３を通してシールド電極１３２がＰ型ウェル領域１１１に接触している。
また、Ｐ型ウェル領域１１１の上面には、絶縁層１３１の開口部１３３に対応する位置にＰ＋の高濃度拡散層１１２が形成されており、この高濃度拡散層１１２を介してシールド電極１３２とＰ型ウェル領域１１１とが電気的に導通している。
そして、素子分離部１３０の上部には、共用コンタクト部１４０のプラグ１４１が設けられ、絶縁層１３１の上部を貫通してシールド電極１３２に接触している。 In such an element structure in the pixel, a common contact part 140 that stabilizes the potential of the P-type well region 111 of the silicon substrate 110 and stabilizes the potential of the shield electrode 132 of the element isolation part 130 is provided.
Hereinafter, the shared contact structure of this embodiment will be described.
First, as shown in FIG. 1B, a part of the P-type well region 111 of the silicon substrate 110 is disposed below the element isolation portion 130, and on the lower surface of the insulating layer 131 of the element isolation portion 130. An opening 133 is formed so as to face the upper surface of the P-type well region 111, and the shield electrode 132 is in contact with the P-type well region 111 through the opening 133.
A P + high concentration diffusion layer 112 is formed on the upper surface of the P-type well region 111 at a position corresponding to the opening 133 of the insulating layer 131, and the shield electrode 132 is connected to the P type well region 111 via the high concentration diffusion layer 112. The P-type well region 111 is electrically connected.
A plug 141 of the shared contact part 140 is provided on the upper part of the element isolation part 130 and penetrates the upper part of the insulating layer 131 and is in contact with the shield electrode 132.

したがって、本実施例の共用コンタクト構造では、共用コンタクト部１４０のプラグ１４１がシールド電極１３２に接続され、さらにこのシールド電極１３２及び高濃度拡散層１１２を介してＰ型ウェル領域１１１に接続され、共通の基準電位（例えばＧＮＤ等）に保持される。
この結果、同一画素内にＰ型ウェル領域１１１とシールド電極１３２のコンタクトを個別に設ける場合に比べて、コンタクトの数を削減でき、コンタクトの配置面積の縮小によって画素の微細化や開口率の拡大による撮像特性の向上等に貢献できる。 Therefore, in the shared contact structure of the present embodiment, the plug 141 of the shared contact portion 140 is connected to the shield electrode 132 and further connected to the P-type well region 111 via the shield electrode 132 and the high concentration diffusion layer 112. Is maintained at a reference potential (eg, GND).
As a result, the number of contacts can be reduced as compared with the case where the contacts of the P-type well region 111 and the shield electrode 132 are individually provided in the same pixel, and the pixel is miniaturized and the aperture ratio is increased by reducing the contact arrangement area. This can contribute to the improvement of imaging characteristics.

また、本実施例のように、Ｐ型ウェル領域１１１の上にシールド電極１３２を配置し、その上方からコンタクトプラグを形成する構成により、加工誤差によってコンタクトホールを深く形成した場合でも、適正なコンタクト状態を維持できる効果がある。
例えば、図２に示すように、コンタクトプラグ１４１が素子分離部１３０の下面を突き抜けたように形成された場合でも、コンタクトプラグ１４１とシールド電極１３２及びＰ型ウェル領域１１１との導通状態は維持できる。したがって、エッチング等の加工精度を厳格に制御する必要性が小さくなり、形成工程の容易化を実現できる。 Further, as in this embodiment, the shield electrode 132 is disposed on the P-type well region 111, and the contact plug is formed from above, so that even when the contact hole is deeply formed due to a processing error, an appropriate contact is obtained. There is an effect of maintaining the state.
For example, as shown in FIG. 2, even when the contact plug 141 is formed so as to penetrate the lower surface of the element isolation part 130, the conduction state between the contact plug 141, the shield electrode 132, and the P-type well region 111 can be maintained. . Therefore, the necessity of strictly controlling the processing accuracy such as etching is reduced, and the formation process can be facilitated.

なお、図２では、加工時の誤差によってコンタクトプラグ１４１の下端がＰ型ウェル領域１１１まで到達した場合を説明したが、このような素子構造を意図的に採用してもよい。すなわち、コンタクトプラグ１４１がシールド電極１３２を貫通してＰ型ウェル領域１１１の高濃度拡散層１１２まで到達させるような構造とし、シールド電極１３２とＰ型ウェル領域１１１（高濃度拡散層１１２）に直接コンタクトプラグ１４１を接触させて、より確実なコンタクトをとるようにしてもよい。このような構成も本発明に含まれるものとする。
また、上述した実施例では、同一画素内の素子分離部とウェル領域との共用コンタクト部を設ける場合について説明したが、素子のレイアウトによっては、隣接する画素のウェル領域と素子分離部とを一部延在させて重ね合わせ、上述した共用コンタクト部を設けるような構成も可能であり、このような構成も本発明に含まれるものとする。
さらに、図１（Ｂ）に示すＰ＋の高濃度拡散層１１２は通常イオン注入によって形成されるが、別の実施例として高濃度拡散層１１２をシールド電極１３２からの拡散によって形成することも可能である。この場合、高濃度拡散層１１２は非常に浅い接合として形成することが可能になるため、フォトダイオード１２０との電界を緩和してノイズを抑制することができる利点も生ずる。このような構成例も本発明に含まれるものとする。 In FIG. 2, the case where the lower end of the contact plug 141 reaches the P-type well region 111 due to an error during processing has been described, but such an element structure may be intentionally employed. That is, the contact plug 141 penetrates the shield electrode 132 and reaches the high-concentration diffusion layer 112 in the P-type well region 111, and directly contacts the shield electrode 132 and the P-type well region 111 (high-concentration diffusion layer 112). The contact plug 141 may be brought into contact to make a more reliable contact. Such a configuration is also included in the present invention.
In the above-described embodiments, the case where the common contact portion between the element isolation portion and the well region in the same pixel is provided has been described. However, depending on the element layout, the well region and the element isolation portion of adjacent pixels may be integrated. It is also possible to adopt a configuration in which the common contact portions described above are provided by extending and overlapping the portions, and such a configuration is also included in the present invention.
Further, although the P + high concentration diffusion layer 112 shown in FIG. 1B is usually formed by ion implantation, as another example, the high concentration diffusion layer 112 can also be formed by diffusion from the shield electrode 132. is there. In this case, since the high-concentration diffusion layer 112 can be formed as a very shallow junction, there is an advantage that noise can be suppressed by relaxing the electric field with the photodiode 120. Such a configuration example is also included in the present invention.

本発明の実施例による固体撮像素子の要部の構造を示す平面図及び断面図である。It is the top view and sectional drawing which show the structure of the principal part of the solid-state image sensor by the Example of this invention. 図１に示す固体撮像素子において共用コンタクト部に加工誤差が生じた状態を示す断面図である。FIG. 2 is a cross-sectional view showing a state where a processing error has occurred in a shared contact portion in the solid-state imaging device shown in FIG. 従来の固体撮像素子の一例を示す平面図及び断面図である。It is the top view and sectional drawing which show an example of the conventional solid-state image sensor. 従来の固体撮像素子の他の例を示す平面図及び断面図である。It is the top view and sectional drawing which show the other example of the conventional solid-state image sensor. 従来の固体撮像素子のさらに他の例を示す平面図及び断面図である。It is the top view and sectional drawing which show the other example of the conventional solid-state image sensor. 従来の固体撮像素子のさらに他の例を示す平面図及び断面図である。It is the top view and sectional drawing which show the other example of the conventional solid-state image sensor.

符号の説明Explanation of symbols

１１０……シリコン基板、１１１……Ｐ型ウェル領域、１１２……高濃度拡散層、１２０……フォトダイオード、１２１……ドレイン部、１２２……ゲート絶縁膜、１２３……転送電極、１３０……素子分離部、１３１……絶縁層、１３２……シールド電極、１３３……開口部、１４０……共用コンタクト部、１４１……コンタクトプラグ。   DESCRIPTION OF SYMBOLS 110 ... Silicon substrate, 111 ... P-type well region, 112 ... High concentration diffusion layer, 120 ... Photodiode, 121 ... Drain part, 122 ... Gate insulating film, 123 ... Transfer electrode, 130 ... Element isolation part, 131... Insulating layer, 132... Shield electrode, 133... Opening, 140 .. common contact part, 141.

Claims (7)

半導体基板に設けられたウェル領域中に形成される光電変換部と、
前記半導体基板上に設けられた絶縁層中にシールド電極を埋設して形成される素子分離部と、
前記ウェル領域と前記シールド電極の電位安定化を行う共用コンタクト部と、
を有することを特徴とする固体撮像素子。 A photoelectric conversion part formed in a well region provided in a semiconductor substrate;
An element isolation portion formed by burying a shield electrode in an insulating layer provided on the semiconductor substrate;
A common contact portion for stabilizing the potential of the well region and the shield electrode;
A solid-state imaging device comprising: 前記共用コンタクト部は同一画素内のウェル領域とシールド電極に設けられていることを特徴とする請求項１記載の固体撮像素子。   The solid-state imaging device according to claim 1, wherein the shared contact portion is provided in a well region and a shield electrode in the same pixel. 前記素子分離部がウェル領域上に配置されるとともに、前記ウェル領域とシールド電極が導通されていることを特徴とする請求項１記載の固体撮像素子。   The solid-state imaging device according to claim 1, wherein the element isolation portion is disposed on a well region, and the well region and a shield electrode are electrically connected. 前記シールド電極が絶縁層の底面に形成された開口部を介してウェル領域に形成された高濃度拡散層に接続されていることを特徴とする請求項３記載の固体撮像素子。   4. The solid-state imaging device according to claim 3, wherein the shield electrode is connected to a high-concentration diffusion layer formed in the well region through an opening formed in the bottom surface of the insulating layer. 前記共用コンタクト部のコンタクトプラグはシールド電極に接触していることを特徴とする請求項３記載の固体撮像素子。   The solid-state imaging device according to claim 3, wherein the contact plug of the shared contact portion is in contact with a shield electrode. 前記共用コンタクト部のコンタクトプラグはシールド電極に接触するとともに、シールド電極を貫通してウェル領域の高濃度拡散層に接触していることを特徴とする請求項３記載の固体撮像素子。   4. The solid-state imaging device according to claim 3, wherein the contact plug of the shared contact portion is in contact with the shield electrode, and is in contact with the high concentration diffusion layer in the well region through the shield electrode. 前記素子分離部がウェル領域上に配置され、前記共用コンタクト部のコンタクトプラグはシールド電極に接触するとともに、シールド電極を貫通してウェル領域に形成された高濃度拡散層に接触していることを特徴とする請求項１記載の固体撮像素子。   The element isolation portion is disposed on the well region, and the contact plug of the shared contact portion is in contact with the shield electrode and is in contact with the high concentration diffusion layer formed in the well region through the shield electrode. The solid-state imaging device according to claim 1, characterized in that:
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