JP2010098192A - Photoelectric conversion device, imaging system, and method of manufacturing photoelectric conversion device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve condensing efficiency to a semiconductor region which functions as a photoelectric conversion part in a photoelectric conversion device. <P>SOLUTION: The photoelectric conversion device is provided with: a semiconductor substrate including a first semiconductor region which functions as the photoelectric conversion part and a second semiconductor region which functions as a source electrode or a drain electrode; a gate electrode arranged on the semiconductor substrate; and a contact plug which contacts with both the second semiconductor region and the gate electrode wherein a continuous surface is formed of the upper surface of the contact plug and at least a part of the upper surface of the gate electrode. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a photoelectric conversion device, an imaging system, and a method for manufacturing a photoelectric conversion device.

  In recent years, photoelectric conversion devices such as CCD image sensors and CMOS sensors have been used in two-dimensional image input devices centering on digital still cameras and video camcorders. Alternatively, the photoelectric conversion device is used in a one-dimensional image reading device centering on a facsimile and a scanner.

  Patent Document 3 describes that in the solid-state imaging device 20, the floating diffusion region 28 and the gate electrode portion 34 a are connected by a metal plug 40 as shown in FIG. 2 of Patent Document 3.

  On the other hand, in Patent Document 1, as shown in FIG. 1 of Patent Document 1, it is described that a source / drain region 7 and a gate electrode 6 are directly connected by a polycrystalline silicon plug layer 15 in an SRAM memory cell. ing.

Patent Document 2 describes that, as shown in FIG. 1 of Patent Document 2, in an SRAM, an N ⁺ diffusion layer and a gate electrode G2 are connected by a shared contact C2.
Japanese Patent Laid-Open No. 05-041378 JP 09-055440 A JP 2002-368203 A

  In the photoelectric conversion device, a case is considered in which a shared contact plug that connects a semiconductor region in a semiconductor substrate and a gate electrode on the semiconductor substrate and is not connected to a wiring layer is provided. In this case, it is necessary to provide the wiring layer at a position higher than the shared contact plug from the surface of the semiconductor substrate.

  Here, when the wiring layer defines an opening region above the photodiode, the light receiving surface of the photodiode is affected by the wiring layer as the wiring layer is provided at a higher position from the surface of the semiconductor substrate. There is a possibility that the light collection efficiency will decrease.

  The objective of this invention is improving the condensing efficiency to the semiconductor region which functions as a photoelectric conversion part in a photoelectric conversion apparatus.

  A photoelectric conversion device according to a first aspect of the present invention includes a semiconductor substrate including a first semiconductor region that functions as a photoelectric conversion unit and a second semiconductor region that functions as a source electrode or a drain electrode, and an upper surface of the semiconductor substrate. And a contact plug in contact with both the second semiconductor region and the gate electrode, the surface being continuous by the upper surface of the contact plug and at least a part of the upper surface of the gate electrode Is formed.

  An imaging system according to a second aspect of the present invention is the photoelectric conversion device according to any one of claims 1 to 4, an optical system that forms an image on an imaging surface of the photoelectric conversion device, and the photoelectric conversion device. And a signal processing unit that generates image data by processing the signal output from the control unit.

  In the method for manufacturing a photoelectric conversion device according to the third aspect of the present invention, a gate electrode is formed on a semiconductor substrate, and a first semiconductor region functioning as a photoelectric conversion unit and a source electrode or drain are formed in the semiconductor substrate. A first step of forming a second semiconductor region functioning as an electrode; a second step of forming an insulating film so as to cover the surface of the semiconductor substrate and the gate electrode; and the second semiconductor region A third step of forming a contact hole in the insulating film so as to expose an upper surface of the gate electrode and at least a part of the upper surface of the gate electrode, a fourth step of embedding a conductor in the contact hole, and the gate And a fifth step of polishing the insulating film and the conductor so that a part of the upper surface of the electrode is exposed.

  In the method for manufacturing a photoelectric conversion device according to the fourth aspect of the present invention, a gate electrode is formed on a semiconductor substrate, and a first semiconductor region functioning as a photoelectric conversion unit and a source electrode or drain are formed in the semiconductor substrate. A first step of forming a second semiconductor region functioning as an electrode, a sixth step of forming a first insulating film covering a part of the upper surface of the gate electrode, a surface of the semiconductor substrate, A seventh step of forming a second insulating film so as to cover the first insulating film and the gate electrode; and exposing an upper surface of the first semiconductor region and at least a part of the upper surface of the gate electrode. By performing dry etching as described above, an eighth step of forming a contact hole in the second insulating film, a ninth step of embedding a conductor in the contact hole, and an upper surface of the first insulating film Dew As, characterized by comprising a tenth step of polishing the second insulating film and the conductor.

  ADVANTAGE OF THE INVENTION According to this invention, the condensing efficiency to the semiconductor area | region which functions as a photoelectric conversion part can be improved in a photoelectric conversion apparatus.

  The circuit configuration of the pixel P in the photoelectric conversion device 100 according to the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a diagram illustrating a circuit configuration of a pixel P in the photoelectric conversion device 100 according to the first embodiment of the present invention.

  As shown in FIG. 1, the pixel P includes a photoelectric conversion unit 31, a transfer transistor 32, a floating diffusion (FD) 33, a reset transistor 34, an amplification transistor 36, and a selection transistor 35.

  When light enters the light receiving surface, the photoelectric conversion unit 31 generates and accumulates charges (electrons here) corresponding to the light. The photoelectric conversion unit 31 is, for example, a photodiode, and accumulates charges generated by performing photoelectric conversion at the interface between the anode and the cathode on the cathode. When the transfer transistor 32 is turned on, the transfer transistor 32 transfers the charge generated in the photoelectric conversion unit 31 to the FD 33. The FD 33 converts the transferred charge into a voltage. The reset transistor 34 resets the FD 33 when turned on. The amplification transistor 36 outputs a signal corresponding to the voltage of the FD 33 to the vertical signal line 37 by performing a source follower operation together with the constant current source 38 connected to the vertical signal line 37. That is, the amplification transistor 36 outputs a noise signal corresponding to the voltage of the FD 33 to the vertical signal line 37 in a state where the FD 33 is reset by the reset transistor 34. The amplification transistor 36 outputs an optical signal corresponding to the voltage of the FD 33 to the vertical signal line 37 in a state where the charge generated in the photoelectric conversion unit 31 is transferred to the FD 33 by the transfer transistor 32. The selection transistor 35 brings the pixel P into a selected state when turned on, and puts the pixel P into a non-selected state when turned off. When the selection state / non-selection state of the pixel P is controlled by the potential of the FD 33, the selection transistor 35 may be omitted from the pixel P, and a plurality of photoelectric conversion units 31 are provided for one amplification transistor 36. It may be.

  Here, the FD 33 is formed as a semiconductor region containing impurities in the semiconductor substrate, as will be described later. The second contact plug 11 described later is used, for example, when the FD 33 is connected to the gate electrode of the amplification transistor 36.

  Next, a cross-sectional configuration of the photoelectric conversion apparatus 100 according to the first embodiment of the present invention will be described with reference to FIG. FIG. 2 is a diagram illustrating a cross-sectional configuration of the photoelectric conversion apparatus 100 according to the first embodiment of the present invention. In FIG. 2, electrodes and wirings connecting the MOS transistors are omitted.

  The photoelectric conversion device 100 includes a semiconductor substrate SB, a first gate electrode 8, a second gate electrode 15, a first interlayer insulating film 10, a second interlayer insulating film 12, a wiring layer 14, and a first contact plug 13. , And a second contact plug 11.

  The semiconductor substrate SB includes a P well 1, an element isolation portion 2, a second semiconductor region 3, a first semiconductor region 6, a third semiconductor region 5, and a fourth semiconductor region 4.

  The P well 1 contains P-type impurities at a relatively low concentration.

  The element isolation unit 2 performs element isolation. The element isolation method includes a LOCOS method, a mesa type method, an STI method, etc., and any of the isolation methods is consistent with the gist of the present invention. The element isolation part 2 is made of, for example, silicon oxide.

  The first semiconductor region 6 functions as a photoelectric conversion unit 31 (see FIG. 1) and is a region for accumulating charges generated by photoelectric conversion. The first semiconductor region 6 contains N-type impurities at a concentration higher than the concentration of P-type impurities in the P well 1.

  The second semiconductor region 3 functions as a source electrode or a drain electrode (for example, FD33 which is a drain electrode of the transfer transistor 32 shown in FIG. 1). Second semiconductor region 3 contains N-type impurities at a concentration higher than the concentration of P-type impurities in P well 1.

  The third semiconductor region 5 is a region for protecting the first semiconductor region 6 and making the photoelectric conversion unit 31 (photodiode) have a buried structure. Third semiconductor region 5 contains P-type impurities at a higher concentration than P well 1.

  The fourth semiconductor region 4 is a region containing N-type impurities at a lower concentration than the second semiconductor region 3. The fourth semiconductor region 4 is provided to provide an LDD (Lightly Doped Drain) structure.

  The fifth semiconductor region 41 functions as a source electrode or a drain electrode (for example, a source electrode or a drain electrode for the second gate electrode 15). The fifth semiconductor region 41 includes an N-type impurity at a concentration higher than the concentration of the P-type impurity in the P well 1.

  The first gate electrode 8 is disposed on the semiconductor substrate SB via the gate insulating film 7. Side spacers 31b are arranged on the side surfaces of the first gate electrode 8 and the region adjacent to the side surfaces of the first gate electrode 8 on the surface of the semiconductor substrate SB via the liner insulating film 31a. Here, a stress relaxation film may be further provided between the liner insulating film 31 a and the first gate electrode 8.

  Note that a liner insulating film 21a that functions as an antireflection film is formed on the first semiconductor region 6 and the third semiconductor region 5 in the same manner as the liner insulating film 31a, and is formed and protected in the same manner as the side spacer 31b. An insulating film 21b that functions as a film may be provided.

  The second gate electrode 15 is disposed on the semiconductor substrate SB via the gate insulating film 17. Side spacers 9b are disposed on the side surfaces of the second gate electrode 15 and the regions adjacent to the side surfaces of the second gate electrode 15 on the surface of the semiconductor substrate SB via the liner insulating film 9a.

  The upper surface 15a of the second gate electrode 15 includes a first region 15a1 and a second region 15a2. The first region 15a1 is lower in height than the upper surface 11a of the second contact plug 11. The second region 15a2 has the same height as the upper surface 11a of the second contact plug 11. The first region 15a1 is located closer to the second semiconductor region 3 than the second region 15a2.

  The first interlayer insulating film 10 is disposed so as to cover the surface SBa of the semiconductor substrate SB. The second interlayer insulating film 12 is disposed so as to cover the first interlayer insulating film 10, the first gate electrode 8, the second contact plug 11, and the second gate electrode 15. The first interlayer insulating film 10 and the second interlayer insulating film 12 insulate the surface SBa of the semiconductor substrate SB from the wiring layer 14.

  The wiring layer 14 is disposed on the second interlayer insulating film 12. That is, the wiring layer 14 is arranged above the second contact plug 11 so as to define an opening region OA for the first semiconductor region 6 (photoelectric conversion unit 31). Here, the opening area OA may be defined by a wiring layer other than the wiring layer 14.

  The first contact plug 13 is electrically connected to a contact hole penetrating the second interlayer insulating film 12 and the first interlayer insulating film 10 so as to electrically connect the fifth semiconductor region 41 and the wiring layer 14. The body is arranged. Note that the first contact plug 13 may have a stacked via shape in which a lower contact plug plug and an upper contact plug plug are stacked (see FIG. 7).

  The second contact plug 11 is formed by arranging a conductor in the contact hole so as to electrically connect the second semiconductor region 3 and the second gate electrode 15. The second contact plug 11 is in contact with both the second semiconductor region 3 and the second gate electrode 15. The second contact plug 11 is also called a shared contact plug in the sense that the contact plug of the second semiconductor region 3 and the contact plug of the second gate electrode 15 are shared. The second contact plug 11 is not connected to the wiring layer 14.

  A continuous surface is formed by the upper surface 11 a of the second contact plug 11 and the second region 15 a 2 far from the second semiconductor region 3 on the upper surface 15 a of the second gate electrode 15. Thereby, the height from the surface SBa of the semiconductor substrate SB of the wiring layer 14 that defines the opening region OA with respect to the first semiconductor region 6 (photoelectric conversion unit 31) can be suppressed. As a result, the light collection efficiency to the semiconductor region functioning as the photoelectric conversion unit can be improved.

  The first region 15a1 is lower in height than the upper surface 11a of the second contact plug 11, and is located closer to the second semiconductor region 3 than the second region 15a2. Accordingly, even when a continuous surface is formed by the upper surface 11a of the second contact plug 11 and the second region 15a2 on the upper surface 15a of the second gate electrode 15, the second semiconductor region 3 and the second gate are formed. It is easy to electrically connect the electrode 15 sufficiently.

  Next, a method for manufacturing the photoelectric conversion device 100 according to the first embodiment of the present invention will be described with reference to FIGS. 3A to 3E are process cross-sectional views illustrating the method for manufacturing the photoelectric conversion device 100 according to the first embodiment of the present invention.

  In the step shown in FIG. 3A, first, a P well 1 and an N well (not shown) and an element isolation portion 2 are formed in a semiconductor substrate SB such as silicon. The element isolation portion 2 is formed by STI, selective oxidation, or the like.

  Next, the gate insulating film 7i is formed on the semiconductor substrate SB by a thermal oxidation method or a CVD method. A first gate electrode 8 and a second gate electrode 15 are formed by forming and patterning a polysilicon layer to be a gate electrode on the gate insulating film 7i on the semiconductor substrate SB (first gate electrode 15). Process).

  By injecting an n-type impurity into the semiconductor substrate SB, the first semiconductor region 6 functioning as the photoelectric conversion unit 31 is formed in the semiconductor substrate SB (in the semiconductor substrate) with a high concentration (first step). In addition, by implanting p-type impurities into the semiconductor substrate SB, the third semiconductor region 5 for protecting the first semiconductor region 6 is formed in the vicinity of the surface SBa of the semiconductor substrate SB at a high concentration. The order of forming the gate electrode and the semiconductor region can be selected as appropriate.

  Then, by implanting n-type impurities into the semiconductor substrate SB using the resist pattern and the gate electrode as a mask, the semiconductor region 4i to be the fourth semiconductor region 4 is formed in the vicinity of the surface SBa of the semiconductor substrate SB at a low concentration. . The semiconductor region 4i is a region that is self-aligned with the first gate electrode 8, the second gate electrode 15, and the like.

  Next, a liner insulating film 9ai (first insulating film) is formed so as to cover the surface SBa of the semiconductor substrate SB, the first gate electrode 8, and the second gate electrode 15. An insulating film 9bi to be a side spacer is formed on the liner insulating film 9ai.

  In the step shown in FIG. 3B, the liner insulating film 9ai and the insulating film 9bi are etched back by anisotropic dry etching. Thereby, the liner insulating film 31 a and the side spacer 31 b are formed so as to be adjacent to the side surface of the first gate electrode 8. A liner insulating film 9 a and side spacers 9 b are formed so as to be adjacent to the side surface of the second gate electrode 15.

  The first semiconductor region 6 and the third semiconductor region 5 are covered with a resist and then anisotropic dry etching is performed, so that the liner is formed on the first semiconductor region 6 and the third semiconductor region 5. The insulating film 21a and the insulating film 21b may be formed. The liner insulating film 21a functions as an antireflection film and functions as a protective film that protects the first semiconductor region 6 from damage. In this case, the liner insulating film 9ai is preferably formed of silicon nitride, and the insulating film 9bi is preferably formed of silicon oxide. Further, it is not always necessary to perform anisotropic dry etching on the liner insulating film 9ai and the insulating film 9bi.

  Next, an n-type impurity is implanted into the semiconductor substrate SB using the resist pattern, the gate electrode, and the side spacer as a mask, so that the second semiconductor region 3 and the fifth semiconductor region 41 are placed in the semiconductor substrate SB (semiconductor substrate SB). The inner layer) at a high concentration (first step). The second semiconductor region 3 and the fifth semiconductor region 41 are regions that are self-aligned with the side surfaces of the side spacer 31b. The second semiconductor region 3 and the fifth semiconductor region 41 constitute a transistor having an LDD structure with the fourth semiconductor region 4 formed under the side spacer 31b.

  In the step shown in FIG. 3C, an insulating film 10i is deposited so as to cover the surface SBa of the semiconductor substrate SB, the first gate electrode 8, and the second gate electrode 15, and the surface is polished to be flat. To do. Thereby, an insulating film 10i (second insulating film) to be the first interlayer insulating film 10 is formed (second step).

  Next, a contact hole is formed in the insulating film 10i so as to expose the upper surface of the second semiconductor region 3 and the first region 15a1, which is a part of the upper surface 15a of the second gate electrode 15 (third). Process).

  Then, a conductive material is deposited in the contact hole and on the surface of the insulating film 10i. That is, the conductor 11i is embedded in the contact hole (fourth step).

  In the step shown in FIG. 3D, the insulating film 10i and the conductor 11i are polished so that the upper surface of the conductor 11i is close to the upper surface 15a of the second gate electrode 15 (fifth step). Specifically, the second contact plug 11 and the first interlayer insulating film 10 are formed by polishing the surface conductive material and the surface of the underlying insulating film 10i. At this time, polishing is performed until the second region 15a2 on the upper surface 15a of the second gate electrode 15 is exposed.

  Note that polishing may be performed using the second gate electrode 15 as a stopper layer by utilizing the difference in polishing rate between the insulating film 10 i and the second gate electrode 15.

  Next, as shown in FIG. 2, a second interlayer insulating film (other insulating film) 12 is deposited and formed so as to cover the polished first interlayer insulating film 10 and second contact plug 11. (Sixth step).

  Contact holes are formed in the second interlayer insulating film 12 and the first interlayer insulating film 10 so as to expose the upper surfaces of the second semiconductor region 3 and the fifth semiconductor region 41. Then, a first contact plug 13 is formed by embedding a conductor in the contact hole.

  Next, a wiring layer 14 is formed on the second interlayer insulating film 12 so as to define an opening region OA for the first semiconductor region 3 (seventh step).

  In this way, a continuous surface is formed by the upper surface of the second contact plug and a part of the upper surface of the second gate electrode. Therefore, a sufficient distance between the upper surface of the second contact plug and the wiring layer can be secured, so that the parasitic capacitance between the second contact plug and the wiring layer can be increased even when the height of the wiring layer is lowered. Can be suppressed.

  Note that the contact area between the two contact plugs may be smaller than when the upper surface of the second contact plug is higher than the upper surface of the second gate electrode. Even in this case, since the contact area with the second semiconductor region is dominant as an element for determining the contact plug resistance in the second contact plug, the increase in resistance is slight.

  According to the present embodiment, in the photoelectric conversion device using the second contact plug that is simultaneously connected to the second gate electrode and the second semiconductor region and is not connected to the wiring layer, the light collection efficiency is improved for the following reason. Can be raised.

  The upper surface of the second contact plug and the upper surface of the second gate electrode are the same flat surface that is continuous. Accordingly, the second contact plug can be lowered by a portion higher than the second gate electrode that does not contribute to the connection between the second gate electrode and the second semiconductor region in the second contact plug. As a result, since the height from the semiconductor substrate to the wiring layer can also be reduced, the light collection efficiency of the light passing through the opening region defined by the wiring layer to the first semiconductor region is increased.

  Next, an example of an imaging system to which the photoelectric conversion device of the present invention is applied is shown in FIG.

  As shown in FIG. 4, the imaging system 90 mainly includes an optical system, an imaging device 86, and a signal processing unit. The optical system mainly includes a shutter 91, a lens 92, and a diaphragm 93. The imaging device 86 includes a photoelectric conversion device 100. The signal processing unit mainly includes an imaging signal processing circuit 95, an A / D converter 96, an image signal processing unit 97, a memory unit 87, an external I / F unit 89, a timing generation unit 98, an overall control / calculation unit 99, and a recording. A medium 88 and a recording medium control I / F unit 94 are provided. The signal processing unit may not include the recording medium 88.

  The shutter 91 is provided in front of the lens 92 on the optical path, and controls exposure.

  The lens 92 refracts the incident light to form an image of the subject on the imaging surface of the photoelectric conversion device 100 of the imaging device 86.

  The diaphragm 93 is provided between the lens 92 and the photoelectric conversion device 100 on the optical path, and adjusts the amount of light guided to the photoelectric conversion device 100 after passing through the lens 92.

  The photoelectric conversion device 100 of the imaging device 86 converts the subject image formed on the imaging surface of the photoelectric conversion device 100 into an image signal. The imaging device 86 reads the image signal from the photoelectric conversion device 100 and outputs it.

  The imaging signal processing circuit 95 is connected to the imaging device 86 and processes the image signal output from the imaging device 86.

  The A / D converter 96 is connected to the imaging signal processing circuit 95 and converts the processed image signal (analog signal) output from the imaging signal processing circuit 95 into an image signal (digital signal).

  The image signal processing unit 97 is connected to the A / D converter 96, and performs various kinds of arithmetic processing such as correction on the image signal (digital signal) output from the A / D converter 96 to generate image data. To do. The image data is supplied to the memory unit 87, the external I / F unit 89, the overall control / calculation unit 99, the recording medium control I / F unit 94, and the like.

  The memory unit 87 is connected to the image signal processing unit 97 and stores the image data output from the image signal processing unit 97.

  The external I / F unit 89 is connected to the image signal processing unit 97. Thus, the image data output from the image signal processing unit 97 is transferred to an external device (such as a personal computer) via the external I / F unit 89.

  The timing generation unit 98 is connected to the imaging device 86, the imaging signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97. Thereby, a timing signal is supplied to the imaging device 86, the imaging signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97. The imaging device 86, the imaging signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97 operate in synchronization with the timing signal.

  The overall control / arithmetic unit 99 is connected to the timing generation unit 98, the image signal processing unit 97, and the recording medium control I / F unit 94, and the timing generation unit 98, the image signal processing unit 97, and the recording medium control I / F. The unit 94 is controlled as a whole.

  The recording medium 88 is detachably connected to the recording medium control I / F unit 94. As a result, the image data output from the image signal processing unit 97 is recorded on the recording medium 88 via the recording medium control I / F unit 94.

  With the above configuration, if a good image signal is obtained in the photoelectric conversion device 100, a good image (image data) can be obtained.

  Next, a photoelectric conversion device 200 according to the second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a diagram illustrating a cross-sectional configuration of a photoelectric conversion apparatus 200 according to the second embodiment of the present invention. Below, it demonstrates centering on a different part from 1st Embodiment.

  The photoelectric conversion device 200 includes a liner insulating film 209a and a second contact plug 211. The liner insulating film 209a is disposed so as to cover the second region 15a2 which is a part of the upper surface 15a of the second gate electrode so as to protect from damage caused by dry etching. The liner insulating film 209a also functions as an antireflection film. The liner insulating film 209a prevents reflection of light on the upper surface 15a of the second gate electrode 15. A side space 209b is disposed on the side surface of the second gate electrode via a liner insulating film 209a.

  Here, a continuous surface is formed by the upper surface 211a of the second contact plug 211 and the upper surface 209a1 of the liner insulating film 209a. Accordingly, the height from the surface SBa of the semiconductor substrate SB of the wiring layer 14 that defines the opening region OA to the first semiconductor region 6 (photoelectric conversion unit 31) can be suppressed to be low in the first embodiment. It is the same as the form.

  Moreover, the manufacturing method of the photoelectric conversion apparatus 100 differs from 1st Embodiment by the following points, as shown in FIG. FIG. 6 is a process cross-sectional view illustrating the method for manufacturing the photoelectric conversion device 200 according to the second embodiment of the present invention.

  In the step shown in FIG. 6B1, the liner insulating film 209a and the side space are formed on the second region 15a2 by performing anisotropic dry etching after the upper portion of the second region 15a2 is covered with a resist. A power insulating film 209bi is formed (sixth step).

  As shown in FIG. 6B1, a gate electrode portion that does not require the formation of side spacers, that is, a gate electrode wiring portion on an isolation region, a dummy gate electrode used for planarizing an interlayer film, and a large area gate electrode The center of the film may be covered with a resist. Polishing uniformity can be improved by leaving more liner insulating film 9a on the upper surface of the gate electrode.

  Thereafter, an insulating film is formed so as to cover the surface of the semiconductor substrate, the liner insulating film, and the gate electrode (seventh step), which is the same as the step shown in FIG. Also, by performing dry etching, a contact hole is formed in the insulating film (eighth step), and a conductor is embedded in the contact hole (ninth step), similarly to the step shown in FIG. It is.

  In the step shown in FIG. 6D1, the second contact plug 211 and the first interlayer insulating film 10 are formed by polishing the surface conductive material and the surface of the underlying insulating film 10i (the tenth layer). Process). At this time, polishing is performed until the upper surface 209a1 of the liner insulating film 209a is exposed. The liner insulating film 209a can also be used as a polishing stop film. At this time, a side space 209b is formed. Note that the upper surface 209a1 of the liner insulating film 209a may be removed by polishing.

  In the above description, an example using an nMOS transistor has been described. However, when a photoelectric conversion device is manufactured by a CMOS process, a pMOS transistor can be similarly manufactured by changing the conductivity type.

  Further, as shown in FIG. 7, the first contact plug 213j in the photoelectric conversion device 200j may have a stacked via shape in which a lower contact plug 213bj and an upper contact plug 213aj are stacked. That is, in the step shown in FIG. 3C, a through hole for the lower contact plug 213bj is also formed to embed the conductor. Thereby, since the aspect ratio (depth / width) of the through hole for the upper contact plug 213aj can be reduced, the upper contact plug 213aj can be easily formed. That is, the first contact plug 213j can be easily formed as compared with a case where a conductor is embedded in a through hole having a large aspect ratio. Further, by performing the second contact plug and the lower contact plug 213bj in the same process, it is also possible to reduce contamination of metal impurities due to exposing the semiconductor substrate.

  In all the embodiments, the first region 15a1 and the second region 15a2 on the upper surface 15a of the second gate electrode 15 may have the same height, that is, the same surface. For example, in the planarization when the second contact plug shown in FIG. 3D is formed, the first region 15a1 and the second region 15a2 may be planarized until they have the same height. Further, the second gate electrode 15 may be entirely formed on the element isolation portion 2. The second contact plug can function as long as it is connected to the side surface of the second gate electrode.

The figure which shows the circuit structure of the pixel P in the photoelectric conversion apparatus 100 which concerns on 1st Embodiment of this invention. The figure which shows the cross-sectional structure of the photoelectric conversion apparatus 100 which concerns on 1st Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the photoelectric conversion apparatus 100 which concerns on 1st Embodiment of this invention. 1 is a configuration diagram of an imaging system to which a photoelectric conversion device according to a first embodiment is applied. The figure which shows the cross-sectional structure of the photoelectric conversion apparatus 200 which concerns on 2nd Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the photoelectric conversion apparatus 200 which concerns on 2nd Embodiment of this invention. The figure which shows the cross-sectional structure of the photoelectric conversion apparatus 200j which concerns on the modification of 2nd Embodiment of this invention.

Explanation of symbols

100, 200, 200j Photoelectric conversion device

Claims (7)

A semiconductor substrate including a first semiconductor region functioning as a photoelectric conversion portion and a second semiconductor region functioning as a source electrode or a drain electrode;
A gate electrode disposed on the semiconductor substrate;
A contact plug in contact with both the second semiconductor region and the gate electrode;
With
A continuous surface is formed by the upper surface of the contact plug and at least a part of the upper surface of the gate electrode. The upper surface of the gate electrode is
A first region having a height lower than the upper surface of the contact plug;
A second region having the same height as the upper surface of the contact plug;
Including
The first region is located closer to the second semiconductor region than the second region;
The photoelectric conversion device according to claim 1, wherein a continuous surface is formed by the upper surface of the contact plug and the second region on the upper surface of the gate electrode. A semiconductor substrate including a first semiconductor region functioning as a photoelectric conversion portion and a second semiconductor region functioning as a source electrode or a drain electrode;
A gate electrode disposed on the semiconductor substrate;
An insulating film disposed to cover a part of the upper surface of the gate electrode;
A contact plug in contact with both the second semiconductor region and the gate electrode;
With
A continuous surface is formed by the upper surface of the contact plug and the upper surface of the insulating film. The photoelectric conversion device according to claim 3, wherein the insulating film functions as an antireflection film. The photoelectric conversion device according to any one of claims 1 to 4,
An optical system that forms an image on the imaging surface of the photoelectric conversion device;
A signal processing unit that processes the signal output from the photoelectric conversion device to generate image data;
An imaging system comprising: A gate electrode is formed on a semiconductor substrate, and a first semiconductor region functioning as a photoelectric conversion portion and a second semiconductor region functioning as a source electrode or a drain electrode are formed in the semiconductor substrate. Process,
A second step of forming an insulating film so as to cover the surface of the semiconductor substrate and the gate electrode;
A third step of forming a contact hole in the insulating film so as to expose the upper surface of the second semiconductor region and at least a part of the upper surface of the gate electrode;
A fourth step of embedding a conductor in the contact hole;
A fifth step of polishing the insulating film and the conductor so that a part of the upper surface of the gate electrode is exposed;
A method for manufacturing a photoelectric conversion device, comprising: A gate electrode is formed on a semiconductor substrate, and a first semiconductor region functioning as a photoelectric conversion portion and a second semiconductor region functioning as a source electrode or a drain electrode are formed in the semiconductor substrate. Process,
A sixth step of forming a first insulating film covering a part of the upper surface of the gate electrode;
A seventh step of forming a second insulating film so as to cover the surface of the semiconductor substrate, the first insulating film, and the gate electrode;
An eighth step of forming a contact hole in the second insulating film by performing dry etching so as to expose the upper surface of the second semiconductor region and at least a part of the upper surface of the gate electrode;
A ninth step of embedding a conductor in the contact hole;
A tenth step of polishing the second insulating film and the conductor so that an upper surface of the first insulating film is exposed;
A method for manufacturing a photoelectric conversion device, comprising:

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