JP2006086339A - Multilayer substrate and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer substrate with high flexibility of design and high performance suitable for high density mounting and to provide a method of manufacturing the same. <P>SOLUTION: The multilayer substrate 44 includes a plurality of laminated insulating layers, and a wiring pattern formed between the respective insulating layers. The wiring pattern has a first wiring pattern 22 having a predetermined thickness and a second wiring pattern 23 thinner than the first wiring pattern. The second wiring pattern 23 is constituted as a laminate of a plurality of conductive layers with different etching rates. This multilayer substrate 44 is manufactured by forming the first wiring pattern 22 by pattern etching the one surface of a cladding material constituted as a laminate of a plurality of conductive layers with different etching rates, then adhering the one surface of this cladding material to the front surface of the insulating layer for constituting the part of the multilayer substrate, pattern etching the other surface of the cladding material adhered onto the insulating layer, and forming the second wiring pattern 23. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a multilayer substrate and a manufacturing method thereof, and more particularly to a multilayer substrate having patterns and via hole electrodes having different thicknesses and a manufacturing method thereof.

  In recent years, the demand for high-density mounting has become increasingly severe. For this reason, a “multilayer board” in which a plurality of insulating layers are stacked is often used as a board for various modules mounted on a printed board.

  The production of the multilayer substrate is performed by forming a wiring pattern or the like on each insulating layer constituting the multilayer substrate and laminating them. Connections between wiring patterns formed in different insulating layers are made through via holes penetrating the insulating layers (see Patent Documents 1 and 2).

  In forming a wiring pattern on each insulating layer, there are generally used two types of methods, a method called “subtractive method” and a method called “additive method”. In the subtractive method, a desired pattern is formed by etching a conductive layer uniformly formed in advance on an insulating layer. In general, pattern formation by the subtractive method uses a copper foil having a constant thickness as the conductive layer, so that it is easy to obtain the accuracy of the thickness. However, it is difficult to control the width with high accuracy, and the thickness of the conductor increases. It has the property that the width accuracy decreases. In the additive method, a portion desired to be drawn with a dry film, resist, or the like is exposed and developed, and after plating is grown along the pattern, the dry film is removed to complete a desired pattern. Pattern formation by the additive method has high accuracy in the width direction because the accuracy in the width direction is determined by the exposed and developed dry film, etc., but the accuracy in the thickness direction depends on the surface variation of the plating, so thickness variation Is relatively large and it is difficult to control the thickness with high accuracy.

As described above, each of the subtractive method and the additive method has advantages and disadvantages. The additive method is selected when the accuracy in the width direction is important, and the subtractive method is selected when the accuracy in the thickness direction is important. In forming the pattern, it is sufficient to employ either of these two methods, and these two methods are not mixedly performed on the same surface.
Japanese Patent No. 2857270 Japanese Patent Laid-Open No. 10-322021

  In recent years, there has been an increasing demand for so-called embedding in which not only wiring patterns but also inductance (L) and capacitance (C) are built in a substrate. The built-in LC is required to:

  First, in L used for a high-frequency circuit, control in the width direction of the pattern is important in controlling impedance. Even if the thickness of the pattern is thin to some extent, the influence on the transmission characteristics is small. On the other hand, L (choke coil) used in a power supply system smoothing circuit or the like preferably has a low DC resistance. Therefore, it is important how large the cross-sectional area of the conductor pattern can be.

  In C used in a high frequency circuit, it is important to reduce the variation in capacitance, and specifically, it is necessary to suppress the variation in capacitance to ± 5% or less. In order to realize this, control in the width direction of the pattern is important, but there is no problem even if the thickness of the pattern is thin to some extent. Furthermore, regarding the wiring pattern, it is important to reduce variations in the width and thickness of the pattern in order to control the impedance.

  Under such conditions, for example, “matching circuit L”, which requires accuracy in the width direction of the pattern, such as a power amplifier substrate, and DC resistance is required to be as low as possible (the thickness of the conductor is required). In the case where “L (choke coil) for power supply circuit” must be configured, if any of the above-described patterning methods is selected, it is possible to form both L in the same layer of the multilayer substrate. There was a problem that I could not.

  In other words, if a desired accuracy is required for the width and thickness of the pattern, the degree of freedom in design is limited due to structural limitations and contradictions that patterns with different thicknesses cannot be formed in the same layer. It was difficult to answer the demand for higher performance.

  Accordingly, an object of the present invention is to provide a multilayer substrate and a method for manufacturing the same, which have a high degree of design freedom and can arbitrarily select an optimum pattern shape and variation required for each element.

  A multilayer substrate according to the present invention includes a plurality of laminated insulating layers and a wiring pattern formed between the insulating layers, wherein the wiring pattern includes a first wiring pattern having a predetermined thickness, and the first wiring pattern. A second wiring pattern thinner than the wiring pattern is included, and at least one of the first wiring pattern and the second wiring pattern is configured as a stacked body of a plurality of conductive layers having different etching rates. And

  According to the present invention, for example, the matching circuit L and the power supply circuit L (choke coil) can be configured in the same layer, and the optimum pattern shape and variation required for each element can be arbitrarily selected. Therefore, it is possible to realize a multilayer substrate having a high degree of design freedom and suitable for high-density mounting. Here, “in the same layer” means the vicinity of the boundary between the insulating layers that are in contact with each other, and when both the first and second wiring patterns exist over the boundary between the insulating layers, the first and second When both of the two wiring patterns are in contact with one surface of the boundary surface, and either one of the first and second wiring patterns is in contact with one surface of the boundary surface and the other is the other surface of the boundary surface It means to include the case of touching the surface. Note that there may be cases where it is difficult to clearly distinguish the boundary between insulating layers due to the lamination of insulating layers made of the same material, such as when a build-up layer is further formed on the build-up layer. Since it is clear that the first and second wiring patterns exist between the insulating layers, in this case, there is a boundary between the insulating layers near the first and second wiring patterns. Can be considered. Further, according to the present invention, after the clad material is patterned to form a relatively thick wiring pattern in advance, this is pasted on the core substrate, and then the clad material on the core substrate is further patterned to make the relative pattern. Therefore, the wiring pattern can be formed only by the subtractive method. Therefore, it suffices to have equipment for processing by the subtractive method, and equipment for processing by the additive method is completely unnecessary.

  In the present invention, the laminate is composed of two conductive layers, and the combination of the two conductive layers includes copper (Cu) and aluminum (Al), aluminum (Al) and copper (Cu), and copper (Cu). Nickel (Ni), nickel (Ni) and copper (Cu), copper (Cu) and palladium (Pd), copper (Cu) and silver (Ag), stainless steel (SUS) and palladium (Pd), stainless steel (SUS) It is silver (Ag), silver (Ag) and stainless steel (SUS), or copper (Cu) and stainless steel (SUS). If the combination of the two conductive layers is any one of these, wiring patterns having different thicknesses can be reliably formed by pattern etching of the conductive layers.

  In the present invention, it is preferable to further include a via hole that connects wiring patterns existing in different layers. According to this configuration, the relatively thick second wiring pattern is configured in a substantially loop shape, and the terminal portion of the looped wiring pattern is connected by the via hole, whereby the helical pattern inductance can be configured.

  In the present invention, the thickness (t1) of the second wiring pattern is selected within a range of 1 μm to 18 μm, and the ratio of the thickness of the second wiring pattern to the thickness of the first wiring pattern (t2 / The thickness (t2) of the first wiring pattern is preferably selected so that t1) is in the range of 1.5-20. Within this range, an optimum circuit pattern can be drawn in a required place without hindering the degree of freedom of design.

  In the present invention, at least a part of the first wiring pattern functions as a choke coil. According to this, for example, a multilayer board for a power amplifier having good characteristics can be realized.

  The multilayer substrate manufacturing method according to the present invention includes a first step of pattern-etching one surface of a clad material configured as a laminate of a plurality of conductive layers having different etching rates to form a first wiring pattern; A second step of attaching the one surface of the clad material to the surface of an insulating layer constituting a part of the multilayer substrate; and pattern etching of the other surface of the clad material attached on the insulating layer. And a third step of forming a second wiring pattern having a thickness different from that of the first wiring pattern.

  According to the present invention, patterns having different thicknesses can be formed in the same layer. For example, a thin pattern formed by patterning a conductive layer is an LC pattern for a high frequency circuit and a normal wiring pattern. By making the thick pattern formed by the groove for forming the L pattern for the choke coil, a power amplifier multilayer substrate with good characteristics can be realized. Furthermore, according to the present invention, after a clad material is pattern-etched to form a relatively thick wiring pattern in advance, this is pasted on the core substrate, and then the clad material on the core substrate is further pattern-etched. Since a relatively thin wiring pattern is formed, the wiring pattern can be formed only by the subtractive method. Therefore, it suffices to have equipment for processing by the subtractive method, and equipment for processing by the additive method is completely unnecessary.

  In the present invention, the plurality of conductive layers preferably have different thicknesses, and the thickness of the conductive layer provided on the one surface side of the cladding material is provided on the other surface side of the cladding material. More preferably, it is thicker than the thickness of the conductive layer. According to the present invention, highly accurate wiring patterns having different thicknesses can be reliably formed.

  The clad material is configured as a stacked body of conductive layers in which a first conductive layer, a second conductive layer, and a third conductive layer are sequentially stacked, and the first conductive layer and the third conductive layer are Both are made of a predetermined etching material, the second conductive layer is made of a predetermined etching stop material, and the combination of the etching material and the etching stop material is copper (Cu), aluminum (Al), aluminum (Al), and the like. Copper (Cu), copper (Cu) and nickel (Ni), nickel (Ni) and copper (Cu), copper (Cu) and palladium (Pd), copper (Cu) and silver (Ag), stainless steel (SUS) and Palladium (Pd), stainless steel (SUS) and silver (Ag), silver (Ag) and stainless steel (SUS), or copper (Cu) and stainless steel (SUS) are preferable. If the combination of the cladding material and the etching stop material is any of these, wiring patterns having different thicknesses can be reliably formed by pattern etching of the conductive layer.

  The first conductive layer preferably forms the one surface of the clad material, and the third conductive layer preferably forms the other surface of the clad material. According to this, a relatively thick pattern can be formed by pattern etching of the first conductive layer, and a relatively thin wiring pattern can be formed by pattern etching of the third and second conductive layers. Therefore, wiring patterns having different thicknesses can be reliably formed.

  The present invention preferably further includes a step of forming a via hole and a step of selectively forming a conductive material filling the inside of the via hole. According to this, when filling the inside of the via hole with the conductive material, the conductive material is selectively formed by forming a mask in a region other than the region where the conductive material is formed. Variations can be suppressed, and when a wiring pattern is formed by patterning a conductive layer by a subtractive method, the pattern accuracy can be greatly improved. In addition, since the selectively formed protrusions of the conductive material are mainly polished, warpage is less likely to occur than when the entire surface is polished. Thereby, for example, even when a passive element such as a high-frequency circuit LC is formed on the core substrate, it is possible to suppress variation in impedance.

  In the present invention, the insulating layer may be a core substrate or a build-up layer provided on the core substrate. Furthermore, both of them may be used. When the present invention is applied to both the core substrate and the buildup layer, the thickness variation is reduced for both the wiring pattern formed on the surface of the core substrate and the wiring pattern formed on the surface of the buildup layer. Therefore, the overall pattern accuracy can be improved.

  Thus, according to the present invention, since wiring patterns having different thicknesses can be formed in the same layer, for example, an LC pattern for high frequency circuits and an impedance that require little variation in pattern width and thickness. A normal wiring pattern that requires matching is composed of a first wiring pattern formed by patterning a conductive layer, and a choke that requires a high aspect ratio and a relatively large conductor cross-sectional area (low DC resistance). The coil L pattern can be composed of a relatively thick second wiring pattern, which can be formed in the same layer, and the optimum pattern shape, width and thickness variation required for each element can be arbitrarily set. You can choose. That is, a build-up layer having a high degree of design freedom and suitable for high-density mounting can be manufactured. Further, according to the present invention, after the clad material is patterned to form a relatively thick first wiring pattern in advance, the first wiring pattern is pasted on a thermosetting resin sheet to be a build-up layer, and then build-up is performed. Since the clad material on the layer is further patterned to form a relatively thin second wiring pattern, the wiring pattern can be formed only by the subtractive method. Therefore, it suffices to have equipment for processing by the subtractive method, and equipment for processing by the additive method is completely unnecessary.

  In addition, according to the present invention, since the variation in the thickness of the conductive material caused by polishing is suppressed, when forming a wiring pattern by the subtractive method, the pattern accuracy can be greatly improved. Thereby, for example, even when a passive element such as a capacitor or an inductor is built in the multilayer substrate, it is possible to suppress variations in impedance.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  The method for manufacturing a multilayer substrate according to the present embodiment can be applied to both the “core substrate” constituting the multilayer substrate and the “build-up layer” provided on the core substrate. First, the case where the method for manufacturing a multilayer substrate according to the present embodiment is applied to a “core substrate” will be described with reference to FIGS.

  First, the clad material 10 is prepared (FIG. 1). The clad material 10 before processing is configured as a three-layer laminate in which conductive materials A and B having different etching rates are laminated in the order of A / B / A. That is, the first conductive layer 11 and the third conductive layer 13 are made of the etching material A, and the second conductive layer 12 therebetween is made of the etching stop material B having an etching rate slower than that of the etching material A. The combination of (A / B) is (Cu / Al), (Al / Cu), (Cu / Ni), (Ni / Cu), (Cu / Pd), (Cu / Ag), (SUS / Pd) , (SUS / Ag), (Ag / SUS), (Cu / SUS). A particularly preferred combination is when (A / B / A) is (Cu / Ni / Cu). The thicknesses of the first conductive layer 11 and the third conductive layer 13 are preferably different. In the present embodiment, the first conductive layer 11 is thicker than the third conductive layer 13. The thickness (t1) of the first conductive layer 11 is preferably 1.5 to 20 times the thickness (t3) of the third conductive layer 13, and specifically, the thickness ( It is preferable that t1) is in the range of 1 to 18 μm and the thickness (t2) of the third conductive layer is in the range of 12 to 70 μm.

  Next, dry films 14A and 14B made of a photosensitive material are attached to both surfaces of the clad material 10 (FIG. 2). As a result, the surface of the first conductive layer 11 is covered with the dry film 14A, and the surface of the third conductive layer 13 is covered with the dry film 14B. Then, the dry film 14A is exposed and developed to pattern the dry film, thereby exposing the first conductive layer 11 (FIG. 3).

  Next, the first conductive layer 11 of the clad material 10 is etched using the dry film 14A as a mask (FIG. 4). Thereby, the first conductive layer 11 is patterned, and a relatively thick wiring pattern (first wiring pattern) is formed. At this time, since the second conductive layer 12 as an etching stop material exists between the first conductive layer 11 and the third conductive layer 13, the second conductive layer 12 is slightly etched. However, the cladding material 10 is not completely etched down to the third conductive layer 13. In addition, as an etching liquid at this time, it is preferable to select the following with respect to the combination of an etching material and an etching stop material. That is, when the (etching material / etching stop material) combination is (Cu / Al), an acidic etching solution (sulfuric acid, etc.) is used, and when (Al / Cu) is used, an alkaline etching solution is used (Cu / Ni). In the case of (Ni / Cu), sulfuric acid + hydrogen peroxide etching solution, ammonium persulfate etching solution, or alkaline etching solution, and in the case of (Ni / Cu), commercially available Ni stripping solution, (Cu / Pd), (Cu / Ag), (SUS / Pd) or (SUS / Ag), ferric chloride is preferably used, and in either case (Ag / SUS) or (Cu / SUS), ferric nitrate is preferably used. . Thereafter, the dry films 14A and 14B are peeled off (FIG. 5), and the patterning of the clad material 10 is completed.

  Next, two patterned clad materials 10 described above are prepared, a core substrate 15 is prepared, and two clad materials (hereinafter referred to as clad materials 10A and 10B) are bonded to both surfaces of the core substrate 15, respectively. (FIG. 6). The core substrate 15 serves as an insulating layer for the multilayer substrate and also serves to ensure the overall mechanical strength in the production of the multilayer substrate. Although not particularly limited, the core substrate 15 is made of glass cloth. It is preferable to use a material impregnated with a thermosetting resin, a thermoplastic resin or the like in a core material made of a resin cloth such as a Kevlar or liquid crystal polymer, a porous sheet of a fluororesin, etc. It is preferable to set to about 200 μm. For the purpose of uniformizing the laser processing conditions, a sheet material without a core material such as LCP, PPS, PES, PEEK, PI may be used as the core substrate. If the clad materials 10A and 10B are bonded to the core substrate 15 so that the pattern-etched surface (that is, the first conductive layer 11) faces the core substrate 15 side, and this laminate is pressed, the core substrate Since 15 is cured, the cladding materials 10A and 10B are integrated with the core substrate 15 (FIG. 7).

  Next, dry films 16A and 16B are respectively attached to both surfaces of the core substrate 15 to which the cladding materials 10A and 10B are attached (FIG. 8). Thereby, the surface of the third conductive layer 13 of the clad material 10A is covered with the dry film 16A, and the surface of the third conductive layer 13 of the clad material 10B is covered with the dry film 16B. Then, by exposing and developing the dry film 16A, a part thereof is removed, and a part 13a of the third conductive layer of the clad material 10A is exposed (FIG. 9).

  Next, the cladding material 10A is etched using the dry film 16A as a mask to expose a portion of the core substrate 15 (FIG. 10). The exposed region 15a becomes an opening of a via hole. At this time, the first conductive layer 11 of the clad material 10A is already removed in the first etching step, and the third conductive layer 13 that is an etching material and the second conductive layer that is an etching stop material are formed on the core substrate 15. Since the conductive layer 12 remains, the third conductive layer 13 and the second conductive layer 12 are completely removed by etching them using an etching solution having a strong etching power, and the surface of the core substrate 15 is removed. It will be exposed. In addition, as an etching liquid at this time, it is preferable to select the following with respect to the combination of an etching material and an etching stop material. That is, when the (etching material / etching stop material) combination is (Cu / Al), an acidic etching solution (sulfuric acid, etc.) is used, and when (Al / Cu) is used, an alkaline etching solution is used (Cu / Ni). In the case of (Ni / Cu), sulfuric acid + hydrogen peroxide etching solution, ammonium persulfate etching solution, or alkaline etching solution, and in the case of (Ni / Cu), commercially available Ni stripping solution, (Cu / Pd), (Cu / Ag), (SUS / Pd) or (SUS / Ag), ferric chloride is preferably used, and in either case (Ag / SUS) or (Cu / SUS), ferric nitrate is preferably used. .

  Next, the dry films 16A and 16B are peeled off (FIG. 11), and via holes 17 are formed in the exposed portion 15a of the core substrate 15 by laser processing (FIG. 12). The via hole 17 penetrates the core substrate 11. At this time, the clad material 10 </ b> B opposite to the laser incident side functions as a stopper, so that the third conductive layer 13 of the clad material 10 </ b> B becomes the via hole 17. The bottom part 17a of this is comprised. The diameter of the via hole 17 is not particularly limited, but is preferably set to about 30 to 200 μm.

  Next, a base conductive layer 18 is formed on almost the entire exposed surface including the inner wall of the via hole 17 (FIG. 13). As a method for forming the underlying conductive layer 18, an electroless plating method, a sputtering method, a vapor deposition method, or the like is preferably used. Since the underlying conductive layer 18 serves as an underlying for subsequent electroplating, its thickness is very thin. For example, the underlying conductive layer 18 may be appropriately selected from a range of several hundred angstroms to 3.0 μm.

  Next, the dry films 19A and 19B are attached to the surface of the core substrate 15 (FIG. 14). Thereby, almost the entire surface of the base conductive layer 18 is covered with the dry film 19A, and the surface of the clad material 10B is covered with the dry film 19B. Then, the dry film 19A at the opening of the via hole 17 is removed by exposing and developing the dry film 19A (FIG. 15). The remaining dry film 19A is used as a mask for subsequent electrolytic plating.

  Next, the conductive material 20 is grown in an area not covered with the dry film 19A by electrolytic plating (FIG. 16). That is, the conductive material 20 is selectively formed not on the entire surface of the core substrate 15 but in a region not covered with the dry film 19A. As a result, the via hole 17 is almost completely filled with the conductive material 20. The electrolytic plating is preferably performed so that the inside of the via hole 17 is completely filled with the conductive material 20. The type of the plating solution may be appropriately selected. For example, when the conductive material 20 is copper (Cu), copper sulfate can be used as the plating solution. When a cavity remains in the via hole 17, it is preferable to fill the inside of the via hole 17 with a conductive resin. This is because if the cavities remain, a plating solution or the like remains in the cavities, which causes corrosion of the via holes 17. Although an insulating resin can be used instead of the conductive resin, it is preferable to use a conductive resin in order to ensure electrical connection between the upper and lower layers via the via hole 17.

  Next, after the dry films 19A and 19B are peeled off (FIG. 17), the conductive material 20 is polished parallel to the surface of the core substrate 15 to flatten the entire surface (FIG. 18). At this time, the entire surface can be surely flattened by removing the underlying conductive layer 18 and further polishing the surface of the third conductive layer 13 to a slight extent. For polishing, either chemical polishing or mechanical polishing using a buff may be used, but it is preferable to use these in combination. In particular, if chemical polishing is first performed and then mechanical polishing using a buff is performed, extremely high flatness can be ensured.

  In such a polishing step, if the surface of the third conductive layer 13 is greatly polished, the thickness variation of the third conductive layer 13 may be slightly increased. However, the conductive material 20 is not the entire surface and is selectively used. Therefore, even if the third conductive layer 13 is polished along with the polishing of the conductive material 20, the amount of polishing is very small, and therefore the increase in thickness variation is very small. It is. On the other hand, if the conductive material 20 is formed on the entire surface without using the dry films 19A and 19B, it is necessary to polish the relatively thick (for example, 20 μm) conductive material 20 over the entire surface. The final thickness variation of the third conductive layer 13 becomes considerably large. In the present embodiment, the reason why the mask made of the dry films 19A and 19B is formed in the region where the conductive material 20 should not be formed is that this point is taken into consideration.

  Next, new dry films 21 </ b> A and 21 </ b> B are pasted again on both surfaces of the core substrate 15 (FIG. 19). As a result, the surface of the third conductive layer 13 of the clad material 10A is covered with the dry film 21A, and the surface of the third conductive layer 13 of the clad material 10B is covered with the dry film 21B. Then, the dry films 21A and 21B are exposed and developed to pattern the dry films 21A and 21B, thereby partially exposing the second conductive layers 12 of the cladding materials 10A and 10B (FIG. 20).

  Next, the third conductive layer 13 and the second conductive layer 12 of the cladding materials 10A and 10B are etched using the dry films 21A and 21B as a mask (FIG. 21). Thereby, the third conductive layer 13 and the second conductive layer 12 are patterned, and a relatively thin wiring pattern (second wiring pattern) is formed. At this time, the first conductive layer 11 of the cladding material 10A has already been removed in the first etching step, and the third conductive layer 13 that is an etching material and the first conductive layer 11 that is an etching stop material are formed on the core substrate 15. Since the second conductive layer 12 remains, the third conductive layer 13 and the second conductive layer 12 are completely patterned by etching the clad material using an etching solution having a strong etching power. Note that the same etchant as that used in the second etching step can be used as the etchant at this time.

  Thereafter, the dry films 21A and 21B are peeled off to complete a series of processing on the core substrate 15, and a relatively thick wiring pattern (first wiring pattern) 22 and a relatively thin wiring pattern (second wiring pattern). ) 23 and the processed core substrate 25 in which the electrode patterns 24 above and below the via holes are formed (FIG. 22).

  23 to 26 are plan views showing the shape of the wiring pattern.

  For example, the capacitor element can be configured by setting the shape of the wiring pattern 22 to be an opposing pattern as shown in FIG. 23, and the shape of the wiring pattern 22 (or 23) is a meander-like pattern as shown in FIG. Alternatively, the inductor element can be configured by using a spiral pattern as shown in FIG. 25 or a helical pattern as shown in FIG. In FIG. 25, an electrode pattern 24 on the via hole 17 is formed at the center of the spiral pattern, and is connected to a wiring pattern of another layer via the via hole 17 filled with the conductive material 20. . In FIG. 26, an electrode pattern 24 on the via hole 17 is formed at the end portion of the substantially loop-shaped pattern, and the substantially loop-shaped pattern of another layer is formed via the via hole 17 filled with the conductive material 20. Thus, the entire pattern is configured as a helical pattern. The impedance of these passive elements varies greatly depending on the width and thickness of the wiring pattern. However, if the method according to the present embodiment is used, highly accurate patterning is possible, so the variation in characteristics of these passive elements is greatly reduced. It becomes possible to do.

  As described above, according to the present embodiment, since wiring patterns having different thicknesses can be formed in the same layer, for example, an LC for a high frequency circuit that requires little variation in pattern width and thickness. The normal wiring pattern that requires pattern and impedance matching is composed of the first wiring pattern formed by patterning the conductive layer, and has a high aspect ratio and a relatively large conductor cross-sectional area (low DC resistance). The necessary choke coil L pattern can be formed of a relatively thick second wiring pattern, which can be formed in the same layer, and variations in the optimum pattern shape, width and thickness required for each element. Can be selected arbitrarily. That is, a core substrate having a high degree of design freedom and suitable for high-density mounting can be manufactured.

  In addition, according to the present embodiment, a clad material is patterned to form a relatively thick wiring pattern in advance, which is then pasted on the core substrate, and then the clad material on the core substrate is further patterned to provide a relative thickness. Since a thin wiring pattern is formed, the wiring pattern can be formed only by the subtractive method. Therefore, it suffices to have equipment for processing by the subtractive method, and equipment for processing by the additive method is completely unnecessary.

  Furthermore, according to the present embodiment, when filling the inside of the via hole with a conductive material, the conductive material is selectively formed by forming a mask in a region other than the region where the conductive material is formed. Variations in the thickness of the conductive layer that occur can be suppressed, and when the conductive layer is patterned by a subtractive method to form a wiring pattern, the pattern accuracy can be greatly improved. In addition, since the selectively formed protrusions of the conductive material are mainly polished, warpage is less likely to occur than when the entire surface is polished. Thereby, for example, even when a passive element such as a high-frequency circuit LC is formed on the core substrate, it is possible to suppress variation in impedance. That is, according to the present embodiment, since the thickness variation of the third and second conductive layers to be patterned at this time is suppressed to be extremely small, highly accurate patterning can be performed. Therefore, the width of the relatively thin second wiring pattern formed by these patterning can be set to a desired width.

  Next, a preferred embodiment when the method for manufacturing a multilayer substrate according to the embodiment of the present invention is applied to a “build-up layer” will be described with reference to FIGS. 27 to 45 which are schematic sectional views.

  The method according to the present embodiment may be applied to the buildup layer stacked on the processed core substrate 25 described above, or may be applied to the buildup layer stacked on the core substrate manufactured by another method. In any case, however, it is preferably applied to a build-up layer laminated on a core substrate produced by the method for producing a multilayer substrate according to the present invention. According to this, since the thickness variation is reduced for both the wiring pattern formed on the surface of the core substrate and the wiring pattern formed on the surface of the buildup layer, the pattern accuracy can be improved as a whole. It becomes. Hereinafter, the case where the present invention is applied to the build-up layer laminated on the processed core substrate 25 (see FIG. 22) will be described as an example.

  First, a patterned clad material 10 produced through the steps shown in FIGS. 1 to 5 is prepared, and this is bonded to a thermosetting resin sheet 26 made of B-stage epoxy resin or the like (FIG. 27). At this time, when the laminate 10 is bonded so that the pattern-etched surface of the clad material 10 faces the resin sheet 26 side and the laminated body is pressed, the thermosetting resin is cured, so that the clad material 10 is integrated with the resin sheet 26. Thus, the metal foil 27 with resin is completed (FIG. 28).

  Next, the processed core substrate 25 described above is prepared, and a resin-coated metal foil 27 is laminated on the core substrate 25 (FIG. 29). At this time, if the resin sheet 26 is bonded to the core substrate 25 and the laminated body is hot pressed, the thermosetting resin is cured, so that the metal foil 27 with resin is integrated with the core substrate 25 (see FIG. 30). As a result, a build-up layer (hereinafter referred to as build-up layer 27) is formed on the core substrate 25, and the resin sheet 26 becomes an insulating layer (hereinafter referred to as insulating layer 26) of the build-up layer 27. The first conductive layer 11, the second conductive layer 12, and the third conductive layer 13 are conductive layers on the buildup layer 27.

  Next, the dry film 16 is affixed on the surface of the insulating layer 26 to which the clad material 10 is affixed (FIG. 31). As a result, the surface of the third conductive layer 13 of the clad material 10 is covered with the dry film 16. Then, the dry film 16 is exposed and developed to remove a part thereof, thereby exposing a part 13a of the third conductive layer of the clad material 10 (FIG. 32).

  Next, the cladding material 10 is etched using the dry film 16 as a mask to expose a portion of the insulating layer 26 (FIG. 33). The exposed region 26a becomes an opening of a via hole. At this time, the first conductive layer 11 of the cladding material 10 has already been removed in the first etching process, and the third conductive layer 13 that is an etching material and the second conductive layer that is an etching stop material are formed on the insulating layer 26. Since the conductive layer 12 remains, the third conductive layer 13 and the second conductive layer 12 are completely removed by etching them using an etching solution having a strong etching power, and the surface of the insulating layer 26 is removed. It will be exposed. In addition, as an etching liquid at this time, it is preferable to select the following with respect to the combination of an etching material and an etching stop material. That is, when the (etching material / etching stop material) combination is (Cu / Al), an acidic etching solution (sulfuric acid, etc.) is used, and when (Al / Cu) is used, an alkaline etching solution is used (Cu / Ni). In the case of (Ni / Cu), sulfuric acid + hydrogen peroxide etching solution, ammonium persulfate etching solution, or alkaline etching solution, and in the case of (Ni / Cu), commercially available Ni stripping solution, (Cu / Pd), (Cu / Ag), (SUS / Pd) or (SUS / Ag), ferric chloride is preferably used, and in either case (Ag / SUS) or (Cu / SUS), ferric nitrate is preferably used. .

  Next, the dry film 16 is peeled off (FIG. 34), and the via hole 17 is formed in the exposed portion 26a of the insulating layer 26 by laser processing (FIG. 35). The via hole 17 penetrates the core substrate 11. At this time, the electrode pattern opposite to the laser incident side (here, the electrode pattern on the via hole of the core substrate 25) functions as a stopper. The pattern forms the bottom portion 17 a of the via hole 17. The diameter of the via hole 17 is not particularly limited, but is preferably set to about 30 to 200 μm.

  Next, the base conductive layer 18 is formed on almost the entire exposed surface including the inner wall of the via hole 17 (FIG. 36). As a method for forming the underlying conductive layer 18, an electroless plating method, a sputtering method, a vapor deposition method, or the like is preferably used. Since the underlying conductive layer 18 serves as an underlying for subsequent electroplating, its thickness is very thin. For example, the underlying conductive layer 18 may be appropriately selected from a range of several hundred angstroms to 3.0 μm.

  Next, the dry film 19 is affixed on the surface of the buildup layer 27 (FIG. 37). As a result, almost the entire surface of the underlying conductive layer 18 is covered with the dry film 19. Then, the dry film 19 at the opening of the via hole 17 is removed by exposing and developing the dry film 19 (FIG. 38). The remaining dry film 19 is used as a mask for subsequent electrolytic plating.

  Next, the conductive material 20 is grown in an area not covered with the dry film 19 by electrolytic plating (FIG. 39). That is, the conductive material 20 is selectively formed not in the entire surface of the buildup layer 27 but in a region not covered with the dry film 19. As a result, the via hole 17 is almost completely filled with the conductive material 20. The electrolytic plating is preferably performed so that the inside of the via hole 17 is completely filled with the conductive material 20. The type of the plating solution may be appropriately selected. For example, when the conductive material 20 is copper (Cu), copper sulfate can be used as the plating solution. When a cavity remains in the via hole 17, it is preferable to fill the inside of the via hole 17 with a conductive resin. This is because if the cavities remain, a plating solution or the like remains in the cavities, which causes corrosion of the via holes 17. Although an insulating resin can be used instead of the conductive resin, it is preferable to use a conductive resin in order to ensure electrical connection between the upper and lower layers via the via hole 17.

  Next, after peeling off the dry film 19 (FIG. 40), the conductive material 20 is polished in parallel with the surface of the buildup layer 27 to flatten the entire surface (FIG. 41). At this time, the entire surface can be surely flattened by removing the underlying conductive layer 18 and further polishing the surface of the third conductive layer 13 to a slight extent. For polishing, either chemical polishing or mechanical polishing using a buff may be used, but it is preferable to use these in combination. In particular, if chemical polishing is first performed and then mechanical polishing using a buff is performed, extremely high flatness can be ensured.

  In such a polishing step, if the surface of the third conductive layer 13 is greatly polished, the thickness variation of the third conductive layer 13 may be slightly increased. However, the conductive material 20 is not the entire surface and is selectively used. Therefore, even if the third conductive layer 13 is polished along with the polishing of the conductive material 20, the amount of polishing is very small, and therefore the increase in thickness variation is very small. It is. On the other hand, if the conductive material 20 is formed on the entire surface without using the dry film 19, it is necessary to polish the relatively thick (for example, 20 μm) conductive material 20 over the entire surface. The final thickness variation of the conductive layer 13 becomes considerably large. In the present embodiment, the reason why the mask made of the dry film 19 is formed in the region where the conductive material 20 should not be formed is because of this point.

  Next, a new dry film 21 is attached to the surface of the buildup layer 27 again (FIG. 42). As a result, the surface of the third conductive layer 13 of the clad material 10 is covered with the dry film 21. Then, the dry film 21 is exposed and developed to pattern the dry film 21, and the third conductive layer 13 of the cladding material 10 is partially exposed (FIG. 43).

  Next, the third conductive layer 13 and the second conductive layer 12 of the clad material 10 are etched using the dry film 21 as a mask (FIG. 44). Thereby, the third conductive layer 13 and the second conductive layer 12 are patterned, and a relatively thin wiring pattern (second wiring pattern) is formed. At this time, the first conductive layer 11 of the clad material 10 has already been removed in the first etching step, and the third conductive layer 13 that is an etching material and an etching stop material are formed on the build-up layer 27. Since the second conductive layer 12 remains, the third conductive layer 13 and the second conductive layer 12 are completely patterned by etching them using an etching solution having a strong etching power. Note that the same etchant as that used in the second etching step can be used as the etchant at this time.

  Thereafter, the dry film 21 is peeled off, and a series of processing for the buildup layer 27 is completed, and a relatively thick wiring pattern (first wiring pattern) 22 and a relatively thin wiring pattern (second wiring pattern). 23 and the processed core substrate 25 on which the upper and lower electrode patterns 24 are formed are completed (FIG. 45).

  As described above, according to the present embodiment, since wiring patterns having different thicknesses can be formed in the same layer, for example, an LC for a high frequency circuit that requires little variation in pattern width and thickness. A normal wiring pattern that requires pattern and impedance matching is composed of a relatively thin second wiring pattern that requires a high aspect ratio and a relatively large conductor cross-sectional area (low DC resistance). For the L pattern, it can be composed of a relatively thick first wiring pattern, which can be formed in the same layer, and the optimum pattern shape, width and thickness variation required for each element can be selected arbitrarily it can. That is, a build-up layer having a high degree of design freedom and suitable for high-density mounting can be manufactured.

  Further, according to the present embodiment, after the clad material is patterned to form a relatively thick first wiring pattern in advance, the first wiring pattern is pasted on the thermosetting resin sheet serving as a build-up layer, and then the build is performed. Since the cladding material on the up layer is further patterned to form a relatively thin second wiring pattern, the wiring pattern can be formed only by the subtractive method. Therefore, it suffices to have equipment for processing by the subtractive method, and equipment for processing by the additive method is completely unnecessary.

  Furthermore, according to the present embodiment, when filling the inside of the via hole with a conductive material, the conductive material is selectively formed by forming a mask in a region other than the region where the conductive material is formed. Variations in the thickness of the conductive layer that occur can be suppressed, and when the conductive layer is patterned by a subtractive method to form a wiring pattern, the pattern accuracy can be greatly improved. In addition, since the selectively formed protrusions of the conductive material are mainly polished, warpage is less likely to occur than when the entire surface is polished. Thereby, for example, even when a passive element such as a high-frequency circuit LC is formed on the buildup layer, it is possible to suppress variations in impedance. That is, according to the present embodiment, since the thickness variation of the third and second conductive layers to be patterned at this time is suppressed to be extremely small, highly accurate patterning can be performed. Therefore, the width of the second wiring pattern formed by these patterning can be set to a desired width.

  The present invention is not limited to the embodiments described above, and various modifications are possible within the scope of the invention described in the claims, and these are also included in the scope of the present invention. Needless to say.

  For example, in each of the above embodiments, when filling the inside of the via hole with a conductive material, a conductive material is selectively formed by forming a mask in a region other than the region where the conductive material is formed. It is not essential to form a mask in the region where the conductive material should not be formed.

  Further, in the above embodiment, the clad materials 10A and 10B are attached to both surfaces of the core substrate 15, and thereby the first and second wiring patterns are formed on both surfaces of the core substrate 15, respectively, but only one of them is formed. It may be formed. In this case, a core substrate having a metal foil attached to one side is used as the core substrate, and a clad material is attached to the other side to which the metal foil is not attached. This metal foil plays a role of stopping during laser processing, forms the bottom portion 17a of the via hole during electrolytic plating, and is patterned to be processed into a relatively thin wiring pattern. In addition, it is preferable to use copper foil as metal foil, and it is preferable to set it as about 1-18 micrometers as the thickness (t1). When the conductive layers 112 and 113 are made of a metal foil, an electrolytic copper foil used for a printed wiring board (a copper foil obtained by continuously electrodepositing a solution obtained by dissolving and ionizing copper in a copper sulfate aqueous solution with an electrodeposition roll) If the rolled copper foil is used, the thickness variation can be made extremely small. Moreover, you may adjust the thickness of copper foil by methods, such as a step, as needed.

  Further, in the above embodiment, after patterning one surface of the clad material to form a relatively thick wiring pattern first, the clad material is pasted on the core substrate or the build-up layer. The other side of the clad material was patterned to form a relatively thin wiring pattern. On the contrary, after forming a relatively thin wiring pattern first, a relatively thick wiring pattern was formed. Also good. In this case, the third conductive layer needs to be thinner than the first conductive layer of the clad material to be patterned first.

  Moreover, in the said embodiment, although the electroconductive material is grind | polished after peeling a dry film, you may grind | polish a electroconductive material once before peeling a dry film. That is, the conductive material is polished in the presence of the dry film. At this time, since the dry film itself is hardly polished, the surface of the conductive material substantially coincides with the surface of the dry film. And if a dry film is peeled and the same method is used after that, it will become possible to acquire the effect similar to said each embodiment. When this method is used, the number of polishing steps increases. However, since the conductive material is polished in the presence of the dry film, the thickness of the conductive material is approximately constant and thin in advance. The thickness variation of the conductive layer, the base conductive layer, and the conductive material can be further reduced. In the present invention, the polishing step is not necessarily essential. However, since the thickness of the conductive material is made substantially constant, it is possible to further reduce the thickness variation of the core material, the base conductive layer, and the conductive material to be patterned.

  Further, in the above embodiment, the via hole was formed by laser processing, but is not limited thereto, considering various conditions such as required grinding thickness, grinding width (diameter), grinding rate, For example, an optimal method such as milling, drive last, wet blasting, or drilling may be used.

  In the above embodiment, a patterned dry film is used as a mask for electrolytic plating. Instead of patterning the dry film, an insulating material is selectively formed by a screen printing method and used as a mask. It is also possible.

It is a schematic sectional drawing which shows 1 process (preparation of a clad material) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of a dry film) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (patterning of a dry film) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (pattern etching of a clad material) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (peeling of a dry film) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (preparation of a core board | substrate) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (lamination | stacking of a clad material) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of a dry film) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (patterning of a dry film) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (etching of a clad material) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (peeling of a dry film) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of a via hole) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of a base conductive layer) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of a dry film) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (patterning of a dry film) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of an electroconductive material) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (peeling of a dry film) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (surface grinding | polishing) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of a dry film) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (patterning of a dry film) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (pattern etching of a conductive layer) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (peeling of a dry film) of the manufacturing method by preferable embodiment of this invention, and is a figure which shows the processed core board | substrate. It is a schematic plan view which shows the example which used the wiring pattern as the opposing pattern. It is a schematic plan view showing an example in which the wiring pattern is a meandering pattern. It is a schematic plan view showing an example in which a wiring pattern is a spiral pattern. It is a schematic plan view showing an example in which a wiring pattern is a helical pattern. It is a schematic sectional drawing which shows 1 process (lamination | stacking of a clad material) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (manufacture of metal foil with resin) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (preparation of a processed core board | substrate) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (lamination | stacking of metal foil with resin) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of a dry film) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (patterning of a dry film) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (etching of a clad material) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (peeling of a dry film) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of a via hole) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of a base conductive layer) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of a dry film) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (patterning of a dry film) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of an electroconductive material) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (peeling of a dry film) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (surface grinding | polishing) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of a dry film) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (patterning of a dry film) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (pattern etching of a conductive layer) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (peeling of a dry film) of the manufacturing method by other preferable embodiment of this invention, and is a figure which shows the completed multilayer substrate.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Cladding material 10A, 10B Cladding material 11 Core substrate 11 1st conductive layer 11 2nd conductive layer 13 3rd conductive layer 13a Part of 3rd conductive layer 14 Dry film 14A, 14B Dry film 15 Core substrate 15a Core Part of substrate 16 Dry film 16A, 16B Dry film 17 Via hole 17a Bottom portion of via hole 18 Underlying conductive layer 19 Dry film 19A, 19B Dry film 20 Conductive material 21 Dry film 21A, 21B Dry film 22 First wiring pattern 23 Second Wiring pattern 24 via hole electrode pattern 25 processed core substrate 26 insulating layer (thermosetting resin sheet)
26a Part 27 of insulating layer Build-up layer (metal foil with resin)

Claims (13)

A plurality of laminated insulating layers;
A wiring pattern formed between each insulating layer,
The wiring pattern includes a first wiring pattern having a predetermined thickness and a second wiring pattern thinner than the first wiring pattern,
At least one of the first wiring pattern and the second wiring pattern is configured as a stacked body of a plurality of conductive layers having different etching rates.   The laminate is composed of two conductive layers, and the combination of the two conductive layers includes copper (Cu) and aluminum (Al), aluminum (Al) and copper (Cu), copper (Cu) and nickel (Ni). Nickel (Ni) and copper (Cu), copper (Cu) and palladium (Pd), copper (Cu) and silver (Ag), stainless steel (SUS) and palladium (Pd), stainless steel (SUS) and silver (Ag) The multilayer substrate according to claim 1, wherein the multilayer substrate is any one of silver (Ag) and stainless steel (SUS), copper (Cu) and stainless steel (SUS).   The multilayer board according to claim 1, further comprising a via hole for connecting wiring patterns existing in different layers.   The thickness (t1) of the second wiring pattern is selected within a range of 1 μm to 18 μm, and the ratio (t2 / t1) between the thickness of the second wiring pattern and the thickness of the first wiring pattern is 1. 4. The multilayer substrate according to claim 1, wherein a thickness (t2) of the first wiring pattern is selected so as to be in a range of 5 to 20. 5. 5. The multilayer substrate according to claim 1, wherein at least a part of the first wiring pattern functions as a choke coil.
A first step of forming a first wiring pattern by pattern-etching one surface of a clad material configured as a laminate of a plurality of conductive layers having different etching rates;
A second step of attaching the one surface of the clad material to the surface of an insulating layer constituting a part of the multilayer substrate;
And a third step of forming a second wiring pattern having a thickness different from that of the first wiring pattern by pattern-etching the other surface of the clad material affixed on the insulating layer. A method for producing a multilayer substrate.   The method for manufacturing a multilayer substrate according to claim 6, wherein the plurality of conductive layers have different thicknesses.   The multilayer according to claim 7, wherein a thickness of the conductive layer provided on the one surface side of the clad material is larger than a thickness of the conductive layer provided on the other surface side of the clad material. A method for manufacturing a substrate.   The clad material is configured as a stacked body of conductive layers in which a first conductive layer, a second conductive layer, and a third conductive layer are sequentially stacked, and the first conductive layer and the third conductive layer are Both are made of a predetermined etching material, the second conductive layer is made of a predetermined etching stop material, and the combination of the etching material and the etching stop material is copper (Cu), aluminum (Al), aluminum (Al), and the like. Copper (Cu), copper (Cu) and nickel (Ni), nickel (Ni) and copper (Cu), copper (Cu) and palladium (Pd), copper (Cu) and silver (Ag), stainless steel (SUS) and 7. Palladium (Pd), stainless steel (SUS) and silver (Ag), silver (Ag) and stainless steel (SUS), copper (Cu) and stainless steel (SUS) Method of manufacturing a multilayer substrate according to any one of 8.   The multilayer substrate according to claim 9, wherein the first conductive layer forms the one surface of the clad material, and the third conductive layer forms the other surface of the clad material. Manufacturing method. Forming a via hole; and
The method for manufacturing a multilayer substrate according to claim 6, further comprising a step of selectively forming a conductive material filling the inside of the via hole.   The method for manufacturing a multilayer substrate according to claim 6, wherein the insulating layer is a core substrate.   The method for manufacturing a multilayer substrate according to claim 6, wherein the insulating layer is a build-up layer provided on the core substrate.

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