JP4034771B2 - Multilayer substrate and manufacturing method thereof - Google Patents

Description

  The present invention relates to a multilayer substrate and a manufacturing method thereof, and more particularly, to a multilayer substrate having wiring patterns and via hole electrodes having different thicknesses and a manufacturing method thereof.

  In recent years, the demand for high-density mounting has become increasingly severe. For this reason, a “multilayer board” in which a plurality of insulating layers are stacked is often used as a board for various modules mounted on a printed board.

  The production of the multilayer substrate is performed by forming a wiring pattern or the like on each insulating layer constituting the multilayer substrate and laminating them. Connections between wiring patterns formed in different insulating layers are made through via holes penetrating the insulating layers (see Patent Documents 1 and 2).

  In forming a wiring pattern on each insulating layer, there are generally used two types of methods, a method called “subtractive method” and a method called “additive method”. In the subtractive method, a desired pattern is formed by etching a conductive layer uniformly formed in advance on an insulating layer. In general, pattern formation by the subtractive method uses a copper foil having a constant thickness as the conductive layer, so that it is easy to obtain the accuracy of the thickness. However, it is difficult to control the width with high accuracy, and the thickness of the conductor increases. It has the property that the width accuracy decreases. In the additive method, a portion desired to be drawn with a dry film, resist, or the like is exposed and developed, and after plating is grown along the pattern, the dry film is removed to complete a desired pattern. Pattern formation by the additive method has high accuracy in the width direction because the accuracy in the width direction is determined by the exposed and developed dry film, etc., but the accuracy in the thickness direction depends on the surface variation of the plating, so thickness variation Is relatively large and it is difficult to control the thickness with high accuracy.

As described above, each of the subtractive method and the additive method has advantages and disadvantages. The additive method is selected when the accuracy in the width direction is important, and the subtractive method is selected when the accuracy in the thickness direction is important. In forming the pattern, it is sufficient to employ either of these two methods, and these two methods are not mixedly performed on the same surface.
Japanese Patent No. 2857270 Japanese Patent Laid-Open No. 10-322021

  In recent years, there has been an increasing demand for so-called embedding in which not only wiring patterns but also inductance (L) and capacitance (C) are built in a substrate. The built-in LC is required to:

  First, in L used for a high-frequency circuit, control in the width direction of the pattern is important in controlling impedance. Even if the thickness of the pattern is thin to some extent, the influence on the transmission characteristics is small. On the other hand, L (choke coil) used in a power supply system smoothing circuit or the like preferably has a low DC resistance. Therefore, it is important how large the cross-sectional area of the conductor pattern can be.

  In C used in a high frequency circuit, it is important to reduce the variation in capacitance, and specifically, it is necessary to suppress the variation in capacitance to ± 5% or less. In order to realize this, control in the width direction of the pattern is important, but there is no problem even if the thickness of the pattern is thin to some extent. Furthermore, regarding the wiring pattern, it is important to reduce variations in the width and thickness of the pattern in order to control the impedance.

  Under such conditions, for example, “matching circuit L”, which requires accuracy in the width direction of the pattern, such as a power amplifier substrate, and DC resistance is required to be as low as possible (the thickness of the conductor is required). In the case where “L (choke coil) for power supply circuit” must be configured, if any of the above-described patterning methods is selected, it is possible to form both L in the same layer of the multilayer substrate. There was a problem that I could not.

  In other words, if a desired accuracy is required for the width and thickness of the pattern, the degree of freedom in design is limited due to structural limitations and contradictions that patterns with different thicknesses cannot be formed in the same layer. It was difficult to answer the demand for higher performance.

  Accordingly, an object of the present invention is to provide a multilayer substrate and a method for manufacturing the same, which have a high degree of design freedom and can arbitrarily select an optimum pattern shape and variation required for each element.

  A multilayer substrate according to the present invention includes a plurality of laminated insulating layers and a wiring pattern formed between the insulating layers, wherein the wiring pattern includes a first wiring pattern having a predetermined thickness, and the first wiring pattern. A second wiring pattern that is thicker than the wiring pattern is included, and these are mixed in the same layer. Here, “in the same layer” means the vicinity of the boundary between the insulating layers that are in contact with each other, and when both the first and second wiring patterns exist over the boundary between the insulating layers, the first and second When both of the two wiring patterns are in contact with one surface of the boundary surface, and either one of the first and second wiring patterns is in contact with one surface of the boundary surface and the other is the other surface of the boundary surface It means to include the case of touching the surface. Note that there may be cases where it is difficult to clearly distinguish the boundary between insulating layers due to the lamination of insulating layers made of the same material, such as when a build-up layer is further formed on the build-up layer. Since it is clear that the first and second wiring patterns exist between the insulating layers, in this case, there is a boundary between the insulating layers near the first and second wiring patterns. Can be considered.

  According to the present invention, for example, the high frequency circuit LC pattern and the normal wiring pattern configured as the first wiring pattern and the choke coil L pattern configured as the second wiring pattern are configured in the same layer. The optimum pattern shape and variation required for each element can be arbitrarily selected. That is, a high-performance multilayer substrate suitable for high-density mounting can be realized with a high degree of design freedom.

  In the present invention, the first wiring pattern is formed on a surface of a predetermined insulating layer among the plurality of insulating layers, and the second wiring pattern is at least partially in the predetermined insulating layer. Is preferably embedded.

  According to the present invention, since the first wiring pattern can be configured by the subtractive method and the second wiring pattern can be configured by the additive method, the optimum pattern shape and variation required for each element can be reduced. Can be arbitrarily selected.

  In the present invention, it is preferable to further include a via hole that connects wiring patterns existing in different layers.

  According to the present invention, since the second wiring pattern can be formed at the same time as the via hole, the second wiring pattern can be formed within the range of the normal process without increasing the number of processes.

  In the present invention, the thickness (t1) of the first wiring pattern is selected within a range of 1 μm to 18 μm, and the ratio of the thickness of the first wiring pattern to the thickness of the second wiring pattern (t2 / t1). ) Is preferably selected such that the thickness (t2) of the second wiring pattern is in the range of 1.5-20. Within this range, an optimum circuit pattern can be drawn in a required place without hindering the degree of freedom of design.

  In the present invention, it is preferable that at least a part of the second wiring pattern functions as a choke coil. According to this, for example, a multilayer board for a power amplifier having good characteristics can be realized.

  The multilayer substrate manufacturing method according to the present invention includes a first step of forming a first wiring pattern having a predetermined thickness on a surface of an insulating layer constituting a part of the multilayer substrate, and a pattern forming groove in the insulating layer. And a third step of forming a second wiring pattern thicker than the first wiring pattern by filling the inside of the pattern forming groove with a conductive material. It is characterized by.

  According to the present invention, patterns having different thicknesses can be formed in the same layer. For example, a thin pattern formed by patterning a conductive layer is an LC pattern for a high frequency circuit and a normal wiring pattern. Thick patterns due to the grooves for forming can be selected as L patterns for choke coils, so that a multilayer board for power amplifiers with good characteristics can be realized, and the optimum pattern shape and variation required for each element can be selected arbitrarily. it can. That is, a high-performance multilayer substrate suitable for high-density mounting with a high degree of design freedom can be manufactured.

  In the present invention, the first step includes a step of patterning a conductive layer formed on at least one surface of the insulating layer, and the third step includes a step of forming a base conductive layer, and a conductive property. Preferably, the method includes a step of forming a mask in a region where the material should not be formed, and a step of growing the conductive material by electrolytic plating.

  According to the present invention, the above-described thin pattern can be formed by the additive method, and the thick pattern can be formed by the subtractive method. Therefore, the optimum pattern shape and variation required for each element can be arbitrarily set. A multilayer substrate suitable for high-density mounting can be manufactured. Here, the step of forming the mask is preferably performed by patterning the photosensitive material by exposure after forming the photosensitive material on substantially the entire surface, or selectively processing the insulating material by screen printing. It is preferable to carry out by forming.

  In the present invention, it is preferable that the second step includes a step of forming a via hole, and the third step includes a step of filling the inside of the via hole with a conductive material.

  According to the present invention, since the second wiring pattern can be formed at the same time as the via hole forming step, the wiring pattern by the pattern forming groove can be formed within the range of the normal step without increasing the number of steps. .

  In the present invention, it is preferable that in the second step, the via hole is formed so that a conductive layer included in another insulating layer forms a bottom portion of the via hole.

  According to the present invention, it is possible to simplify the process by forming the conductive material using a plating solution capable of almost completely filling the hole having the bottom.

  In the present invention, it is preferable that the third step is a step of selectively forming a conductive material filling the via hole and the pattern forming groove.

  According to the present invention, since the conductive material that selectively fills at least a part of the via hole and the pattern forming groove is selectively formed, it is possible to suppress variation in the thickness of the insulating layer caused by polishing. .

  In the present invention, the insulating layer may be a core substrate or a build-up layer provided on the core substrate. Furthermore, both of them may be used. When the present invention is applied to both the core substrate and the buildup layer, the thickness variation is reduced for both the wiring pattern formed on the surface of the core substrate and the wiring pattern formed on the surface of the buildup layer. Therefore, the overall pattern accuracy can be improved.

  As described above, according to the present invention, the variation in the width and thickness of the pattern is small, and the high-frequency circuit LC pattern that requires the pattern thickness accuracy with respect to the insulating layer and the normal wiring pattern that requires impedance matching (the first wiring pattern) For the wiring pattern), the pattern thickness can be made relatively thin by pattern etching of the conductive layer having a constant thickness by the subtractive method. For the L pattern for the choke coil (second wiring pattern), The pattern forming groove is formed by drilling in the same process as the via hole formation, and then the conductive material is embedded in the pattern forming groove simultaneously with the via hole, so that the aspect ratio is high and the conductor sectional area is increased. A relatively large pattern (low DC resistance) can be obtained. In other words, according to the present embodiment, the optimum pattern shape and variation required for each element can be arbitrarily selected, so that a high-performance multilayer substrate having a high degree of design freedom and suitable for high-density mounting can be realized. it can.

  In addition, according to the present invention, since the thickness variation of the conductive material caused by polishing is suppressed, when forming a wiring pattern by a patterning method such as a subtractive method, the pattern accuracy can be greatly improved. It becomes possible. Thereby, for example, even when a passive element such as a capacitor or an inductor is built in the multilayer substrate, it is possible to suppress variations in impedance.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  The method for manufacturing a multilayer substrate according to the present embodiment can be applied to both the “core substrate” constituting the multilayer substrate and the “build-up layer” provided on the core substrate. First, the case where the method for manufacturing a multilayer substrate according to the present embodiment is applied to a “core substrate” will be described with reference to FIGS.

  First, the core substrate 10 is prepared (FIG. 1). The core substrate 10 before processing is composed of an insulating layer 11 and conductive layers 12 and 13 formed on both surfaces of the insulating layer 11, respectively. The insulating layer 11 plays the role of ensuring the overall mechanical strength in the production of the multilayer substrate, and is not particularly limited, but the material includes glass cloth, Kevlar, resin cloth such as liquid crystal polymer, fluorine It is preferable to use a material impregnated with a thermosetting resin, a thermoplastic resin, or the like for the core material made of a porous sheet of resin, and the thickness is preferably set to about 20 μm to 200 μm. Further, a sheet material without a core material such as LCP, PPS, PES, PEEK, and PI may be used as the insulating layer 11 for the purpose of uniformizing laser processing conditions. The conductive layers 12 and 13 are preferably composed of metal foil, particularly copper foil, and the thickness (t1) is preferably set to about 1 to 18 μm. When the conductive layers 12 and 13 are made of a metal foil, an electrolytic copper foil used for a printed wiring board (a copper foil obtained by continuously electrodepositing a solution obtained by dissolving and ionizing copper in a copper sulfate aqueous solution with an electrodeposition roll) If the rolled copper foil is used, the thickness variation can be made extremely small. Moreover, you may adjust the thickness of copper foil by methods, such as a step, as needed.

  Next, dry films 14 and 15 made of a photosensitive material are attached to both surfaces of the core substrate 10 (FIG. 2). As a result, almost the entire surfaces of the conductive layers 12 and 13 are covered with the dry films 14 and 15. Then, the dry film 14 is exposed and developed to remove a part of the dry film 14 and expose the parts 12a and 12b of the conductive layer 12 (FIG. 3).

  Next, the conductive layer 12 is etched using the dry film 14 as a mask to partially expose the insulating layer 11 (FIG. 4). A part 11a of the exposed region of the insulating layer becomes an opening of a via hole, and the other part 11b becomes an opening of a pattern forming groove.

  Next, the dry films 14 and 15 are peeled off (FIG. 5), and a via hole 16 is formed in a part 11a of the exposed region of the insulating layer 11 by laser processing, and another part 11b of the exposed region of the insulating layer 11 is formed. A pattern forming groove 17 is formed on the substrate (FIG. 6). In the laser processing, the via hole 16 and the pattern forming groove 17 are separately formed by setting the laser power and the irradiation time to an optimum level for each place. The via hole 16 penetrates the insulating layer 11. At this time, the conductive layer 13 functions as a stopper, so that the conductive layer 13 constitutes the bottom portion 16 a of the via hole 16. The diameter of the via hole 16 is not particularly limited, but is preferably set to about 30 to 200 μm. On the other hand, the pattern forming groove 17 is merely digging the insulating layer 11 to a predetermined depth and does not penetrate the insulating layer 11 unlike the via hole 16. The depth of the pattern forming groove 17 is the ratio (t2 / t1) between the thickness (t1) of the conductive layers 12 and 13 and the thickness (t2) of the wiring pattern finally formed using the pattern forming groove 17 Is preferably set to be in the range of 1.5-20.

  Next, a base conductive layer 18 is formed on almost the entire exposed surface including the inner walls of the via hole 16 and the pattern forming groove 17 (FIG. 7). As a method for forming the underlying conductive layer 18, an electroless plating method, a sputtering method, a vapor deposition method, or the like is preferably used. Since the underlying conductive layer 18 serves as an underlying for subsequent electroplating, its thickness is very thin. For example, the underlying conductive layer 18 may be appropriately selected from a range of several hundred angstroms to 3.0 μm.

  Next, a dry film 19 made of a photosensitive material is attached to the surface of the core substrate 10 (FIG. 8). As a result, almost the entire surface of the underlying conductive layer 18 is covered with the dry film 27. Then, by exposing and developing the dry film 19, the dry film 19 at the opening of the via hole 16 and the pattern forming groove 17 is removed (FIG. 9). The remaining dry film 19 is used as a mask for subsequent electrolytic plating.

  Next, the conductive material 20 is grown in an area not covered with the dry film 19 by electrolytic plating (FIG. 10). That is, the conductive material 20 is selectively formed not on the entire surface of the core substrate 10 but in a region not covered with the dry film 19. As a result, the inside of the via hole 16 is almost completely filled with the conductive material 20. Further, the inside of the pattern forming groove 17 is also filled with the conductive material 20.

  The electrolytic plating is preferably performed so that the insides of the via hole 16 and the pattern forming groove 17 are completely filled with the conductive material. The type of the plating solution may be appropriately selected. For example, when the conductive material is copper (Cu), copper sulfate can be used as the plating solution. When a cavity remains inside the via hole 16, it is preferable to fill the inside of the via hole 16 with a conductive resin. This is because if the cavities remain, a plating solution or the like remains in the cavities, which causes corrosion of the via holes. Although an insulating resin can be used in place of the conductive resin, it is preferable to use a conductive resin in order to ensure electrical connection between the upper and lower layers via the via hole 16.

  Next, after peeling off the dry film 19 (FIG. 11), the conductive material 20 is polished parallel to the surface of the core substrate 10 to flatten the entire surface (FIG. 12). At this time, polishing is performed to such an extent that the underlying conductive layer 18 is removed and the surface of the conductive layer 12 is slightly polished, so that the entire surface can be surely flattened. For polishing, either chemical polishing or mechanical polishing using a buff may be used, but it is preferable to use these in combination. In particular, if chemical polishing is first performed and then mechanical polishing using a buff is performed, extremely high flatness can be ensured.

  In such a polishing process, if the surface of the conductive layer 12 is greatly polished, the thickness variation of the conductive layer 12 may be slightly increased, but the conductive material 20 is selectively formed instead of the entire surface. Therefore, even if the conductive layer 12 is polished along with the polishing of the conductive material 20, the amount of polishing is very small, and therefore the increase in thickness variation is very small. On the other hand, if the conductive material 20 is formed on the entire surface without using the dry film 19, it is necessary to polish the relatively thick (for example, 20 μm) conductive material 20 over the entire surface. The final thickness variation of 12 becomes considerably large. In the present embodiment, the reason why the mask made of the dry film 19 is formed in the region where the conductive material 20 should not be formed is because of this point. However, in the present invention, it is not essential to form a mask in a region where the conductive material 20 should not be formed.

  Next, the dry films 21 and 22 are respectively attached to both surfaces of the core substrate (FIG. 13), and the dry films 21 and 22 are patterned by exposing and developing the dry films 21 and 22, and the conductive layers 12 and 13 are partially formed. Are exposed (FIG. 14). Then, the exposed portions of the conductive layers 12 and 13 are removed by etching (FIG. 15). Since the conductive layers 12 and 13 to be patterned at this time have very small variations in thickness, highly accurate patterning can be performed. The remaining conductive layers 12 and 13 become part of the normal wiring pattern (first wiring pattern) 23 and the electrode pattern 25 on the via hole. Finally, by peeling off the dry films 21 and 22, a series of processing on the core substrate 10 is completed, and the first wiring pattern 23, the second wiring pattern 24, and the electrode pattern 25 on the via hole are formed. The core substrate 26 is completed (FIG. 16).

  17 to 19 are plan views showing the shape of the wiring pattern.

  For example, a capacitor element can be configured by setting the shape of the wiring pattern 23 to a facing pattern as shown in FIG. 17, and the shape of the wiring pattern 23 (or 24) is a meander-like pattern as shown in FIG. Alternatively, the inductor element can be configured by using a spiral pattern as shown in FIG. 19 or a helical pattern as shown in FIG. In FIG. 19, an electrode pattern 25 on the via hole 16 is formed at the center of the spiral pattern and is connected to a wiring pattern of another layer via the via hole 16 filled with the conductive material 20. . In FIG. 20, an electrode pattern 25 on the via hole 16 is formed at the end portion of the substantially loop-shaped pattern, and the substantially loop-shaped pattern of another layer is formed via the via hole 16 filled with the conductive material 20. Thus, the entire pattern is configured as a helical pattern. The impedance of these passive elements varies greatly depending on the width and thickness of the wiring pattern. However, if the method according to the present embodiment is used, highly accurate patterning is possible, so the variation in characteristics of these passive elements is greatly reduced. It becomes possible to do.

  As described above, according to the present embodiment, since wiring patterns having different thicknesses can be formed in the same layer, for example, an LC for a high frequency circuit that requires little variation in pattern width and thickness. The normal wiring pattern that requires pattern and impedance matching is composed of the first wiring pattern formed by patterning the conductive layer, and has a high aspect ratio and a relatively large conductor cross-sectional area (low DC resistance). The required L pattern for the choke coil is constituted by the second wiring pattern by the pattern forming groove, which can be formed in the same layer, and has the optimum pattern shape, width and thickness required for each element. Variations can be arbitrarily selected. That is, a core substrate having a high degree of design freedom and suitable for high-density mounting can be manufactured.

  Furthermore, according to the present embodiment, the pattern formation groove is formed in the same process as the formation of the via hole by laser processing, and then the pattern formation groove is made conductive in the process of filling the inside of the via hole with a conductive material. Since the second wiring pattern is formed by being filled with the material, the second wiring pattern can be formed within the range of a normal process without increasing the number of processes.

  Furthermore, according to the present embodiment, when the inside of the via hole or the pattern forming groove is filled with the conductive material, the conductive material is selectively formed by forming a mask in a region other than the region where the conductive material is formed. Therefore, variation in the thickness of the conductive layer caused by polishing can be suppressed, and when the wiring pattern is formed by patterning the conductive layer, the pattern accuracy can be greatly improved. Thereby, for example, even when a passive element such as a high frequency LC is formed on the core substrate, it is possible to suppress variation in impedance.

  Next, the case where the manufacturing method of the multilayer substrate according to the present embodiment is applied to the “build-up layer” will be described with reference to FIGS.

  The method according to the present embodiment may be applied to a buildup layer that is stacked on the processed core substrate 26 manufactured by the method described with reference to FIGS. 1 to 16, and is manufactured by another method that will be described later. However, in any case, it is preferable to apply to a buildup layer laminated on a core substrate manufactured by the method for producing a multilayer substrate according to the present invention. . According to this, since the thickness variation is reduced for both the wiring pattern formed on the surface of the core substrate and the wiring pattern formed on the surface of the buildup layer, the pattern accuracy can be improved as a whole. It becomes. Hereinafter, the case where the present invention is applied to the build-up layer laminated on the processed core substrate 26 (see FIG. 16) will be described as an example.

  First, a processed core substrate 26 is prepared, and a buildup layer is laminated on the core substrate 26 (FIG. 21). The build-up layer 30 before processing is made of a sheet (metal foil with resin) in which a metal foil 32 is provided on a thermosetting resin 31 made of a B-stage epoxy resin or the like. When this sheet is bonded so that the thermosetting resin 31 side faces the core substrate 26 and this laminate is hot pressed, the thermosetting resin 31 is cured, so that the buildup layer 30 is integrated with the core substrate 26. (FIG. 22). Thereby, the thermosetting resin 31 becomes an insulating layer of the buildup layer, and the metal foil 32 becomes a conductive layer.

  Next, the dry film 33 comprised with the photosensitive material is affixed on the surface of the buildup layer 30 (FIG. 23). As a result, almost the entire surface of the conductive layer 32 is covered with the dry film 33. Then, the dry film 33 is exposed and developed to remove a part of the dry film 33 and expose the parts 32a and 32b of the conductive layer 12 (FIG. 24).

  Next, the conductive layer 32 is etched using the dry film 33 as a mask to partially expose the insulating layer 31 (FIG. 25). A part 31a of the exposed region of the insulating layer becomes an opening of a via hole, and the other part 31b becomes an opening of a pattern forming groove.

  Next, the dry film 33 is peeled off (FIG. 26), and a via hole 34 is formed in a part 31a of the exposed region of the insulating layer 31 by laser processing, and a pattern is formed in the other part 31b of the exposed region of the insulating layer 31. A forming groove 35 is formed (FIG. 27). In the laser processing, the via hole 34 and the pattern forming groove 35 are separately formed by setting the laser power and the irradiation time to an optimum level for each place. The via hole 34 penetrates the insulating layer 31. At this time, the conductive layer (here, the electrode pattern 23) on the core substrate 26 functions as a stopper, so that the conductive layer forms the bottom 34 a of the via hole 34. It will be. The diameter of the via hole 34 is not particularly limited, but is preferably set to about 30 to 200 μm. On the other hand, the pattern forming groove 35 is merely in which the insulating layer 31 is dug to a predetermined depth and does not penetrate the insulating layer 31 like the via hole 34. The depth of the pattern forming groove 35 is the ratio (t2 / t1) between the thickness (t1) of the conductive layer 32 and the thickness (t2) of the wiring pattern finally formed using the pattern forming groove 35. It is preferably set to be in the range of 1.5 to 20.

  Next, a base conductive layer 36 is formed on almost the entire exposed surface including the inner walls of the via hole 34 and the pattern forming groove 35 (FIG. 28). As a method for forming the base conductive layer 36, it is preferable to use an electroless plating method, a sputtering method, a vapor deposition method, or the like. Since the base conductive layer 36 serves as a base for subsequent electrolytic plating, the thickness of the base conductive layer 36 is very thin. For example, the base conductive layer 36 may be appropriately selected from a range of several hundred angstroms to 3.0 μm.

  Next, the dry film 37 comprised with the photosensitive material is affixed on the surface of the buildup layer 30 (FIG. 29). As a result, almost the entire surface of the base conductive layer 36 is covered with the dry film 37. Then, by exposing and developing the dry film 37, the dry film 37 in the openings of the via hole 34 and the pattern forming groove 35 is removed (FIG. 30). The remaining dry film 37 is used as a mask for subsequent electrolytic plating.

  Next, a conductive material 38 is grown in an area not covered with the dry film 37 by electrolytic plating (FIG. 31). That is, the conductive material 38 is selectively formed not on the entire surface of the buildup layer but in a region not covered with the dry film 37. As a result, the inside of the via hole 34 is almost completely filled with the conductive material 38. Further, the inside of the pattern forming groove 35 is also filled with a conductive material.

  Next, after the dry film 37 is peeled off (FIG. 32), the conductive material 38 is polished parallel to the surface of the buildup layer 30 to flatten the entire surface (FIG. 33). Here, as in the above embodiment, the entire surface can be surely flattened by removing the underlying conductive layer 36 and polishing the surface of the conductive layer 12 to a slight extent. Also in this case, it is possible to ensure extremely high flatness by first performing chemical polishing and then performing mechanical polishing using a buff.

  In such a polishing step, if the surface of the conductive layer 32 is greatly polished, the thickness variation of the conductive layer 32 may be slightly increased, but the conductive material 38 is selectively formed instead of the entire surface. Therefore, even if the conductive layer 32 is polished along with the polishing of the conductive material 38, the amount of polishing is very small, and therefore the variation in thickness is very small. However, in the present invention, it is not essential to form a mask in a region where the conductive material 38 should not be formed.

  Next, the dry film 39 is attached to the surface of the buildup layer (FIG. 34), the dry film 39 is exposed and developed to pattern the dry film 39, and the conductive layer 32 is partially exposed (FIG. 35). . Then, the exposed portion of the conductive layer 32 is removed by etching (FIG. 36). Since the conductive layer 32 to be patterned at this time has a very small variation in thickness, highly precise patterning can be performed. The remaining conductive layer 32 becomes a part of the normal wiring pattern (first wiring pattern) 40 and the electrode pattern 42 on the via hole. Finally, by peeling off the dry film 39, a series of processing for the build-up layer 30 is completed, and the multilayer substrate 43 in which the first wiring pattern 40, the second wiring pattern 41, and the electrode pattern 42 on the via hole are formed. Is completed (FIG. 37).

  As described above, according to the present embodiment, since wiring patterns having different thicknesses can be formed in the same layer, for example, an LC for a high frequency circuit that requires little variation in pattern width and thickness. The normal wiring pattern that requires pattern and impedance matching is composed of the first wiring pattern formed by patterning the conductive layer, and has a high aspect ratio and a relatively large conductor cross-sectional area (low DC resistance). The required L pattern for the choke coil is constituted by the second wiring pattern by the pattern forming groove, which can be formed in the same layer, and has the optimum pattern shape, width and thickness required for each element. Variations can be arbitrarily selected. That is, a build-up layer having a high degree of design freedom and suitable for high-density mounting can be manufactured.

  Furthermore, according to the present embodiment, the pattern formation groove is formed in the same process as the formation of the via hole by laser processing, and then the pattern formation groove is made conductive in the process of filling the inside of the via hole with a conductive material. Since the second wiring pattern is formed by being filled with the material, the second wiring pattern can be formed within the range of a normal process without increasing the number of processes.

  Furthermore, according to the present embodiment, when the inside of the via hole or the pattern forming groove is filled with the conductive material, the conductive material is selectively formed by forming a mask in a region other than the region where the conductive material is formed. Therefore, variation in the thickness of the conductive layer caused by polishing can be suppressed, and when the wiring pattern is formed by patterning the conductive layer, the pattern accuracy can be greatly improved. Thereby, for example, even when a passive element such as a high frequency LC is formed on the buildup layer, it is possible to suppress variation in impedance.

  Next, another preferred embodiment of the method for producing a multilayer substrate according to the present invention will be described in detail.

  The multilayer substrate manufacturing method according to the present embodiment can also be applied to both the “core substrate” constituting the multilayer substrate and the “build-up layer” provided on the core substrate. Hereinafter, the case where the manufacturing method of the multilayer substrate according to the present embodiment is applied to the “build-up layer” will be described with reference to FIGS. 38 to 51 which are schematic sectional views. Since the basic process for the core substrate and the build-up layer is the same as in the above-described embodiment, only the “build-up layer” will be described in this embodiment, and the description of the core substrate will be omitted. . The same elements as those in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  The method according to the present embodiment may be applied to a buildup layer that is laminated on the processed core substrate 26 manufactured by the method described with reference to FIGS. 1 to 16, and is manufactured by the method according to the present embodiment. However, in any case, it is preferable to apply to a buildup layer laminated on a core substrate manufactured by the method for producing a multilayer substrate according to the present invention. . According to this, since the thickness variation is reduced for both the wiring pattern formed on the surface of the core substrate and the wiring pattern formed on the surface of the buildup layer, the pattern accuracy can be improved as a whole. It becomes. Hereinafter, the case where the present invention is applied to the build-up layer laminated on the processed core substrate 26 (see FIG. 16) will be described as an example.

  First, the processed core substrate 26 is prepared, and the buildup layer 30 is laminated on the core substrate 26 (FIG. 38). The build-up layer 30 before processing is made of a sheet (metal foil with resin) in which a metal foil 32 is provided on a thermosetting resin 31 made of a B-stage epoxy resin or the like. When this sheet is bonded so that the thermosetting resin 31 side faces the core substrate 26 and this laminate is hot pressed, the thermosetting resin 31 is cured, so that the buildup layer 30 is integrated with the core substrate 26. (FIG. 39). Thereby, the thermosetting resin 31 becomes an insulating layer of the buildup layer, and the metal foil 32 becomes a conductive layer.

  Next, a dry film 33 made of a photosensitive material is attached to the surface of the buildup layer 30 (FIG. 40). As a result, almost the entire surface of the conductive layer 32 is covered with the dry film 33. Then, by exposing and developing the dry film 33, the dry film 33 is patterned and the conductive layer 32 is partially exposed (FIG. 41).

  Next, the conductive layer 32 is etched using the dry film 33 as a mask to partially expose the insulating layer 31 (FIG. 42). A part 31a of the exposed region of the insulating layer becomes an opening of a via hole, and the other part 31b becomes an opening of a pattern forming groove. On the other hand, the remaining conductive layer 32 mainly becomes a normal wiring pattern (first wiring pattern) having a predetermined thickness. That is, in the present embodiment, the pattern etching for forming the first wiring pattern and the etching for securing the formation region of the via hole and the pattern forming groove are performed in the same process. It is different from the form. Since the conductive layer 32 to be patterned at this time has a very small thickness variation, it is possible to perform highly accurate patterning. Therefore, the width of the wiring pattern can be set to a desired width.

  Next, the dry film 33 is peeled off (FIG. 43), and a via hole 34 is formed in a part 31a of the exposed region of the insulating layer 31 by laser processing, and a pattern is formed in the other part 31b of the exposed region of the insulating layer 11. A forming groove 35 is formed (FIG. 44).

  Next, a base conductive layer 36 is formed on almost the entire exposed surface including the inner walls of the via hole 34 and the pattern forming groove 35 (FIG. 45). As a method for forming the base conductive layer 36, it is preferable to use an electroless plating method, a sputtering method, a vapor deposition method, or the like.

  Next, the dry film 37 comprised with the photosensitive material is affixed on the surface of the buildup layer 30 (FIG. 46). As a result, almost the entire surface of the base conductive layer 36 is covered with the dry film 37. Then, by exposing and developing the dry film 37, the dry film 37 in the openings of the via hole 34 and the pattern forming groove 35 is removed (FIG. 47). The remaining dry film 37 is used as a mask for subsequent electrolytic plating.

  Next, a conductive material 38 is grown in an area not covered with the dry film 37 by electrolytic plating (FIG. 48). As a result, the inside of the via hole 34 is almost completely filled with the conductive material 38. Further, the inside of the pattern forming groove 35 is also filled with a conductive material.

  Next, after peeling off the dry film 37 (FIG. 49), the conductive material 38 is polished parallel to the surface of the buildup layer 30 to flatten the entire surface (FIG. 50). As a result, the second wiring pattern 41 thicker than the first wiring pattern 39 and a part of the electrode pattern 42 on the via hole are formed. Then, by removing the unnecessary base conductive layer 36 where no wiring pattern or the like is formed using an etchant such as an acid (soft etching), a series of processing on the build-up layer is completed, and the first process is completed. A multilayer substrate 43 on which the wiring pattern 40, the second wiring pattern 41, and the electrode pattern 42 on the via hole are formed is completed (FIG. 51).

  As described above, according to the present embodiment, since wiring patterns having different thicknesses can be formed in the same layer, for example, an LC for a high frequency circuit that requires little variation in pattern width and thickness. The normal wiring pattern that requires pattern and impedance matching is composed of the first wiring pattern formed by patterning the conductive layer, and has a high aspect ratio and a relatively large conductor cross-sectional area (low DC resistance). The required L pattern for the choke coil is constituted by the second wiring pattern by the pattern forming groove, which can be formed in the same layer, and has the optimum pattern shape, width and thickness required for each element. Variations can be arbitrarily selected. That is, a build-up layer having a high degree of design freedom and suitable for high-density mounting can be manufactured.

  Furthermore, according to the present embodiment, the pattern formation groove is formed in the same process as the formation of the via hole by laser processing, and then the pattern formation groove is made conductive in the process of filling the inside of the via hole with a conductive material. Since the second wiring pattern is formed by being filled with the material, the second wiring pattern can be formed within the range of a normal process without increasing the number of processes.

  Furthermore, according to the present embodiment, pattern etching for forming the first wiring pattern and etching for securing the formation region of the via hole and the pattern forming groove are performed in one etching process on the conductive layer. Since the steps are performed together, the number of steps can be reduced as compared with the above-described embodiment.

  The present invention is not limited to the embodiments described above, and various modifications are possible within the scope of the invention described in the claims, and these are also included in the scope of the present invention. Needless to say.

  For example, in each of the above embodiments, the via hole and the pattern forming groove are formed by laser processing. However, the present invention is not limited to this, and various grinding thicknesses, grinding widths (diameters), grinding rates, and the like are required. In consideration of the conditions, for example, an optimum method such as milling, drive last, wet blast, drill, etc. may be taken.

  Further, in each of the above embodiments, a patterned dry film is used as a mask for electrolytic plating. Instead of patterning the dry film, an insulating material is selectively formed by screen printing, and this is used as a mask. Can also be used.

  Moreover, in 1st Embodiment mentioned above, although the electroconductive material is grind | polished after peeling a dry film, before peeling a dry film, an electroconductive material was once grind | polished, and also the dry film was peeled off. Thereafter, if polishing is performed again, the number of times of polishing increases, but the thickness of the conductive material can be made almost constant and thin, so that more accurate patterning can be performed. Further, although the conductive layer is not polished in each of the above embodiments, the conductive layer may be polished when it is necessary to make the thickness of the conductive layer uniform.

  In each of the above embodiments, the wiring pattern (second wiring pattern) by the pattern forming groove is formed by an additive method such as electrolytic plating, and the other wiring pattern (first wiring pattern) is etched. Although the subtractive method such as the method is used, both wiring patterns may be formed by the additive method. That is, in the multilayer substrate manufacturing method according to the present invention, at least the first step of forming the pattern forming groove in the insulating layer constituting a part of the multilayer substrate, and the inside of the pattern forming groove is filled with the conductive material. What is necessary is just to provide the 2nd process and the 3rd process of forming a wiring pattern in the surface of an insulating layer. In this case, the thickness accuracy of the first wiring pattern is somewhat deteriorated, but if the thickness is set sufficiently thin, it is possible to suppress the deterioration of the thickness accuracy.

  In the first embodiment described above, first, the second wiring pattern is formed by the pattern forming groove together with the via hole, and then the first wiring pattern is formed. In the second embodiment, First, the first wiring pattern is formed by etching, and then the second wiring pattern is formed by the pattern forming groove together with the via hole. Therefore, in the present invention, the order of forming these wiring patterns is Does not matter. That is, during the manufacturing process of the multilayer substrate, a step of forming a first wiring pattern having a predetermined thickness on the surface of the insulating layer constituting a part of the multilayer substrate, and a pattern forming groove is formed in the insulating layer Thereafter, the step of filling the inside of the pattern forming groove with a conductive material to form a second wiring pattern thicker than the first wiring pattern may be included regardless of the order.

It is a schematic sectional drawing which shows 1 process (preparation of a core board | substrate) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of a dry film) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (patterning of a dry film) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (etching of a conductive layer) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (peeling of a dry film) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows one process (formation of a via hole and a pattern formation groove | channel) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of a base conductive layer) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of a dry film) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (patterning of a dry film) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of an electroconductive material) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (peeling of a dry film) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (surface grinding | polishing) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of a dry film) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (patterning of a dry film) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (etching of a conductive layer) of the manufacturing method by preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (peeling of a dry film) of the manufacturing method by preferable embodiment of this invention, and is a figure which shows the processed core board | substrate. It is a schematic plan view which shows the example which used the wiring pattern as the opposing pattern. It is a schematic plan view showing an example in which the wiring pattern is a meandering pattern. It is a schematic plan view showing an example in which a wiring pattern is a spiral pattern. It is a schematic plan view showing an example in which a wiring pattern is a helical pattern. It is a schematic sectional drawing which shows 1 process (press with the metal foil with resin) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (preparation of a multilayer board | substrate) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of a dry film) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (patterning of a dry film) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (etching of a conductive layer) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (peeling of a dry film) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of a via hole and a pattern formation groove | channel) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of a base conductive layer) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of a dry film) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (patterning of a dry film) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of an electroconductive material) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (peeling of a dry film) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (surface grinding | polishing) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of a dry film) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (patterning of a dry film) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (etching of a conductive layer) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (peeling of a dry film) of the manufacturing method by other preferable embodiment of this invention, and is a figure which shows the completed multilayer substrate. It is a schematic sectional drawing which shows 1 process (press with the metal foil with resin) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (preparation of a multilayer board | substrate) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of a dry film) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (patterning of a dry film) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (etching of a conductive layer) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (peeling of a dry film) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of a via hole and a pattern formation groove | channel) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of a base conductive layer) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of a dry film) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (patterning of a dry film) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (formation of an electroconductive material) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (peeling of a dry film) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (surface grinding | polishing) of the manufacturing method by other preferable embodiment of this invention. It is a schematic sectional drawing which shows 1 process (soft etching) of the manufacturing method by other preferable embodiment of this invention, and is a figure which shows the completed multilayer substrate.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Core substrate 11 Insulating layer 11a, 11b Part of insulating layer 12 Conductive layer 12a, 12b Part of conductive layer 13 Conductive layer 14 Dry film 15 Dry film 16 Via hole 16a Bottom of via hole 17 Pattern formation groove 18 Underlying conductive layer 19 Dry film 20 conductive material 21 dry film 22 dry film 23 via hole electrode pattern 24 wiring pattern by pattern forming groove 25 other wiring pattern 26 processed core substrate 30 buildup layer 31 insulating layer (thermosetting resin)
31a, 31b Part of insulating layer 32 Conductive layer (metal foil)
32a, 32b Part of conductive layer 33 Dry film 34 Via hole 34a Bottom of via hole 35 Pattern forming groove 36 Underlying conductive layer 37 Dry film 38 Conductive material 39 Dry film 40 Via hole electrode pattern 41 Wiring pattern by pattern forming groove 42 Others Wiring pattern 43 Multi-layer substrate

Claims (8)

A first step of forming a first wiring pattern having a predetermined thickness on a surface of an insulating layer constituting a part of the multilayer substrate;
A second step of forming a pattern forming groove in the insulating layer;
And a third step of forming a second wiring pattern thicker than the first wiring pattern by filling the inside of the pattern forming groove with a conductive material,
The first step includes a step of patterning a conductive layer formed on at least one surface of the insulating layer,
The third step includes a step of forming a base conductive layer, a step of forming a mask in a region where the conductive material should not be formed, and a step of growing the conductive material by an electrolytic plating method. A method for producing a multilayer substrate. 2. The method of manufacturing a multilayer substrate according to claim 1 , wherein the step of forming the mask is performed by patterning the photosensitive material by exposure after forming the photosensitive material on substantially the entire surface. The method for manufacturing a multilayer substrate according to claim 1 , wherein the step of forming the mask is performed by selectively forming an insulating material by a screen printing method. The second step includes a step of forming a via hole,
4. The method of manufacturing a multilayer substrate according to claim 1, wherein the third step includes a step of filling the inside of the via hole with a conductive material. 5. 5. The method of manufacturing a multilayer substrate according to claim 4 , wherein in the second step, the via hole is formed so that a conductive layer included in another insulating layer constitutes a bottom portion of the via hole. 6. The method of manufacturing a multilayer substrate according to claim 4, wherein the third step selectively forms a conductive material filling the via holes and the pattern formation grooves. The method for manufacturing a multilayer substrate according to claim 1 , wherein the insulating layer is a core substrate. The method for manufacturing a multilayer substrate according to claim 1 , wherein the insulating layer is a build-up layer provided on a core substrate .

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