JP2006080554A - Silicon carbide semiconductor apparatus and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor apparatus that is easy to obtain desired element characteristics and its manufacturing method. <P>SOLUTION: On an N<SP>+</SP>type SiC substrate 1, a first drift layer 2 of an N<SP>-</SP>type and a second drift layer 3 of an N<SP>-</SP>type are formed in order by epitaxial growth. First and second gate regions 5 and 6 of a P<SP>+</SP>type are formed on the first drift layer 2 with the second drift layer 3 between. An N-type source region 4 is formed on the second drift layer 3 and the first and second gate regions 5 and 6, and a part contacting the first and second gate regions 5 and 6 has an impurity concentration at the same level as the second drift layer 3. The uppermost surface has concentration gradient changing continuously to have the impurity concentration at the same level as a substrate 1. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a silicon carbide semiconductor device provided with a J-FET.

FIG. 18 shows a cross-sectional configuration of a silicon carbide semiconductor device provided with an N-channel J-FET. As shown in FIG. 18, the N channel type J-FET is formed using a substrate obtained by epitaxially growing an N ⁻ type drift layer 101 on an N ⁺ type substrate 100 made of silicon carbide. P-type first and second gate regions 102 and 103 are formed in the surface layer portion of the N ⁻ -type epitaxial layer 101 by ion implantation. An N ⁺ type source region 104 is formed in the surface layer portion of the N ⁻ type epi layer 101 between the first and second gate regions 102 and 103. The first and second gate electrodes 105 and 106 are formed on the surfaces of the first and second gate regions 102 and 103, and the source electrode 107 is formed on the surface of the N ⁺ -type source region 104. A drain electrode 108 is formed on the back surface side of N ⁺ type substrate 100 to constitute a silicon carbide semiconductor device.

  When the J-FET having such a configuration is a normally-off type, when no voltage is applied to the first and second gate electrodes 105 and 106, the first and second gate regions 102 and 103 The first and second gate regions 102 and 103 are designed to be pinched off by the extending depletion layer. Then, a current path (substantially channel) is formed by controlling the width of the depletion layer extending from the first and second gate regions 102 and 103, and a current is passed between the source and drain through this portion, so that the J-FET is formed. Make it work.

In the above-described conventional normally-off J-FET, it is desirable that the gate control bias can be applied to the same level as the built-in potential (gate junction diffusion voltage). However, when the built-in potential becomes smaller than the set value, when the gate applied voltage exceeds the built-in potential, holes are injected from the first and second gate regions 102 and 103 into the N ⁻ type drift layer 101, Control by the gate becomes impossible. As a result, problems such as a decrease in recovery characteristics and an increase in leaks occur.

When the substrate material is SiC (silicon carbide), the theoretical value of the built-in potential is about 2.9 volts, but both the first and second gate regions 102 and 103 and the N ⁺ -type source region 104 are ion-implanted. In the case where it is formed, the theoretical value cannot be used as a design value due to a problem that the voltage drops to about 2.1 volts due to crystal defects, etc., and desired device characteristics cannot be obtained. It was. Further, since the first and second gate regions 102 and 103, which are high concentration regions, and the N ⁺ type source region 104 are in contact with each other, there is a problem that junction leakage is likely to occur.

  The present invention has been made under such a background, and an object thereof is to provide a method for manufacturing a silicon carbide semiconductor device in which desired element characteristics can be easily obtained.

  In the first and second aspects of the present invention, the first conductivity type second drift layer (63) having a low concentration is formed between the first and second gate regions (65, 66) of the second conductivity type. For this reason, the first and second gate regions (65, 66) do not have a high-concentration junction, and junction leakage hardly occurs.

  In particular, according to the first aspect of the present invention, the first gate region (65) and the second gate region (66) can be arranged close to each other, which is particularly advantageous when manufacturing a normally-off type device. is there.

In particular, according to the second aspect of the present invention, since the source and the gate can be formed to be separated by self-alignment, it is advantageous in manufacturing a normally-on type device.
In addition, the code | symbol in the bracket | parenthesis of each said member shows the correspondence with the specific member as described in embodiment mentioned later.

  According to the present invention, a silicon carbide semiconductor device having desired element characteristics can be obtained even when the substrate material is SiC (silicon carbide).

(First embodiment)
FIG. 1 shows a cross-sectional configuration of a silicon carbide semiconductor device provided with a J-FET in the present embodiment.

The manufacturing process of the silicon carbide semiconductor device in this embodiment is shown using FIG.
First, as shown in FIG. 2A, an N ⁺ type SiC substrate 61 is prepared, and an N ⁻ type first drift layer 62 and an N ⁻ type second drift are epitaxially grown on the N ⁺ type SiC substrate 61. A layer 63 and an N ⁺ type source region 64 are sequentially formed. The impurity concentration of the source region 64 is about the same as that of the substrate 61. 2B, after forming an LTO film 72 on the surface of the N ⁺ type source region 64, the first and second gate regions 65 and 66 of the LTO film 72 are formed by photolithography. The part corresponding to the formation scheduled position is opened.

Subsequently, as shown in FIG. 2C, using the LTO film 72 as a mask, unnecessary portions of the N ⁺ type source region 64 are removed by etching, and then the second drift layer 63 exposed on the surface using the LTO film 72 as a mask. Are ion-implanted to form P ⁺ -type first and second gate regions 65 and 66. Then, the mask material 72 is removed by etching, and as shown in FIG. 1, an interlayer insulating film 67 is formed on the substrate surface, and then a source electrode and first and second gate electrodes are formed on the interlayer insulating film 67 by photoetching. A contact hole is formed for this purpose. Further, after forming an electrode layer on the interlayer insulating film 67, patterning is performed to form the first and second gate electrodes 69 and 70, and the source electrode 68 is formed. Further, the drain electrode 71 is formed on the back surface side of the N ⁺ type substrate 61. Thereafter, a semiconductor device is completed through a sintering process.

  As described above, in the present embodiment, the first and second gate regions 65 and 66 are formed by etching and ion implantation. For this reason, the first gate region 65 and the second gate region 66 can be disposed close to each other, which is particularly advantageous when a normally-off type device is manufactured. That is, since the distance between the first and second gate regions 65 and 66 can be formed by self-alignment to a minimum, it is easy to obtain a silicon carbide semiconductor element that operates normally.

(Second Embodiment)
Next, the second embodiment will be described focusing on the differences from the first embodiment.
In FIG. 3, the manufacturing process of the silicon carbide semiconductor device in this embodiment is shown. Since this manufacturing process is basically the same as that of the first embodiment, only the parts different from the first embodiment are shown.

The steps up to substantially the steps shown in FIGS. 2A to 2C are the same as those in the first embodiment. That is, a substrate 61 made of N ⁺ type silicon carbide is prepared in FIG. 2, and a first drift layer 62 made of N ⁻ type silicon carbide having an impurity concentration lower than that of the substrate 61 is formed on the substrate 61 by epitaxial growth. , on the first drift layer 62, impurity concentration than the first drift layer 62 even lower N ^- a second drift layer 63 made of the type of silicon carbide is formed by epitaxial growth, on the second drift layer 63, An N ⁺ type source region 64 made of silicon carbide having an impurity concentration similar to that of the substrate 61 is formed by epitaxial growth, an LTO film 72 is disposed at a predetermined position on the surface of the source region 64, and the oxide film 72 is used as a mask. Unnecessary portions of the source region 64 are removed by etching, and the second drift layer 63 is exposed.

  Subsequently, as shown in FIG. 3A, an LTO film 73 is formed on the entire surface of the substrate so as to cover the surface of the substrate including the LTO film 72 and the exposed second drift layer 63. Then, by etching back the entire surface of the LTO film 73 on the surface of the substrate, as shown in FIG. 3B, the second drift layer 63 is exposed again, and the side surfaces of the LTO film 72 and the source region 64 therebelow ( An oxide film side wall 73a is formed on the side wall. Then, using the LTO film 72 and the oxide film sidewall 73a as a mask, ion implantation is performed on the second drift layer 63 exposed on the surface to form first and second gate regions 65 and 66. Thereafter, the oxide film side wall 73a and the LTO film 72 are removed by etching. Then, each electrode is formed.

  Thereby, in this embodiment, since the distance between the first and second gate regions 65 and 66 can be easily controlled by the oxide film sidewall 73a, it is easy to obtain a silicon carbide semiconductor device that operates normally on by self-alignment. . That is, since the source and the gate can be formed to be separated by self-alignment, it is advantageous in manufacturing a normally-on type device.

  Hereinafter, reference examples of the present invention will be described with reference to the drawings. Note that the configurations described in the reference examples listed below are also employed in the first and second embodiments described above, and the effects obtained in the reference examples are also described in the first and second embodiments. There is what can be obtained similarly in the second embodiment.

(First reference example)
In FIG. 4, the cross-sectional structure of the silicon carbide semiconductor device provided with J-FET in this reference example is shown.

As shown in FIG. 4, the silicon carbide semiconductor device includes, for example, an N ⁺ type substrate 1 having an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ or more and, for example, 1 × 10 ^{15 to} 5 × 10 ¹⁶ thereon. An N ⁻ type first drift layer 2 having an impurity concentration of cm ⁻³ is provided. These N ⁺ -type substrate 1 and N ⁻ -type first drift layer 2 are made of silicon carbide, thereby forming a semiconductor substrate. The first drift layer 2 is formed by epitaxial growth.

A first gate region 5 and a second gate region 6 made of a plurality of P ⁺ -type layers are formed on the N ⁻ type drift layer 2 by ion implantation, and the first gate region 5 and the second gate region 6 are mutually connected. An N 2 ⁻ type second drift layer 3 is formed so as to be spaced apart and having a width Wch therebetween. That is, the N-type second drift layer 3 having a lower concentration than the first drift layer 2 is formed on the first drift layer 2, and the second drift layer 3 is formed on the first drift layer 2. First and second gate regions 5 and 6 are formed with a gap therebetween. The first and second gate regions 5 and 6 have an impurity concentration of 1 × 10 ^{18 to} 5 × 10 ¹⁹ cm ⁻³ , for example, and the second drift layer 3 has an impurity concentration of 1 × 10 ^{15 to} 5 × 10 ¹⁵ cm ⁻³ . Impurity concentration. An N type source region 4 is formed by epitaxial growth so as to cover the upper surfaces of the N 2 ⁻ type second drift layer 3 and the first and second gate regions 5 and 6. The N-type source region 4 has a concentration gradient that continuously changes between the lower end and the upper end (film thickness direction). For example, the portion in contact with the first and second gate regions 5 and 6 has the same impurity concentration as the second drift layer 3, and the portion in contact with the source electrode 8 in the outermost surface portion is about the same as the substrate 1. Has a concentration gradient that continuously changes so as to have an impurity concentration of 1 × 10 ^{18 to} 5 × 10 ²⁰ cm ⁻³ .

First and second gate electrodes 9 and 10 electrically connected to the respective regions are formed on the surfaces of the first and second gate regions 5 and 6, and the same region is formed on the surface of the N-type source region 4. 4 is formed, and the first and second gate electrodes 9 and 10 and the source electrode 8 are electrically separated by the interlayer insulating film 7. A drain electrode 11 is formed on the back side of the N ⁺ type substrate 1.

The J-FET configured as described above can operate either normally-off or normally-on depending on the design value. This operation differs depending on the connection mode of the first and second gate electrodes 9 and 10 and is performed as follows.
(Part 1)
When the potentials of the first gate electrode 9 and the second gate electrode 10 are controllable, both the first and second gate regions 5 and 6 are based on the potentials of the first and second gate electrodes 9 and 10. Double gate drive is performed to control the amount of extension of the depletion layer extending from to the second drift layer 3. For example, when no voltage is applied to the first and second gate electrodes 9 and 10, the second drift layer 3 is pinched off by a depletion layer extending from both the first and second gate regions 5 and 6. Thereby, the current between the source and the drain is turned off. When a forward bias is applied between the first and second gate regions 5 and 6 and the substantial channel region (3), the extension amount of the depletion layer extending to the second drift layer 3 is reduced. Thereby, a substantial channel is set, and a current flows between the source and the drain.
(Part 2)
In the case where only the potential of the first gate electrode 9 can be controlled independently and the potential of the second gate electrode 10 is the same potential as the source electrode 8, for example, based on the potential of the first gate electrode 9. Single gate driving for controlling the amount of extension of the depletion layer extending from the first gate region 5 side to the second drift layer 3 side is performed. In this case as well, basically the same operation as in the case of the double gate drive is performed, but the channel is set only by the depletion layer extending from the first gate region 5 side.
(Part 3)
In the case where only the potential of the second gate electrode 10 can be controlled independently and the potential of the first gate electrode 9 is set to the same potential as the source electrode 8, for example, based on the potential of the second gate electrode 10. Single gate driving for controlling the amount of extension of the depletion layer extending from the second gate region 6 side to the second drift layer 3 side is performed. In this case as well, basically the same operation as in the case of the double gate drive is performed, but the channel is set only by the depletion layer extending from the second gate region 6 side.

Next, a method for manufacturing such a silicon carbide semiconductor device will be described with reference to FIGS.
First, as shown in FIG. 5A, an N ⁺ type substrate 1 is prepared, and an N ⁻ type first drift layer 2 and an N ⁻ type second drift layer 3 are formed on the N ⁺ type substrate 1 by epitaxial growth. Is deposited. Further thereon, an N-type source region 4 is formed by epitaxial growth. In the epitaxial growth for forming the source region, the initial concentration is as low as the second drift layer 3 and a continuous concentration gradient is set so as to be high in the final stage of growth (impurity concentration in FIG. 4). (See distribution chart).

Then, as shown in FIG. 5B, after the LTO film 12 is formed on the surface of the N-type source region 4, the first and second gate regions 5 and 6 of the LTO film 12 are formed by photolithography. A part corresponding to the planned position is opened. Subsequently, ions are implanted into the substrate surface using the LTO film 12 as a mask to form P ⁺ -type first and second gate regions 5 and 6 as shown in FIG. FIG. 5C shows the state after removing the mask.

  Subsequently, after removing the mask material 12, as shown in FIG. 6A, unnecessary portions of the N-type source region 4 are removed by photoetching so as to obtain the first and second gate regions 5 and 6. .

Further, as shown in FIG. 6B, after an interlayer insulating film 7 is formed on the substrate surface, contact holes are formed in the interlayer insulating film 7 by photoetching. Then, after an electrode layer is formed on the interlayer insulating film 7, the film is patterned to form the first and second gate electrodes 9 and 10 and the source electrode 8. A drain electrode 11 is formed on the back side of the N ⁺ type substrate 1. Thereafter, the semiconductor device shown in FIG. 1 is completed through a sintering process.

As described above, in the present reference example, the first and second drift layers 2 and 3 and the N-type source region 4 are formed by epitaxial growth, and only the first and second gate regions 5 and 6 are formed by ion implantation. Therefore, manufacturing is easy, and since the ion implantation process is minimized, crystal defects can be suppressed, and the built-in potential can be prevented from lowering than the theoretical value. Furthermore, since there is no high-concentration PN junction, junction leakage can be suppressed. That is, since the source region 4 has a structure having a high concentration portion and a low concentration portion that change continuously, the first and second gate regions 5 and 6 do not contact the high concentration portion, so that a PN junction leak occurs. Hateful.
(Second reference example)
Next, the second reference example will be described focusing on the differences from the first reference example.

In FIG. 7, the cross-sectional structure of the silicon carbide semiconductor device provided with J-FET in this reference example is shown.
In the cell portion, the N-type source region 4 is not selectively etched for contact with the first and second gate regions 5 and 6, and the first and second portions are arranged in the outer peripheral portion of the cell portion where the J-FET is provided. The two gate regions 5 and 6 are configured to be electrically connected to the outside.

A method for manufacturing such a silicon carbide semiconductor device will be described with reference to FIG.
First, through steps similar to those in FIGS. 5A to 5C in the first reference example, first and second gate regions 5 and 6 are formed in the lower layer of the N-type source region 4 by ion implantation. At this time, the first and second gate regions 5 and 6 in FIG. 5C are extended to the outer periphery of the cell.

  Thereafter, the N-type source region 4 at the outer periphery of the cell is subjected to photoetching as shown in FIG. 8 to form openings 13 and 14. As a result, the first and second gate regions 5 and 6 are exposed at the outer periphery of the cell.

Thereafter, as shown in FIG. 7, an insulating layer 7 is formed on the surface of the substrate, and then a predetermined region is removed by photoetching to make contact with the electrode. Further, an electrode layer is formed and patterned to form the first and second gate electrodes 9 and 10 and the source electrode 8. As a result, the source electrode 8 is formed in the cell portion provided with the J-FET, and the first and second gate electrodes 9 and 10 are formed in the cell outer peripheral portion. Then, after forming the drain electrode 11 on the back surface side of the N ⁺ type substrate 1, a semiconductor device is completed through a sintering process.

In this way, the contacts of the first and second gate regions 5 and 6 can be obtained at the cell outer periphery. In this way, it is not necessary to pattern the N-type source region 4 in the cell portion, and the layout of the first and second gate electrodes 9, 10 and the source electrode 8 can be simplified. The structure is advantageous for reducing the element size.
(Third reference example)
Next, a third reference example will be described focusing on differences from the first reference example.

In FIG. 9, the cross-sectional structure of the silicon carbide semiconductor device provided with J-FET in this reference example is shown.
As shown in FIG. 9, in this reference example, an N type drift layer 22 made of silicon carbide is formed on an N ⁺ type SiC substrate 21. The drift layer 22 is formed by epitaxial growth, and the portion in contact with the substrate 21 has the same impurity concentration as that of the substrate 21 and has a concentration gradient that continuously changes so as to become a lower concentration as it becomes an upper layer of the substrate. Inside the drift layer 22, P ⁺ -type first and second gate regions 25 and 26 are formed so as to be separated from each other. An N ⁺ type source region 24 is formed on the drift layer 22 so as to have an impurity concentration comparable to that of the substrate 21.

  The first gate electrode 29 is electrically connected to the first gate region 25, the second gate electrode 30 is electrically connected to the second gate region 26, and the source electrode 28 is electrically connected to the source region 24. Yes. A drain electrode 31 is formed on the back side of the substrate 21.

  Here, the impurity concentration of the drift layer 22 has a distribution that gradually decreases gradually. Therefore, the first and second gate regions 25 and 26 do not have a high-concentration junction, and junction leakage is unlikely to occur. In addition, there is an advantage that the gate breakdown voltage is improved as compared with the case where a high concentration PN junction is formed in the first and second gate regions 25 and 26.

A method for manufacturing such a silicon carbide semiconductor device will be described with reference to FIGS.
First, as shown in FIG. 10A, an N ⁺ type SiC substrate 21 is prepared, and an N type drift layer 22 and an N ⁺ type source region 24 are sequentially formed on the N ⁺ type substrate 21 by an epitaxial growth technique. To do. Here, when the drift layer 22 is formed on the substrate 21, epitaxial growth is performed so that the impurity concentration is initially the same as that of the substrate 21 and the impurity concentration decreases toward the top. Further, the source region 24 has an impurity concentration comparable to that of the substrate 21.

As an example of a specific concentration, an N ⁺ type substrate 21 having a concentration of 1 × 10 ¹⁸ cm ⁻³ is prepared, and epitaxial growth of the N type drift layer 22 having a concentration of 1 × 10 ¹⁶ cm ⁻³ is started. Then, the concentration is continuously decreased from 1 × 10 ¹⁶ cm ⁻³ to 5 × 10 ¹⁵ cm ⁻³ so as to obtain a desired film thickness. Next, the N ⁺ type source region 4 is epitaxially grown at a concentration of 1 × 10 ¹⁹ cm ⁻³ .

Subsequently, as shown in FIG. 10B, a resist 35 is arranged on the upper surface of the source region 24, and using this as a mask, P ⁺ -type first and second gate regions 25 as shown in FIG. 10C. , 26 are formed. That is, the first gate region 25 and the second gate region 26 are formed in the drift layer 22 by an ion implantation technique so as to be separated from each other. Further, as shown in FIG. 11A, unnecessary portions of the N ⁺ type source region 24 are removed, and as shown in FIG. 11B, the interlayer insulating film 27, the source electrode 28, the first gate electrode 29, the first gate electrode 29, Two gate electrodes 30 and a drain electrode 31 are formed.

  Thereby, the structure shown in FIG. 9 can be obtained. In this manufacturing method, since the impurity concentration in the drift layer 22 under the source region 24 is continuously changed, the silicon carbide semiconductor device can be manufactured by continuously changing the material gas concentration for epitaxial growth. This is advantageous in improving throughput and can be manufactured particularly easily and inexpensively.

In this structure, as in the first and second reference examples, the contact can be formed inside or on the outer periphery of the cell portion.
(Fourth reference example)
Next, a fourth reference example will be described focusing on differences from the first reference example.

In FIG. 12, the cross-sectional structure of the silicon carbide semiconductor device provided with J-FET in this reference example is shown.
In comparison with the first reference example shown in FIG. 4, in this reference example shown in FIG. 12, an N ⁻ -type layer 43 is formed on the first and second gate regions 45 and 46, and The N-type source region 44 has a structure having no concentration gradient. That is, the N ⁻ type first drift layer 42 is silicon carbide formed by epitaxial growth on the substrate 41 made of N ⁺ type SiC and having a lower concentration than the substrate 41. The P ⁺ -type first and second gate regions 45 and 46 are formed on the first drift layer 42 so as to be separated from each other. Further, the N 2 ⁻ type second drift layer 43 is formed so as to cover between the first and second gate regions 45 and 46 and the upper surfaces of the first and second gate regions 45 and 46, and The density is relatively lower than that of the layer 42. The N ⁺ -type source region 44 is formed on the second drift layer 43 and has an impurity concentration comparable to that of the substrate 41. The first gate electrode 49 is electrically connected to the first gate region 45, and the second gate electrode 50 is electrically connected to the second gate region 46. The source electrode 48 is electrically connected to the source region 44, and the drain electrode 51 is formed on the back side of the substrate 41.

A method for manufacturing such a silicon carbide semiconductor device will be described with reference to FIGS.
As shown in FIG. 13A, a substrate 41 made of N ⁺ type silicon carbide is prepared, and a first drift layer 42 made of N ⁻ type silicon carbide having an impurity concentration lower than that of the substrate 41 is provided on the substrate 41. Are formed by epitaxial growth. Then, on the first drift layer 42, impurity concentration than the first drift layer 42 lower N ^- formed by the mold a second drift layer 43 made of silicon carbide epitaxial growth. Further, an N ⁺ type source region 44 made of silicon carbide having an impurity concentration similar to that of the substrate 41 is formed on the second drift layer 43 by epitaxial growth.

Thereafter, as shown in FIG. 13 (b), a mask material 52 is disposed on the upper surface of the source region 44, and then, as shown in FIG. 14 (a), P is introduced into the second drift layer 43 by an ion implantation technique. ⁺ Type first and second gate regions 45 and 46 are formed. The first and second gate regions 45 and 46 are formed at positions that are in contact with the first drift layer 42 and are separated from each other. Then, as shown in FIG. 14B, after unnecessary portions of the source region 44 are removed, an interlayer insulating film 47 is disposed in a predetermined region as shown in FIG. 12, and the first gate region 45 is electrically connected. A first gate electrode 49 connected to the first gate electrode 50; a second gate electrode 50 electrically connected to the second gate region 46; a source electrode 48 electrically connected to the source region 44; The drain electrode 51 is formed.

Thus, first, the second gate region 45 and 46, by adjusting the ion implantation energy, the 1, N on the second gate region 45 and 46 ^- as type layer 43 is present, also, N The mold source region 44 does not have a concentration gradient.

In the structure of FIG. 12, since the first and second gate regions 45 and 46 are not in contact with the source region 44, leakage due to a high concentration PN junction can be prevented. That is, the low-concentration N-type (N ⁻ -type) second drift layer 43 is formed so as to cover the first and second gate regions 45 and 46 and the upper surfaces of the first and second gate regions 45 and 46. Therefore, the first and second gate regions 45 and 46 do not have high-concentration junctions, and junction leakage hardly occurs.

  Further, according to the present manufacturing process, in the drift layers 42 and 43 and the source region 44, the impurity concentration on the substrate surface is high, the impurity concentration in the drift layers 42 and 43 is low, and the portion that becomes the upper surface of the gate regions 45 and 46 Is epitaxially grown so that the impurity concentration becomes very thin, and only the first and second gate regions 45 and 46 are formed by ion implantation. This method is simple, inexpensive to manufacture, and can prevent the built-in potential from being lower than the theoretical value in terms of device characteristics, and can maintain a high breakdown voltage between the source and gate. It is. In addition, when the first and second gate regions 45 and 46 are formed by the ion implantation technique, the second drift layer 43 is present between the first and second gate regions 45 and 46 and the source region 44. As a result, it is possible to insert a layer with a low impurity concentration between the source and the gate, thereby preventing junction leakage between the source and the gate. In particular, when forming a normally-on silicon carbide semiconductor device, It becomes a device with high pressure resistance.

12 to 14, when the first and second gate regions 45 and 46 are formed by the ion implantation technique, the first and second gate regions 45 and 46 are connected to the source via the second drift layer 43. The ions are implanted so as to be opposed to the region 44. As shown in FIGS. 15A and 15B, the first and second gate regions 45 and 46 are in direct contact with the source region 44, and The ion implantation may be performed so that the two drift layer 43 exists only between the first and second gate regions 45 and 46 which are separated from each other. Thus, an ideal silicon carbide semiconductor device can be obtained in which a depletion layer is formed only in second drift layer 43 between first and second gate regions 45 and 46 that are separated from each other.
(Fifth reference example)
Next, a fifth reference example will be described focusing on differences from the first to fourth reference examples.

  16 and 17 show a cross-sectional configuration of a silicon carbide semiconductor device provided with a J-FET in this reference example. FIG. 16 corresponds to FIG. 12 in the fourth reference example, and FIG. 17 corresponds to the case of FIG.

  In this reference example, insulator layers 80, 81, 82, 83 made by adding vanadium (V) are formed on and in contact with the first and second gate regions 45, 46. That is, in this reference example, V (vanadium) is ion-implanted using the same mask immediately after the ion implantation process of the first and second gate regions, as compared with the fourth reference example (the same applies to other reference examples) Insulator layers 80, 81, 82, 83 are inserted in portions where the first and second gate regions 45, 46 and the source region 44 are opposed to each other. That is, by injecting V (vanadium) into the same region after the step of implanting ions into the first and second gate regions 45 and 46, the insulator in contact with the first and second gate regions 45 and 46 is in contact. Including the step of inserting the layers 80, 81, 82, 83.

  By the insulator layers 80, 81, 82, 83, the NPN parasitic bipolar operation by the N-type drain portions (41, 42), the P-type gate portions (45, 46), and the N-type source portions (43, 44). Can be suppressed. That is, since the first and second gate regions 45 and 46 are disposed opposite to the high concentration source region 44 via the insulator layers 80, 81, 82, and 83, an NPN parasitic bipolar operation is unlikely to occur.

  The reference examples described so far are not limited to the normally-off type, and can be applied to a normally-on type J-FET.

1 is a longitudinal sectional view of a silicon carbide semiconductor device in a first embodiment. FIG. FIG. 4 shows a manufacturing process of the silicon carbide semiconductor device shown in FIG. 1. The figure which shows the manufacturing process of the silicon carbide semiconductor device in 2nd Embodiment. The longitudinal cross-sectional view of the silicon carbide semiconductor device in a 1st reference example. FIG. 5 shows a manufacturing process of the silicon carbide semiconductor device shown in FIG. 4. FIG. 5 shows a manufacturing process of the silicon carbide semiconductor device shown in FIG. 4. The longitudinal cross-sectional view of the silicon carbide semiconductor device in a 2nd reference example. FIG. 8 shows a manufacturing process of the silicon carbide semiconductor device shown in FIG. 7. The longitudinal cross-sectional view of the silicon carbide semiconductor device in a 3rd reference example. FIG. 10 shows a manufacturing process of the silicon carbide semiconductor device shown in FIG. 9. FIG. 10 shows a manufacturing process of the silicon carbide semiconductor device shown in FIG. 9. The longitudinal cross-sectional view of the silicon carbide semiconductor device in a 4th reference example. FIG. 13 shows a manufacturing process of the silicon carbide semiconductor device shown in FIG. 12. FIG. 13 shows a manufacturing process of the silicon carbide semiconductor device shown in FIG. 12. The figure which shows the manufacturing process of the silicon carbide semiconductor device of another example. The longitudinal cross-sectional view of the silicon carbide semiconductor device in a 5th reference example. The longitudinal cross-sectional view of the silicon carbide semiconductor device in a 5th reference example. The figure which shows the cross-sectional structure of the conventional silicon carbide semiconductor device.

Explanation of symbols

1 ... N ⁺ -type substrate, 2 ... N ^- -type first drift layer, 3 ... N ^- -type second drift layer, 4 ... N-type source region, 5 ... first gate region, 6: second gate region, 8 ... Source electrode, 9 ... First gate electrode, 10 ... Second gate electrode, 11 ... Drain electrode, 21 ... N ⁺ type substrate, 22 ... N-type drift layer, 24 ... N-type source region, 25 ... First gate region , 26 ... second gate region, 28 ... source electrode, 29 ... first gate electrode, 30 ... second gate electrode, 31 ... drain electrode, 41 ... N ⁺ type substrate, 42 ... N ^- type first drift layer, 43 ... N ^- -type second drift layer, 44 ... N-type source region, 45 ... first gate region, 46 ... second gate region, 48 ... source electrode, 49 ... first gate electrode, 50 ... second gate electrode, 51 ... Drain electrode, 73 ... LTO film, 73a ... Oxide film side wall, 80, 8 1, 82, 83 ... insulator layers.

Claims (2)

Forming a first drift layer (62) made of silicon carbide of the first conductivity type having a lower impurity concentration than the substrate (61) by epitaxial growth on the substrate (61) made of silicon carbide of the first conductivity type; ,
Forming, on the first drift layer (62), a second drift layer (63) made of silicon carbide of the first conductivity type having a lower impurity concentration than the first drift layer (62) by epitaxial growth;
Forming, on the second drift layer (63), a first conductivity type source region (64) made of silicon carbide having an impurity concentration similar to that of the substrate (61) by epitaxial growth;
Disposing an oxide film (72) at a predetermined position on the surface of the source region (64);
Removing unnecessary portions of the source region (64) by etching using the oxide film (72) as a mask;
Forming second conductive type first and second gate regions (65, 66) by ion implantation in the second drift layer (63) exposed on the surface using the oxide film (72) as a mask;
Removing the oxide film (72) by etching;
A first gate electrode (69) electrically connected to the first gate region (65); a second gate electrode (70) electrically connected to the second gate region (66); and the source Forming a source electrode (68) electrically connected to the region (64) and a drain electrode (71) on the back side of the substrate (61);
A method for manufacturing a silicon carbide semiconductor device, comprising: Forming a first drift layer (62) made of silicon carbide of the first conductivity type having a lower impurity concentration than the substrate (61) by epitaxial growth on the substrate (61) made of silicon carbide of the first conductivity type; ,
Forming, on the first drift layer (62), a second drift layer (63) made of silicon carbide of the first conductivity type having a lower impurity concentration than the first drift layer (62) by epitaxial growth;
Forming, on the second drift layer (63), a first conductivity type source region (64) made of silicon carbide having an impurity concentration similar to that of the substrate (61) by epitaxial growth;
Disposing an oxide film (72) at a predetermined position on the surface of the source region (64);
Removing unnecessary portions of the source region (64) by etching using the oxide film (72) as a mask to expose the second drift layer (63);
Forming an oxide film (73) so as to cover the surface of the substrate comprising the oxide film (72) and the exposed second drift layer (63);
The second drift layer (63) is exposed again by etching back the entire surface of the oxide film (73) on the surface of the substrate, and oxidized on the side surfaces of the oxide film (72) and the source region (64) therebelow. Forming a film sidewall (73a);
Using the oxide film (72) and the oxide film side wall (73a) as a mask, the second drift layer (63) exposed on the surface is ion-implanted to form first and second gate regions (second conductivity type). 65, 66),
Removing the oxide film sidewall (73a) and the oxide film (72) by etching;
A first gate electrode (69) electrically connected to the first gate region (65); a second gate electrode (70) electrically connected to the second gate region (66); and the source Forming a source electrode (68) electrically connected to the region (64) and a drain electrode (71) on the back side of the substrate (61);
A method for manufacturing a silicon carbide semiconductor device, comprising:

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