JPH03244163A - Manufacture of electrostatic induction semiconductor device - Google Patents

Abstract

PURPOSE:To make an alignment between gate and source regions maintain always with high accuracy and to set the reverse breakdown strength between a gate and a source at a desired value by a method wherein windows for gate region use are formed by making masks exist, the masks are removed in a state that sidewalls are left and windows for source region use are formed. CONSTITUTION:A substrate 1 formed by depositing an n<-> layer 3 on an n<+> semiconductor layer 2 is used, polycrystalline Si layers which are used as masks 5 are respectively provided on the surface of this substrate 1 via thin oxide films 4 of a prescribed pattern and an oxide film 6 for sidewall use is formed on the side surfaces of these masks 5. Then, P-type impurity ions are implanted using the masks 5 and the film 6 as masks, a p<+> gate region 15 is formed between the masks 5 and at this time, oxide films 10 and 10', which are respectively formed on the masks 5 and the region 15, are etched and removed and an oxide film 16 is applied on the whole surface while masks 5 are buried. After that, N-type impurity ions are implanted through windows 20 formed by removing the masks 5 and n<+> source regions 18 are formed.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing an electrostatic induction semiconductor device.

[Conventional technology]

Static induction semiconductor devices (for example, static induction transistors or static induction zyristors) are characterized by high gate drive sensitivity and high-speed characteristics. Gate-type electrostatic induction semiconductor devices have even more remarkable high-speed characteristics because the impedance of the gate is low.

Figure 2 shows the basic configuration of a surface gate type static induction transistor. This static induction transistor includes a semiconductor substrate 60 in which an n+ semiconductor layer 61 and an n− semiconductor layer 62 are laminated, and as shown in FIG. A gate region (p impurity diffusion region) 63 and a gate region (p impurity diffusion region) 64 are formed such that the gate region 64 sandwiches the source region 63. The illustrated static induction transistor has a vertical structure in which the drain electrode 51 is provided on the back surface of the substrate opposite to the source electrode 52 and the gate region 53.

Conventionally, the areas around the gate region and source region of this static induction transistor have been made as follows.

First, as shown in FIG. 3 (al), an oxide film 71 is formed on the surface of the semiconductor substrate 60 in which an n-semiconductor N61 and an n-semiconductor N62 are laminated. , a window 72 is formed in the oxide film 71 to expose the area where the gate region will be formed, and an n-type impurity is implanted and diffused using the remaining oxide film 71 as a mask to form the gate region 64. When forming the gate region 64, an oxide film 73 is formed on the window 72.

Subsequently, as shown in FIG. 3Fdl, a window 7 is formed in the oxide film 71.
4 to expose the source region forming portion of the semiconductor substrate 60, as shown in FIG. 3(e), the window 7 is opened.
An n-type impurity is supplied from step 4 to form a source region 63.

[Problem to be solved by the invention]

In the case of the above manufacturing method, the source region 63 and the gate region 6
4, that is, the alignment accuracy between the source region 63 and the gate region 64 varies greatly. Conventionally,
As described above, since the alignment accuracy is not sufficient, the reverse breakdown voltage between the gate and source of the obtained static induction transistor is out of the permissible range, resulting in a problem of poor yield.

In order to improve alignment accuracy, the interval between the window 72 for supplying impurities for the gate region and the window 74 for supplying impurities for the source region must be exactly a predetermined value. However, in the conventional method, each window 72.7
The interval between windows 72 and 74 is determined by the accuracy of mask alignment in the process, but it is difficult to perform this mask alignment with high precision, and as a result, the intervals between windows 72 and 74 vary. Therefore, it does not reach the predetermined value.

SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a method capable of manufacturing a static induction semiconductor device having a desired gate-to-source reverse breakdown voltage with a high yield.

[Means to solve the problem]

In order to solve the above problems, the present invention manufactures an electrostatic induction semiconductor device in which a source region and a gate region are positioned on the surface of a semiconductor substrate, with the gate region sandwiching the source region. In this case, the semiconductor substrate is such that the source region formation area is covered with a mask, and a sidewall is formed on the side surface of the mask to cover the space between the gate area formation area and the gate area formation area. The impurity diffusion region for the gate region is formed using a semiconductor substrate with exposed formation portions, and then,
The mask is removed and source region forming impurities are supplied to the source region forming locations.

The electrostatic induction semiconductor device in this invention includes a static induction transistor, an electrostatic induction SIRISK, etc. In the case of a SIRISK, the source is commonly called a cathode (DOI/IN is an anode), and therefore, the scope of the claims is In the case of cyrisk, the source shall be read as the cathode. The basic structure of the static induction transistor is as shown in FIG. 2, and the basic structure of the static induction transistor is shown in FIG. (b) The structure is changed to a p semiconductor layer.

[For production]

In the manufacturing method of the present invention, a window for the gate region is created by the presence of the mask, and a window for the source region is created by removing the mask while leaving the sidewalls. That is, the area between the sidewalls is the window for the gate region, and the area left after removing the mask is the window for the source (or cathode) region. Therefore, the width of the sidewall determines the distance between the gate region and the source region. Therefore, the alignment accuracy between the gate region and the source region is determined by the width accuracy of the sidewalls, regardless of the positional accuracy of the mask. Since this sidewall is easily manufactured to a desired width with high accuracy, it is easy to maintain high alignment accuracy between the gate region and the source region at all times. Therefore, a static induction semiconductor device having a gate-source reverse breakdown voltage at a desired value can be easily manufactured with a high yield.

C Embodiment] Hereinafter, the present invention will be explained in detail with reference to FIG. 1, taking as an example the case of manufacturing a surface gate type vertical structure static induction transistor.

First, as shown in FIG. 1(a), after forming a thin oxide film 4' on the surface of a semiconductor substrate I having an n-semiconductor layer 3 on an n-semiconductor layer 2, a polysilicon film 5 for a mask is formed. 1, the polysilicon 5' is patterned by dry etching, etc., and the exposed portions of the oxide film 4' are removed by etching, etc., as shown in FIG. (As shown in BL, the source region formation area is formed using polysilicon (mask) through a thin oxide film 4.
Leave it covered with 5. Note that the thin oxide film 4 has the function of preventing the type 9 impurity for the gate region from diffusing into the region where the source region is to be formed through the polysilicon 5;
The thickness is selected to be such that n-type impurities for the source region can be implanted later.

Next, as shown in FIG. 1(C), a sidewall oxide film 6' is laminated. The oxide film 6' is an oxide film having excellent step coverage, and is exemplified by an oxide film deposited by low pressure CVD at a temperature of about 850'C.

After forming the oxide film 6', an anisotropic dry etching process is performed to form a sidewall 6 on the side surface of the polysilicon 5, as shown in FIG. 1(d). The width of the sidewall 6 can be easily and precisely controlled by adjusting the thickness of the oxide film.

In the semiconductor substrate 1 shown in FIG. 1fd), the source region formation area is covered with a polysilicon (mask) 5, and a sidewall 6 is provided on the side surface of the polysilicon 5 to cover the space between the gate area formation area and the semiconductor substrate 1. This is a semiconductor substrate in which a portion for forming a gate region is exposed. The window 7 is left open at the location where the gate region is to be formed.

Next, as shown in FIG. 1(e), a p-type impurity is implanted through the window 7 (for example, boron (B
), perform appropriate thermal diffusion treatment, and then
As shown in FIG.
form.

When forming the oxide film 10, an oxide film 10' is also formed on the surface of the polysilicon 5, so as shown in FIG. As shown in FIG. 1(h), the oxide film 10' is removed by etching and notching, and then the resist 11 is removed. The resist 11 is used only to remove the oxide film 10', and does not require very precise dimensional accuracy and alignment accuracy.

Then, as shown in FIG. 1 (11), the polysilicon 5 is selectively etched away to open a source region window 20. Note that a thin oxide film 4 remains at the bottom of the window 20.

Next, as shown in FIG. 1, an n-type impurity is implanted through the window 20 through the oxide film 4 by an ion implantation method (for example, phosphorus (P) ions are implanted) to form a source region 18.

Thereafter, contact windows are opened, electrodes are formed, etc. according to the usual method, and the static induction transistor is completed.

Note that, in the above, the n-type impurity was supplied while leaving the oxide film 4, but the oxide film 4 may also be removed.

Further, depending on the material of the mask, the formation of the thin oxide film 4 may be omitted, and the present invention is not limited to the above embodiment. For example, in the above embodiment, if the n' semiconductor layer 2 of the semiconductor substrate 1 is a p' semiconductor layer, this is an example of electrostatic induction silicone manufacturing. Furthermore, in the above embodiment, n
Another example is one in which the type and p-type are completely reversed.

Note that the manufacturing method of the present invention also has the following advantages.

Conventionally, if you try to change the distance between the gate region and the source region without changing the source region window and the mask pattern for creating the source region window, the depth of the gate region will change, and it will be difficult to change. Even the characteristics you don't want will change. In this invention, the window width for the gate region can be changed simply by changing the width of the sidewall without changing the mask pattern, so the gap between the gate region and the source region can be adjusted without changing the depth of the gate region. Changes are possible. This word means that each characteristic between gate and source, normally ion characteristics, normally ion characteristics, etc. can be controlled easily and appropriately without changing the mask in any way. - layer,
It is considered useful.

〔Effect of the invention〕

As described above, in the method for manufacturing a static induction semiconductor device of the present invention, it is possible to easily maintain high alignment accuracy between the gate region and the source region at all times.
A static induction semiconductor device having a desired gate-source reverse breakdown voltage can be easily manufactured at a high yield.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view showing the process of obtaining a surface gate type vertical structure static induction transistor according to an example of the present invention, and FIG. 2 is a surface gate type vertical structure static induction transistor. 1. Semiconductor substrate 5.・Polysilicon (
Mask) 6...Side wall 15...Gate region 18...Source region

Claims (1)

[Claims] 1. In a method for manufacturing an electrostatic induction semiconductor device in which a source region and a gate region are formed on a surface portion of a semiconductor substrate, with the gate region sandwiching the source region, the semiconductor substrate is used as the semiconductor substrate for forming the source region. A semiconductor substrate is used in which a portion is covered with a mask, and a side wall is formed on the side surface of the mask to cover a space between the portion and the portion where the gate region is formed, and the portion where the gate region is formed is exposed. forming an impurity diffusion region for a gate region, and then removing the mask to supply source region forming impurities to the source region forming location. Method.