JPH0529235A - Manufacture of gaas element having high purity layer - Google Patents

Abstract

PURPOSE:To manufacture the title GaAs element having a high purity layer or pin, nin, pip, nip structure without developing unmatched lattice at all. CONSTITUTION:An n<-> or p<->GaAs substrate 1 is mounted on a solution melting GaAs and then a p<+> or n<+> GaAs grown layer 2 is formed on the substrate 1. Next, said substrate 1 is polished to form an n<-> or p<->GaAs layer 1a in specific thickness. Later, an n<+> or p<+> layer is formed on the p<->GaAs layer 1a further to form an element having a high purity layer or a pin structure. At this time, the impurities wherein the mean value of common coupling radius of a unit body or assembled body is almost equal to the mean value of common coupling radius of Ga and As are to be used as the impurities of the GaAs grown layer 2.

Description

Detailed Description of the Invention

[0001]

The present invention relates to GaA having a high purity layer.
The present invention relates to a method of manufacturing an s element.

[0002]

2. Description of the Related Art As an element having a high-purity layer (i layer),
pin diode, static induction transistor (SIT),
There are bipolar static induction transistors (BSIT), static induction (SI) thyristors and the like. Conventionally, these elements were generally manufactured using Si as a material, but it is conceivable to manufacture them using GaAs, which has various excellent characteristics as compared with Si.

In general, GaAs is excellent in manufacturing a semiconductor element, particularly a power semiconductor element, because it has a higher electron mobility, a higher breakdown voltage, and a very short life of both electrons and holes, as compared with Si. It has the following features. That is, it is possible to fabricate a high-speed switching element while utilizing the characteristics of the intrinsic (i) semiconductor without using a lifetime killer as is performed with Si. Further, since GaAs is a direct transition type semiconductor unlike Si, it can be expected to emit light with high brightness and high sensitivity with switching. Especially for GaAs, SI thyristor or BSI
If T is realized, it will be possible to establish a completely electrically isolated optically controlled power system that controls the power of several hundreds of volts and several tens of amps with light, and the device itself serves as a light source to the device in the next stage. It will be possible.

[0004]

However, since GaAs is still behind in its crystal growth technology and device fabrication technology compared with Si, SIT, BSIT, S
Currently, there is no device such as an I thyristor which requires an i layer having a certain thickness or more. This becomes the active layer of the device i
This is because it is very difficult to form a layer. Reported G
In aAsSIT, the impurity concentration of the i layer is 10 ¹⁴ to
It is about 10 ¹⁵ cm ^-3 , and a sufficiently low value cannot be obtained for an i layer.

The cause of this is that in the conventional technique, as shown in FIG. 20, an i layer (n ⁻ layer) B is grown on an n ⁺ GaAs substrate (wafer) A by a vapor phase growth method or a liquid layer growth method,
This is because the element is formed thereon, and when the n ⁻ layer (i layer) B is grown on the n ⁺ substrate A, an i layer having a sufficiently low impurity concentration is obtained by impurity diffusion or autodoping. I can't.

However, even if a high-purity i-layer is obtained, since the impurity concentrations of the n ⁺ substrate and the i-layer are different by several orders of magnitude, the lattice constants of both layers are effectively different and the lattice mismatch is present. Due to the misfit dislocation (FIG. 21 (a)) and the substrate curvature (FIG. 21 (b)).
When such a substrate is used, there are serious problems such as misalignment of the mask due to the curvature of the substrate and breakage of the substrate during the element manufacturing process.

As described above, in the conventional technique, there is a contradiction that an element is not ideal if an attempt is made to create a more ideal element.

Therefore, in view of the above points, the present invention has as its main object to provide a method of manufacturing a GaAs device having a high-purity layer.

Another object of the present invention is to provide a manufacturing method capable of manufacturing a GaAs device having a high-purity layer without causing lattice mismatch.

The present invention further includes pin, nin, and pip.
Another object of the present invention is to provide a method of manufacturing a GaAs device having a nip structure.

[0011]

In order to solve the above-mentioned main problems, GaAs having a high-purity layer formed according to the present invention.
As shown in FIG. 1 (a), the method for manufacturing the element is such that high purity G
An aAs substrate 1 is prepared, and a GaAs growth layer 2 having a high impurity concentration is formed on the high-purity GaAs substrate 1 as shown in FIG.
Forming high purity GaAs as shown in FIG. 1 (c).
The substrate 1 is polished to form a high-purity GaAs layer 1a having a predetermined thickness, and then an element is formed on the high-purity GaAs layer 1a.

In order to solve the above problems, a method of manufacturing a GaAs device having a high-purity layer according to the present invention is described in FIG.
As shown in (a), n ⁻ or p ⁻ GaAs substrate 1
Was prepared, the as shown in FIG. (B) n ^- or p ^- high purity p ⁺ or n ⁺ GaAs growth layer 2 is formed on a GaAs substrate 1, the as shown in FIG. 1 (c) n ^- Alternatively, the p ⁻ GaAs substrate 1 is polished to form an n ⁻ or p ⁻ GaAs layer 1a having a predetermined thickness, and then an n ⁺ or p ⁺ layer is formed on the n ⁻ or p ⁻ GaAs layer 1a to form a pin, It is characterized by forming nin, pip and nip structure elements.

The GaAs growth layer 2 is formed by a liquid phase epitaxy method.

The formation of the GaAs growth layer 2 by the liquid phase growth method is performed by using the Ga above the solution in which GaAs is dissolved.
It is characterized in that the As substrate 1 is placed.

As the impurities of the GaAs growth layer 2, a substance having an average value of covalent bond radii of a single substance or a combined covalent bond radius that is substantially equal to an average value of covalent bond radii of Ga and As is used. And

[0016]

In the above method, after the GaAs growth layer 2 having a high impurity concentration is formed on the high-purity GaAs substrate 1, the high-purity G layer is formed.
Since the aAs substrate 1 is polished to form the high-purity GaAs layer 1a having a predetermined thickness, the high-purity G having a certain thickness is used.
It is possible to obtain an aAs layer, and this high-purity GaAs layer 1a
By forming an element on the substrate, a GaAs element having a high-purity layer can be manufactured.

In the above method, n ⁻ or p
^- After forming the p ⁺ or n ⁺ GaAs growth layer 2 on the GaAs substrate 1 n ^- or ^p - of polishing the GaAs substrate 1 a predetermined thickness n ^- or ^p - to form a GaAs layer 1a, the n ^- or ^p - to form a n ⁺ or p ⁺ layer in the GaAs layer 1a pin, nin, pip and n
It is possible to manufacture a GaAs device having a high-purity layer having an ip structure.

Since the GaAs growth layer 2 is formed by the liquid phase growth method, the thick growth layer 2 can be formed. In particular, the GaAs growth layer 2 is formed on the upper side of the solution in which GaAs is dissolved. Since the GaAs substrate 1 is placed on the substrate, the thick growth layer 2 can be efficiently formed in a short time.

As the impurities of the GaAs growth layer 2, the one having the average value of the covalent bond radii of the single substance or the average value of the covalent bond radii of the combination is substantially equal to the average value of the covalent bond radii of Ga and As is used. , GaAs growth layer 2 and GaA
Even if the concentration difference from the s layer 1a is large, the lattice matching does not deteriorate.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a principle embodiment of the method according to the invention. First, a high-purity GaAs substrate (n ⁻
Alternatively, p ⁻ 10 ¹¹ to 10 ¹³ cm ⁻³ ) 1 on top of FIG.
As shown in (b), a thick GaAs layer (n ⁺ or p ⁺ 10 ¹⁸ to 10 ²⁰ cm) with a thickness of about 300 μm was formed by liquid phase epitaxy
^{- 3)} to grow 2. Next, as shown in FIG. 1C, the high-purity GaAs substrate 1 is polished to a predetermined thickness, and an element is formed on this high-purity GaAs layer 1a. As a result, the original substrate becomes the active layer of the device and the growth layer becomes the substrate of the device.

Here, Ga is used as a solvent for the liquid phase growth method of GaAs. Since the solubility of GaAs in Ga is high, a growth layer having a thickness of 300 μm can be easily obtained by performing slow cooling once from 900 ° C. to 600 ° C. In addition to Ga, Sn, Bi, In, or the like can be used as the solvent in consideration of lattice compensation.

As described above, the i-layer and the high-impurity-concentration layer have different lattice constants because the impurity concentrations contained in the crystal are different by 7 to 8 digits. That is, the strain caused by the lattice mismatch cannot be ignored, and causes the curvature of the substrate and misfit dislocations. However, Ge is used as an impurity for p ⁺ growth, and Te and P are used as impurities for n ⁺ growth. , Se and Sb, Se and Sn, S and Sb, S and Sn, S
The use of a combination of n and Si solves the problem of lattice mismatch caused by misfit dislocations and substrate curvature. Here, when Sn is used as an impurity,
It is also possible to use Sn as a solvent in advance.

That is, using the lattice compensation effect, p⁺
Or n⁺Let the lattice constant of the growth layer be p ^-Or n^-substrate
Select an impurity that can match the lattice constant of
is doing. n^-Or p^-GaAs is almost an impurity
Is not included, it is close to intrinsic GaAs, so its lattice constant is intrinsic
It is thought that it has almost the same value as the lattice constant of GaAs crystal.
It

First, the case of Ge as a p-type dopant will be described with reference to Table 1 showing typical covalent bond radii of atoms. Ge has a covalent radius of 1.22,
It is just the average value of the covalent bond radius of Ga and As. The actual lattice constants of GaAs and Ge single crystals are very close to 5.6533Å and 5.6461Å, respectively. As a result, even if Ge is added at about 10 ¹⁹ cm ⁻³ , the lattice constant of that layer matches the lattice constant of the n ⁻ or p ⁻ layer.

[Table 1]

In the case of an n-type dopant, there is no one having the same covalent bond radius as Ge, so two types of impurities are combined. Now, when using Te as an n-type dopant, from Table 1, the covalent bond radius of Te is 1.3.
It turns out that it is larger than the values of 2Å and Ga and As. In this case, the lattice constant is n ⁻ or p ⁻ by simultaneously adding P, which is the same V group as As and does not serve as a p-type dopant and has a covalent radius smaller than Ga or As.
It can be fitted to a GaAs substrate, and for the same reason, n
A combination of the above impurities can be used as the type dopant. That is, in both cases of n ⁺ growth and p ⁺ growth, even if a junction of layers having an impurity concentration difference of 7 to 8 digits is formed, a substrate having an i layer without misfit dislocations or curves is obtained. It becomes possible to provide. Se may be used as the n-type dopant.

The thickness of the i layer varies depending on the application of the element, but can be arbitrarily selected within the range of processing precision of the polishing technique. With the current polishing technology, an arbitrary thickness can be obtained within an error range of about 1 μm. Actually, a thickness of about 5 μm to 100 μm is used as a GaAs power element.

The method of the present invention is the reverse of the idea of the conventional GaAs device fabrication technique, and shows that n ⁻ and p ⁻ high-purity G
The aAs substrate serves as the active layer of the device, and the thick p ⁺ and n ⁺ layers formed by the liquid layer growth method serve as the device substrate. That is, in a device manufacturing process using a normal epitaxy technique, first, a method of growing a low impurity concentration semiconductor layer for forming an active region of a device on a high impurity concentration semiconductor substrate by an epitaxial method is used. Has been. On the other hand, in the present invention, unlike the conventional technique, a thick layer with a high impurity concentration is grown by an epitaxial technique on a high-purity (low impurity concentration) substrate cut out from a high-purity crystal, and conversely as a substrate. The active region of the device is constructed over the entire high-purity (low impurity concentration) semiconductor used, that is, the substrate side.

As described above, using GaAs, SI
To make T, SI thyristor, etc.
m high purity GaAs layer and thick n ⁺ or p ⁺ layer (3
(About 00 μm) is required. When the SI thyristor is made of Si, the high purity layer has a thickness of 100.
Since it may be necessary to have a thickness of μm or more, and the p ⁺ layer is only an electrode, it is easy to form. However, in the case of GaAs, the thickness of the high-purity layer must be thin, and it itself supports the device. Therefore, the p ⁺ (or n ⁺ ) layer must be thick so that it serves not only as an electrode but also as a substrate for the device. In the device manufacturing process according to the present method, after the growth, the high-purity layer that was originally the substrate needs to be polished so that it can withstand the thickness.

A practical liquid phase growth method effective for growing such a thick high impurity concentration layer on a high purity substrate in a short time will be described below with reference to FIG. First, high purity Ga is placed in a carbon boat for growing a GaAs thick film shown in FIG.
The As substrate 41, the Ga solution 42 for growth, and the GaAs polycrystal 43 for raw materials are set, and the temperature is raised to 900 ° C. in a hydrogen atmosphere and kept for an appropriate time.

The high-purity GaAs substrate 41 has a plane orientation of (100). Of course, the plane orientation of the substrate 41 may be, for example, (111) A or (111) B other than this. Further, the Ga solution 42 is prepared by dissolving GaAs in an amount that saturates at 900 ° C. in advance. Furthermore, this Ga
Ge is added to the solution 42 so that the growth layer is doped with about 10 ¹⁹ cm ⁻³ of Ge. In addition, Ga for raw materials
The As polycrystal 43 is used to supply unsaturated GaAs during the holding time at 900 ° C. when the prepared Ga solution is slightly unsaturated. Growth solution 4
The reason why Ga is used as 2 is that Ga is one of the constituent elements of GaAs, so there is no concern that it will become an impurity when added, and that the solubility of GaAs in Ga is high, so that a thick growth layer can be easily obtained. .

After an appropriate time, the boat is slid with a quartz rod to bring the substrate 41 and the solution 42 into contact with each other as shown in FIG. 2 (b), and the temperature is lowered at a slow cooling rate of 0.13 ° C / min. , Liquid phase growth is performed. When the temperature reaches 600 ° C., the boat is slid again to separate the substrate 41 from the solution 42 and the growth is completed, as shown in FIG.

The most characteristic feature of the above-described growth method is that the GaAs substrate 41 is set above the solution 42. This is a supersaturated state of G
This is because, in the solution a, GaAs is transported to the upper side by buoyancy, so that a much thicker growth layer can be obtained than when the substrate 41 is arranged on the lower side. Through this series of processes, reproducibly thick p ⁺ Ga of about 300 μm
An As layer is obtained, which is of sufficient thickness for the subsequent device fabrication process. Of course, also for the growth of the n ⁺ layer, a thick layer can be similarly obtained only by changing the dopant used. Further, the boat is not limited to this structure, and it is possible to grow on a plurality of substrates at the same time.

Since the liquid phase growth method makes it easy to control the amount of impurities added, desired high concentration n ⁺ or p ⁺ doping can be easily performed, and the lattice matching between the substrate and the growth layer is achieved for the above-mentioned reason. Therefore, even if there is a 7-digit difference in impurity concentration such as 1 × 10 ¹² cm ^-3 and 1 × 10 ¹⁹ cm ^-3, no substrate curvature or misfit dislocation is observed, and the device fabrication process An ideal element can be realized without adversely affecting.

The spreading resistance of the high impurity concentration layer grown on the high purity substrate 41 by the method described above with reference to FIG.
As shown in FIG. 3, after polishing the substrate after growth obliquely, it is possible to perform measurement while raising two thin needles and moving the position little by little in the arrow direction. Data obtained by this measurement Is shown in the graph as shown in FIG. Simply speaking, the higher the resistance value, the lower the impurity concentration, and the lower the resistance value, the higher the impurity concentration. As is clear from FIG. 4, the resistance changes sharply near the interface, and p ⁺ −n ⁻ is very steep.
It can be seen that a bond has been formed. Moreover, the numerical value of the impurity concentration in the figure is the result of measurement by another measuring method (four-point probe method or the like).

Next, a method of evaluating the lattice matching between the high impurity concentration layer grown by the above method and the high purity substrate and the result thereof will be described. An X-ray diffractometer was used for this evaluation. If the lattice constants of the substrate and the growth layer are different by irradiating the bonded surface, which is obtained by obliquely polishing the substrate after growth, with the X-ray, the diffracted X-rays are overlapped from both layers. ,
It becomes a wide peak. Furthermore, when the lattice constant difference is large, the peaks are separated into two peaks.

The graph of FIG. 5A shows the case where the substrate before the growth is measured, and naturally one peak is observed,
The full width at half maximum is as narrow as 14.93 seconds, which shows the good crystallinity of the substrate. FIG. 5B shows p ⁺ (Ge-doped, 1 × 10
It is the measurement result of the sample having grown ¹⁹ cm ^-3 ). The result is one peak, the half-width of which is slightly wider than the case of only the 18.27 seconds substrate, but it is still sufficiently narrow and the lattice matching between the growth layer and the substrate is sufficient. Not only is it taken, but the crystallinity of the growth layer is good.

By using the above-mentioned method, an ideal GaAs device which requires an i-layer having a certain thickness can be easily manufactured. Specifically, SIT, BSIT, SI
Thyristors, pin diodes, etc. can be manufactured. SIT, BSIT, SI thyristor,
There are a buried gate type, a surface gate type, a cut gate type (trench gate type) and the like, but it goes without saying that the above method is effective for all the gate structures.

Next, the case where a GaAs pin diode is manufactured by using the present invention will be described. The pin diode is often used in Si as a high-speed and high-voltage diode, but if the pin diode is made of GaAs, its characteristics become more remarkable. See pi
The n diode is also used as a light receiving element, but
In particular, the light emission characteristic of s has a great meaning. G
n ^- layer thickness of aA spin diode is 30-50μ
When it is about m, the entire n ⁻ layer is in a very high injection state in the forward biased state of the diode, and infrared light is emitted. However, the light emitting region in this case is a normal Ga
Since it is much wider than AsLED (light emitting diode),
It is possible to obtain strong infrared rays as a whole.

Specifically, FIGS. 6A to 6E and FIG.
A pin diode is manufactured by the method shown in (a) and (b).
It was First, the high-purity GaAs substrate shown in FIG.
(N^-, (100) plane, 2 × 10¹² cm ^-3, Thickness 300
μm) 31 on top of which is used a Ga solution with Te and P added.
300 μm n⁺The layer 32 was grown (FIG. 6 (b)). This
N ⁺The carrier concentration of the layer 32 is 5 × 10¹⁸ cm ^-3And
Of course n^--N⁺So that the lattice match of the junction can be taken
The amounts of Te and P are adjusted. Then n^-GaAs substrate
31 is ground to a thickness of 50 μm and its surface is mirror-finished.
Raise n^-A GaAs layer 31a was formed (Fig. 6)
(C)).

Next, phosphorus glass PS is formed on the surface of the n ^- layer 31a.
The film PSG / Si ₃ N ₄ 33 consisting of G and silicon nitride is CV
D was deposited by the method D, and a part of it was removed by the reactive etching method (FIG. 6D). The remaining PSG / Si ₃ N
₄ 33 was subjected to Mg ion implantation as a mask p ⁺
The layer 34 was formed (FIG.6 (e)). Here, the ion implantation dose and accelerating voltage are such that the impurity concentration of the p ⁺ layer is 1 × 10 ^19.
The thickness is adjusted to be 2 μm in cm ^-3 . Here, Be, Cd, or Zn can be used instead of Mg. Also, instead of performing ion implantation, diffusion of Zn causes p
It is also possible to form a ⁺ .

Next, PSG / Si ₃ N ₄ 33 is once removed by the reactive etching method, and then Si is removed by the CVD method.
O ₂ 35 is deposited and annealed (FIG. 7A).
Next, the SiO ₂ 35 is removed and PSG / Si ₃ N ₄ 3 is added again.
6 is deposited, a part of the p ⁺ layer 34 is removed by etching, a window is opened, and AuGe 37 is vapor-deposited. Also, AuGe 38 is vapor-deposited on the entire surface of the back surface on the side of n ⁺ , and then heat treatment is performed to manufacture an electrode (FIG. 7B).

The protective films 33 and 36 of the element described here are made of P
SG / Si₃N_FourHowever, SiO ₂, Si₃N_Four, S
iO_xN_yCan also be used for annealing after ion implantation.
The protective film 35 of the₂Instead of Si₃N_Four, S
iO_xN_y, AlN, GaN can also be used
It

A pi produced by the method described with reference to FIG.
The 1 / C ² -V characteristic of the n diode shown in FIG. 8 clearly has a linear relationship, and it can be seen that the p ⁺ −n ⁻ junction is an ideal step junction.

The spectral sensitivity characteristic (light reception) of the pin diode shown in FIG. 9 has a peak at about 870 nm. Since the n ⁻ layer has a thickness of about 80 μm, the efficiency is low, but the sensitivity can be sufficiently increased if the thickness and the way of taking in the light are optimally designed.

From the light emission characteristics (light emission) of the pin diode shown in FIG. 10, it was confirmed that the pin diode emits light in the forward bias state. The area of the active region of this device is 3 × 3 mm ² , and the current (5, 1,
0, 20 mA) has a very low current density. That is,
By establishing an element formation process, reducing the leak current, and optimizing the heat dissipation structure and the light extraction structure of the element, it is possible to obtain high-luminance light emission with a high current density. Of course, this phenomenon can be applied to light emission when the SI thyristor and BSIT are conducting.

FIGS. 11A to 11C show the structures of surface gate type, buried gate type and notch gate (groove gate) type SI thyristors, respectively, and FIGS.
Shows the structure of a surface gate type, a buried gate type and a notch gate (groove gate) type BSIT (SIT), respectively.

A method of manufacturing the normally-off type SI thyristor having the trench gate structure shown in FIG.
(A)-(e), FIG. 14 (a)-(d), and FIG.
This will be described with reference to (a) to (c). First, FIG.
The plane orientation (100) shown in (a) and n ^{− with a} thickness of 300 μm
A GaAs substrate (2 × 10 ¹² cm ⁻³ ) 11 is prepared. Then, a p ⁺ GaAs layer (Ge-doped) 12 of about 300 μm is grown on the n ⁻ GaAs substrate 11 by liquid layer growth (FIG. 13B). Here, the Ge doping amount is 1 ×
It is set to 10 ¹⁹ cm ^-3 .

Next, the n ^-- GaAs substrate 11 is polished and processed into a mirror surface to form an n ^-- GaAs layer 11a having a thickness of 50 μm (FIG. 13 (c)). After that, this n ^- GaAs layer 1
1a was grown with Ga as a solvent and Te and P were simultaneously doped to grow an n ⁺ layer (1 × 10 ¹⁹ cm ⁻³ ) of about 2 μm.
3 is obtained (FIG. 13 (d)). Needless to say, the p ⁺ −n ⁻ −n ⁺ junctions obtained up to this point are all lattice-matched, and misfit dislocations and substrate curvature due to lattice strain are not seen.

Next, this n⁺By CVD on layer 13
Si₃N_FourAnd PSG (phosphorus glass) 14 are deposited.
(Fig. 13 (e)), this PSG / Si₃N_FourReact 14
Partial removal by a reactive etching method (FIG. 14).
(A)). After that, this PSG / Si ₃N_Four14 masses
The reactive etching method or ordinary solution
By the etching method^-Etching the GaAs layer 11a
Forming a groove 15 having a depth of 5 μm (FIG. 14).
(B)). Here, the width of the groove 15 is 5 μm,
The width is set to 5 μm.

Next, PSG / Si ₃ N ₄ 17 was added to 0.5.
After depositing about μm, only the bottom of the groove 15 is removed by the reactive etching method (FIG. 14C). Next, this P
Using SG / Si ₃ N ₄ 17 as a mask, Mg ions are implanted only into the bottom of the groove 15. Here, the dose amount and accelerating voltage are appropriately adjusted, and the thickness is 5 × 10 ¹⁸ cm with a thickness of about 2 μm.
^-3 p ⁺ layer 18 is formed (FIG. 14D). Then P
SG / Si ₃ N ₄ 17 is completely removed by reactive etching, SiO ₂ 19 is deposited on the entire surface by a CVD method, and annealing is performed at 700 ° C. for 15 minutes in a capped state (FIG. 15A).

Next, all of this SiO ₂ 19 is removed by reactive etching, PSG / Si ₃ N ₄ 20 is deposited again (FIG. 15B), and a part of it is removed by reactive etching to remove AuGe 21. An SI thyristor was manufactured by depositing by evaporation and taking an electrode. Of course, an electrode is also attached to the anode 22 on the back surface (FIG. 15 (c)).

The formation of n ⁺ in FIG. 13D may be performed by ion implantation of Si, S, Se, Te, Sn or the like without using the liquid layer growth. In addition, Be, Cd, Zn or the like may be used instead of Mg for the p ⁺ ion implantation of FIG. 14 (d). The thyristor manufactured as described above exhibited normally-off type characteristics as designed.

Protective films (insulating films) 14 and 17 for the above-mentioned elements
Although PSG / Si ₃ N ₄ was used as the material, SiO ₂ , S
i ₃ N _4, etc. SiO _x N _y can be used. Further, as the protective film 19 at the time of annealing after the ion implantation, Si is used.
O ₂ was used, but Si ₃ N ₄ , SiO _x N _y AlN, G
It is also possible to use aN. In addition, in the above-mentioned device, the electrodes for the cathode, anode, and gate are all AuG.
Although it was manufactured by using e, it may be n-type, that is, Ni-AuGe or Pt-AuGe may be used for the cathode portion 16, and p may be used.
Au for the mold, that is, the gate 18 and the anode portion 12
Zn or Au may be used.

As described above, the important point in manufacturing the SI thyristor is the formation of the n ^-- p ⁺ junction (FIG. 13B).
After that, the conventional technique may be used in the process of forming the element. The fabricated SI thyristor was a normally-off type (which does not conduct between the anode and the cathode unless a forward bias voltage is applied to the gate), but this is easily turned on by changing the distance between the gates. Can be obtained.

In the normally-off type thyristor, the channel must be pinched off with a zero gate bias, and the gate spacing must be made extremely narrow with the conventional n ⁻ layer purity, which is difficult to manufacture. However, according to the method described above, high purity GaAs of 10 ¹¹ to 10 ¹³ cm ^-3 is obtained.
Since the layer can be used as an active layer, pinch-off can be easily realized, and even if the gate interval is not narrowed as in the conventional case,
A normally-off type element can be realized, and there are no restrictions on the production of a normally-off type element.

Since the element manufactured as described above is of the normally-off type, it is naturally capable of optical triggering, and can also be optically quenched by being externally attached or combined with an IC-formed phototransistor. Also, near-infrared light emission has been confirmed in the ON state. Needless to say, this light emission can be obtained regardless of whether the light emission is normally off or on.

The SI thyristor having a double (twin) gate structure (a) or an anode short structure (b) shown in FIG. 16 which is considered for speeding up is also provided before the growth of the high impurity concentration layer. N ^- GaAs by ion implantation
It suffices if the n ⁺ region is formed in the substrate 11a, so that it can be easily manufactured and a higher speed device can be realized.

Next, a groove gate type B shown in FIG.
A case where the SIT is manufactured will be described. BSIT and S
There is no structural difference in IT, and the channel is pinched off in the gate zero bias state by adjusting the impurity concentration of the n ⁻ layer and the gate interval, and conduction is not provided between the source and drain unless forward bias is applied to the gate. The normally-off type SIT is called BSIT. That is, the same fabrication can be performed by only changing the impurity concentration and the gate interval of the n ⁻ GaAs substrate which also uses a normally-on type SIT in which the source and the drain are electrically connected with a gate zero bias.

Also, compare FIG. 12 (c) with FIG. 11 (c).
Then, as you can see, BSIT (SIT) and SI Siri
The star is p in the anode part⁺N⁺Just change to structural
Makes no difference. That is, BSIT is first n^-G
p on aAs substrate⁺Instead of n⁺Just grow the layers
I understand. Specifically, n^-GaAs substrate ((10
0) surface, 2 × 10¹²cm^-3 ) And then Te and
Growth was performed using a Ga solution that was simultaneously doped with P.
N with a thickness of 0 μm⁺GaAs layer (5 × 10¹⁸cm ^-3 )
Obtained. Subsequent fabrication of elements is the same as in the case of SI thyristor
The same method was used, and the device dimensions were the same. This
Even in BSIT, optical triggering is possible and at the same time,
Phototransis externally attached or integrated into an IC
Can be light-quenched by
A light emission phenomenon can also be confirmed in the ON state.

As described above, highly pure Ga of n ⁻ and p ⁻
By using As substrate 11, GaAs SIT, BSIT, SI thyristor, p
It has become possible to easily manufacture an in diode or the like.

In particular, BSIT or normally-off type SI thyristor which requires a high-purity i layer can be easily manufactured. This BSIT or normally-off type SI thyristor can turn on the element by an optical trigger, and at the same time, as shown in FIGS. 17 (a) and 17 (b), is it manufactured on the same substrate by integration? Alternatively, it can be photo-quenched by an electrostatic induction phototransistor (SIPT) connected as an external circuit, and whether or not these normally-off type elements are realized by GaAs will be a serious problem for future power devices.

P of GaAs produced as described above
The in diode, the SI thyristor (both normally-on and normally-off), and the BSIT in the high injection state emit high-intensity infrared light in the ON state.

As shown in FIGS. 18 (a) and 18 (b), GaAs, SIT, BSIT, and the anode portion (p ⁺ ) of the SI thyristor are Al having a good lattice matching with GaAs.
GaAs can be used to make the p ⁺ -n ⁻ junction a heterojunction. At this time, if the BSIT or SI thyristor is turned on by an optical trigger, this AlGaAs
Since the layer has a larger energy gap than GaAs, it functions as a window layer and plays an important role in introducing light into a channel region effective for carrier generation and extracting emitted light to the outside.

The light directly obtained when the BSIT, the pin diode, and the SI thyristor are on is infrared light, but since the light emission is strong, an appropriate rare earth phosphor (Y
_0.56 Yb _0.25 Er _0.01 OCl: Red, Y _0.84 Yb _0.15 Er
_0.01 F _{3: Green, Y 0.65 Yb 0. 35 Tm 0.001} F 3: if by coating blue) on a portion of the surface, easily visible light. As a result, actual high-speed signal processing is performed by infrared rays, and visible light can be used for the naked eye monitor such as wiring.

Further, in the SI thyristor shown in FIG. 18, the energy gap of AlGaAs is larger than that of GaAs due to the structure using the heterojunction with AlGaAs. It is possible to use a window layer effective for taking out infrared rays emitted internally or to the outside. Further, in this device, since the AlGaAs layer also emits light in the ON state, red light emission as well as infrared light can be obtained without coating the surface with a rare earth element.

As shown in FIGS. 19 (a) to 19 (c), elements such as BSIT (SIT), SI thyristor, pin diode and the like, in which p and n types are inverted, can be similarly manufactured. it can.

On the above-mentioned substrate, SIT, BSIT,
Each integrated device of the SI thyristor can be made. Similarly, BSIT, SI thyristor, optical S
It is also possible to form an IC by combining various elements such as a combination of IT and BSIT, optical SIT and SI thyristor, a bipolar transistor, or a normal FET.

SIT, BSIT, SI thyristor
As a gate p⁺(Or n ⁺) Not only
It is also possible to use a Schottky gate.

According to the embodiment described above, the G utilizing the features of the high-purity layer, i.
An aAs element such as SIT, BSIT, or SI thyristor can be easily manufactured. Regarding SIT, compared with SIT of Si of the same level, it is possible to manufacture a device having a higher breakdown voltage and a higher speed. Further, regarding BSIT, the lifetime of electrons and holes in GaAs is very short, so that it is possible to realize a high-current high-speed switching element with a very short time compared to Si, which is one of the fields in the field of power devices. It is thought to bring about a great revolution. It goes without saying that a very high speed element can be formed in the SI thyristor as well as the BSIT.

As is well known for Si, BS
The IT and SI thyristors can turn on and off the device by light, but since GaAs is a direct transition type semiconductor, both electrons and holes are highly injected into the i layer. Therefore, high-intensity infrared emission can be expected. That is, the GaAsSI thyristor can be used as a light source for other elements in its ON state.

Since the GaAsSI thyristor is capable of optical triggering and quenching, it controls the current drive of several hundreds of volts and several tens of amps with light, and the element itself sends an optical signal to another element, which is completely electrical. It becomes possible to establish a light control power system separated into two. Of course, such an element capable of optical triggering and optical quenching and emitting light in the ON state can be realized by GaAsBSIT in the high injection state.

[0072]

As described above, according to the present invention, after forming a high impurity concentration GaAs growth layer on a high purity GaAs substrate, the high purity GaAs substrate is polished to obtain a high purity GaAs layer having a predetermined thickness. Since the GaAs layer is formed, it is possible to obtain a GaAs layer having a high degree of purity and a certain thickness.
A device can be formed on the aAs layer to manufacture a GaAs device having a high-purity layer.

[0073] Further, n ^- or ^p - after the formation of the p ⁺ or n ⁺ GaAs growth layer on a GaAs substrate n ^- or ^p - of polishing the GaAs substrate predetermined thickness n ^- or ^p - GaAs layer Form this n ^- or p ^- G
By forming an n ⁺ or p ⁺ layer on the aAs layer, a GaAs device having a high purity layer having a pin structure can be manufactured.

Further, since the high impurity concentration GaAs growth layer is formed by the liquid phase growth method, in particular, the high-purity GaAs substrate is placed on the upper side of the solution in which GaAs is dissolved, the thick growth layer is efficiently formed in a short time. Can be formed.

Furthermore, as the impurities of the high impurity concentration GaAs growth layer, the one having the average value of the covalent bond radius of the single substance or the combined covalent bond radius of the combination is substantially equal to the average value of the covalent bond radius of Ga and As is used. Therefore, even if there is a large difference in impurity concentration between the high impurity concentration GaAs growth layer and the high purity GaAs layer, a GaAs element having a high purity layer can be manufactured without causing lattice mismatch.

[Brief description of drawings]

FIG. 1 is a diagram showing a principle example of a method for manufacturing a GaAs device having a high-purity layer according to the present invention.

FIG. 2 is a diagram showing a specific method for growing a high-impurity layer on a high-purity substrate using a growth carbon boat.

FIG. 3 is a diagram showing a method for measuring the spread resistance of a cross section of a Ge-doped phase.

FIG. 4 is a graph showing the results of measuring the spread resistance of a cross section of a Ge-doped layer.

FIG. 5 is a diagram showing a rocking curve for explaining a lattice compensation result by Ge doping.

FIG. 6 is a diagram showing a part of the steps of the method for manufacturing a pinGaAs diode according to the method of the present invention.

FIG. 7 is a diagram showing another part of the process of the method for manufacturing a pinGaAs diode according to the method of the present invention.

FIG. 8 is a graph showing CV characteristics of a pin diode.

FIG. 9 is a graph showing a spectral sensitivity characteristic of a pin diode.

FIG. 10 is a graph showing a light emitting characteristic of a pin diode.

FIG. 11 is a diagram showing various structures of an SI thyristor which is a GaAs device having a high-purity layer.

FIG. 12 is a BSI that is a GaAs device having a high-purity layer.
It is a figure which shows various structures of T (SIT).

FIG. 13: Groove gate type GaAsSI by the method of the present invention
It is a figure which shows a part of process of the manufacturing method of a thyristor.

FIG. 14: Groove gate type GaAsSI by the method of the present invention
It is a figure which shows another part of the process of the manufacturing method of a thyristor.

FIG. 15: Groove gate type GaAsSI by the method of the present invention
It is a figure which shows another part of the process of the manufacturing method of a thyristor.

FIG. 16 is a diagram showing an SI thyristor structure for speeding up.

FIG. 17 is a circuit diagram showing an example of an optical trigger and an optical quench SI thyristor.

FIG. 18 is a diagram showing a structural example of an SI thyristor using AlGaAs as an anode.

FIG. 19 is a diagram showing an example of type inversion of each element.

FIG. 20 is a diagram showing an example of a conventional method for manufacturing a GaAs device having a high-purity layer.

FIG. 21 is a diagram for explaining a problem of the device manufactured by the conventional method shown in FIG. 16.

[Explanation of symbols]

1,11,31 High purity GaAs substrate (n ⁻ or p ⁻ GaAs substrate) 1a, 11a, 31a High purity GaAs layer (n ⁻ or p ⁻ GaAs layer) 2, 12, 32 High impurity concentration GaAs growth layer (p ⁺ Or n ⁺ GaAs growth layer)

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Tokuzo Sukegawa             266 Nazuka-cho, Hamamatsu City, Shizuoka Prefecture             Tsuka House 1-51 (72) Inventor Masakazu Kimura             Shizuoka Iwata Campus 4154 Mitsuke, Iwata City, Shizuoka Prefecture             No. 25

Claims (5)

[Claims] 1. A high-purity GaAs substrate is prepared, a GaAs growth layer having a high impurity concentration is formed on the high-purity GaAs substrate, and the high-purity GaAs substrate is polished to form a high-purity GaAs layer having a predetermined thickness. A method of manufacturing a GaAs device having a high-purity layer, which comprises forming the device and then forming the device on the high-purity GaAs layer. 2. An n ⁻ or p ⁻ GaAs substrate is prepared, a p ⁺ or n ⁺ GaAs growth layer is formed on the n ⁻ or p ⁻ high-purity GaAs substrate, and the n ⁻ or p ⁻ GaAs substrate is polished. To form an n ⁻ or p ⁻ GaAs layer having a predetermined thickness, and thereafter, n ⁺ or p layer is formed on the n ⁻ or p ⁻ GaAs layer.
^A method of manufacturing a GaAs device having a high-purity layer, which comprises forming a ⁺ layer to form a device having a pin, nin, pip, and nip structure. 3. The method of manufacturing a GaAs device having a high-purity layer according to claim 1, wherein the GaAs growth layer is formed by a liquid phase epitaxy method. 4. The formation of the GaAs growth layer by the liquid phase growth method is carried out by applying the Ga to the upper side of a solution in which GaAs is dissolved.
The method of manufacturing a GaAs device having a high-purity layer according to claim 3, wherein the As substrate is placed on the substrate. 5. The impurity of the GaAs growth layer is such that the average value of the covalent bond radii of a single substance or the combination thereof is approximately equal to the average value of the covalent bond radii of Ga and As. A method of manufacturing a GaAs device having a high-purity layer according to any one of claims 1 to 4.