RU2297690C1 - Method for manufacturing superconductor heterostructure around a3b5 compounds by way of liquid-phase epitaxy - Google Patents

Abstract

FIELD: methods for manufacturing heterostructure around A³B⁵ compounds by way of epitaxy.

SUBSTANCE: proposed method for manufacturing semiconductor heterostructure by way of epitaxy includes growth of epitaxial layer of desired thickness h₀ mismatched over lattice perimeter with material whereon it is grown; prior to do so, experimental calibration curve is constructed for given growth system showing maximal layer thickness h_max at which its epitaxial growth still takes place as function of relative mismatch f between lattices at known mechanical strength of layer specified by Poisson's ratio, design calibration curve of minimal layer thickness h_min as function of lattice relative mismatch f at known mechanical strength of layer specified by Poisson's ratio is constructed, and relative lattice mismatch f of materials being joined at which h₀ meets expression h_min < h₀ < h_max, μm is chosen.

EFFECT: ability of generating sufficient number of effective recombination centers in base layers of device.

13 cl, 2 tbl

Description

The invention relates to pulsed and high-frequency microelectronic technology, and more particularly to methods for manufacturing semiconductor structures from compounds A ³ B ⁵ , as well as from compounds A ² B ⁶ , A ⁴ B ⁴ and A ⁴ B ⁶ by epitaxy methods.

In many types of semiconductor devices, and especially in devices of powerful pulsed and high-frequency technology, to increase their speed, it is necessary to reduce the lifetime of nonequilibrium charge carriers (NEC) in the base layers of the device without loss of operating voltages (switching voltage in thyristors and reverse operating voltage in diodes) and noticeable growth of direct falls. For these purposes, in the lightly doped parts of the instrument structure, efficient recombination centers are created in various ways.

First of all, effective recombination centers are created by doping semiconductors with impurities responsible for the appearance of effective recombination centers during crystal growth or by the diffusion method, for example, when doping germanium with gold, as well as silicon with gold or platinum.

Another way is the generation of intrinsic point defects and dislocations in layers by, for example, implantation of electrons, protons, ions, etc.

In the manufacture of devices based on binary semiconductors, the use of these processes is difficult due to the difficulties of obtaining a relatively pure bulk (substrate) material suitable for power engineering, which determines the predominant use of epitaxial growing methods. In addition, in the epitaxial layers of undoped material based on compounds A ³ B ⁵ and other multicomponent semiconductor compounds, the appearance of deep-level traps is usually associated with intrinsic defects. Therefore, in the fabrication of structures of high-speed devices based on undoped layers of multicomponent semiconductor compounds, it seems appropriate to use the properties and features of the formation of intrinsic point and linear defects in these epitaxial layers.

One way to change the ensemble of intrinsic defects in epitaxial films is isovalent doping (see, e.g., VVChaldyshev and SV Novikov. Isovalent impurity doping of direct-gap III-V semiconductor layers. In: Semiconductor technology: Processing and novel fabrication techniques. Ed . by M. Levinshtein and M. Shur. John Wiley & Sons, Inc., 1997, p. 165-194).

With a gradual increase in the content of isovalent impurities in the layers, the crystal perfection of the epitaxial films first improves and, as a rule, the content of electrically active deep-level centers in them improves. Then, as the concentration of the isovalent component in the elastically deformed layers increases, a gradual increase in the concentration and the appearance of new electrically active deep-level defects are observed. With a further increase in the mismatch in the lattice parameter of the layer and the substrate and the achievement of the so-called critical stresses, partial relaxation of the elastic stresses occurs with the formation of misfit dislocations (MDs). For some even larger values of the mismatch, intense plastic deformation of the solid solution layer occurs, while the residual internal stresses reach their maximum values, and the density of the disks increases sharply; in this case, as a rule, partial or complete destruction of the semiconductor material layer occurs.

The appearance of MDs in the layers usually stimulates the generation of additional defects and, accordingly, deep-level traps. In addition, such excess (additional) defects as MDs can have the properties of traps for charge carriers. In this way, one can change the lifetimes of charge carriers in semiconductor layers and, accordingly, the speed of devices based on them.

This approach to the manufacture of the heteroepitaxial structures described below is universal and applicable in various heterosystems, not only based on compounds A ³ B ⁵ , but also A ² B ⁶ , A ⁴ B ⁴ or A ⁴ B ⁶ . In addition, this method is applicable regardless of the method of epitaxial growth, which is selected depending on the requirements of specific instrument applications.

Known and widely used epitaxial methods for producing single crystal layers for the manufacture of various semiconductor devices. The main distribution was gas phase epitaxy (HFE), gas phase epitaxy from organometallic compounds (MOS hydride method), molecular beam (MPE), and liquid phase epitaxy (LPE).

The MOS hydride method and the MPE method allow thin layers to be deposited with high accuracy, which is used for the manufacture of low-voltage high-frequency devices (up to ~ 20 V). The growth rate of the layers in these methods is quite low, therefore, for growing layers of more than 1 μm, large process times are required, which, in addition, increases the cost of the process.

For power engineering devices, rather long layers with a low impurity concentration and high carrier mobility are required. The HPE and HFE methods (chloride method) are suitable for these purposes, but the HFE method gives insufficiently reproducible results (especially for layer thicknesses). The LPE method attracts with the extremely low cost of the process, the simplicity of equipment and the ability to grow multicomponent compounds.

The main material for high-speed semiconductor electronics is still silicon. Recently, the world's leading manufacturers of silicon devices have begun to use alternative semiconductor materials more often, since silicon as a material no longer fully meets all the requirements for devices operating at high frequencies, including high switching speed, low forward voltage drop, and the ability to work with high temperatures, as well as radiation resistance. Therefore, there was a logical interest in other materials, wider-gap, such as GaAs, SiC, diamond, etc.

A known method of producing smooth GaAs high-voltage pin junctions by liquid phase epitaxy (see US patent No. 5733815, IPC H01L 21/20, published March 31, 1998), including heating the initial charge to form a saturated solution-melt of its components, interaction of the solution-melt with a gas mixture, including hydrogen, water vapor and the reaction products between hydrogen and water vapor with a melt solution and silicon dioxide, filling the gallium arsenide substrate with the obtained melt solution and their subsequent forced cooling to dissolve schivaniya epitaxial layer GaAs.

In the known method, due to the controlled introduction of water vapor into the growth chamber during the process of growing the epitaxial structure, it was possible to reduce the effective carrier lifetimes for GaAs p-i-n diode structures to 15-60 ns; the diode off time was 30-70 ns, which, we note, is currently comparable to the shutdown parameters of the best silicon diode rectifiers at room temperature. Thus, this known method allows the creation of high-voltage GaAs structures, but does not provide for the manufacture of diodes based on them, significantly superior in speed to the best silicon analogues. This may be due to the fact that with this known method of manufacturing GaAs p-i-n diode structures, the number of additional recombination centers created with their properties (capture cross sections of the main and minor carriers of activation energy) is not enough to further increase the performance of the diodes.

In the work (L.S.Berman, V.G.Danilchenko, V.I. Korolkov, F.Yu.Soldatenkov. - Deep-level centers in undoped p-GaAs layers grown by liquid-phase epitaxy. - FTP, 2000, v. 34 5, pp. 558-561), another method was used to increase the performance of devices based on lightly doped GaAs. It has been shown that, as a result of replacing hydrogen with argon during the growth process, the spectrum of deep-level traps in the layers of lightly doped GaAs responsible for the recombination of low-temperature nanocrystals changes due to a change in the ensemble of intrinsic point defects in the epitaxial layers, namely, the appearance of an EL2 defect with large cross sections the capture of charge carriers, which leads to a sharp decrease in the effective lifetime of the NSC (from 200-250 ns to 25-30 ns). Despite a significant decrease in the lifetime of NNZ in GaAs layers obtained in a known manner, this method does not provide the manufacture of sufficiently high-speed devices.

A known method of controlling the speed of GaAs devices by irradiation with gamma rays (V.G. Danilchenko, V.I. Korolkov, Yu.N. Luzin, S.I. Ponomarev, A.V. Rozhkov, G.I. Tsvilev. - The use of γ-ray irradiation to control the speed of high-voltage gallium arsenide devices. - Electronic Technology. Ser. Electrovacuum and gas-discharge devices, 1981, issue 5 (88), pp. 30-32). In the known method, as a result of irradiation with Co ⁶⁰ gamma rays, radiation defects occur that shorten the lifetime of the NCD, which reduced the recovery times of high-voltage GaAs diodes from 200-250 ns to 40-50 ns, which is not a satisfactory value at present. In addition, a significant increase in direct voltage drops with increasing radiation dose can be attributed to the disadvantages.

A known method of manufacturing high-speed power GaAs diodes with a Schottky barrier (see US patent No. 5622877, IPC H01L 21/265, published 04/22/1997), comprising the manufacture of a GaAs layer with a donor concentration of less than 5 · 10 ¹⁵ cm ^-3 thickness of more than 3 μm on heavily doped GaAs, with a donor concentration of more than 1 · 10 ¹⁸ cm ^-3 , chemical deposition on the specified layer of the barrier electrode in the form of an epitaxial nickel layer with a thickness of 0.05 to 0.5 μm, the deposition of a conductive metal layer on the specified barrier electrode and the formation of an ohmic contact on strongweed doped with GaAs.

Schottky diodes have well-known advantages in comparison with pn and p-i-n diodes: direct voltage drops at Schottky barriers are much smaller than at pn junctions, and can reach values of 0.5-0.6 V at high current densities; in addition, carrier transfer through the Schottky barrier is carried out by the main charge carriers, excluding the relatively slow processes of injection and recombination of minority charge carriers, which allows faster switching of devices. The main disadvantage of Schottky diodes is their high leakage currents at reverse bias compared to pn junctions, which makes rectification ineffective under certain conditions, especially at elevated temperatures. In addition, the maximum blocking voltage of the Schottky GaAs barriers does not exceed 150 V. Given the above disadvantages, GaAs Schottky diodes manufactured by the known method, which have the following parameters, are currently the best in speed in the class of high-voltage power diodes (http: // www. ixysrf.com/pdf/briefs/250vGaAsDiodeBrief.pdf): off time - about 15 ns; direct currents ~ 5 A; leakage currents with reverse bias - up to 1.5 mA. Currently, even faster devices of this class are required.

The objective of the invention was the development of such a method of manufacturing a semiconductor heterostructure by liquid phase epitaxy, which would ensure the generation of a sufficient number of effective recombination centers in the base layers of the device, reproducible to obtain semiconductor devices with short shutdown times for pulsed and high-frequency electronic equipment.

The problem is solved in that the method of manufacturing a semiconductor heterostructure by epitaxy involves growing an epitaxial layer of a given thickness h ₀ , mismatched according to the lattice parameter with the material on which the said layer is grown, while an experimental calibration curve for the maximum layer thickness is preliminarily constructed for this growth system h _max, at which it has the epitaxial growth occurs, the magnitude of the relative misalignment of lattices at f estno mechanical strength of the layer defined by the Poisson's ratio ν, construct a calibration curve calculated minimum thickness h _min layer from the relative misalignment of lattices f is known and the mechanical strength of the layer defined by the Poisson's ratio ν, by the expression:

where b is the module of the Burgers vector, microns;

ν - Poisson's ratio for the grown layer;

f = (a ₁ -a ₂ ) / a ₂ - relative mismatch of the gratings;

a ₁ and a ₂ are the lattice parameters of the mating materials of the heterostructure;

and for a given thickness h _{0 of the} grown layer, choose a relative mismatch of the lattices of the mating materials f, in which h ₀ satisfies the expression:

h _min <h ₀ <h _max , μm.

As a result, the inventive method grows such an instrument heteroepitaxial structure in which the thickness h ₀ and the lattice parameter of the layer are correlated in such a way that critical stresses are exceeded due to the mismatch of the lattice constants of the layer and the substrate on which growth occurs, leading to the onset of plastic deformation of this elastically deformed layer. In this case, the stresses in the structure do not reach critical shear stresses leading to intense plastic deformation and, accordingly, to non-epitaxial, non-monocrystalline growth or mechanical destruction of this layer.

The basis of the proposed method is a relatively simple technique for reducing the effective lifetime of NNZ by controlled creation of additional intrinsic defects in the base layers of semiconductor devices that arise due to a mismatch in the lattice parameter of the mating materials from which the heterostructures are made. This is solved by controlling the magnitude of the mismatch in the lattice parameter of the heterocomposition and the thickness of the heteroepitaxial layer. The simplest case of such a heterostructure is an epitaxial layer of a binary compound-based solid solution with isovalent substitution of one of the components grown on the substrate of this binary compound. For this case, the calculation of h _{min is} simplified, since the expressions for the relative mismatch f and the Poisson's ratio ν become simple linear functions of x (f = x · (and _{AC-a BC} ) / a _BC and ν = ν _BC + x · (ν _AB -ν _BC ) for connecting the solid solution A _x B _1-x C). Therefore, the dependence for h _min can be expressed in terms of the composition of the solid solution x.

The growth of the epitaxial layer of the claimed method can be carried out by liquid-phase epitaxy, in which the growth of the epitaxial layer is carried out by heating the initial mixture to form a saturated solution-melt of its components, the interaction of the solution-melt with a gas mixture comprising hydrogen, water vapor and reaction products between hydrogen and water vapor with the aforementioned molten solution and with silicon dioxide, filling the surface of at least one substrate with the obtained molten solution with their eduyuschim forced cooling to room temperature. The cultivation of the layer can be carried out in a drain-type cartridge made, for example, of quartz.

The growth of the epitaxial layer of the claimed method can be carried out by liquid-phase epitaxy in a graphite cartridge, for example, a piston type, in which the epitaxial layer is grown by heating the initial charge to form a saturated solution-melt of its components (including the addition of one or more rare-earth elements in an amount of not more than 0.1 at.%), Annealing the melt solution, creating supersaturation by forced cooling of the melt solution, filling the surface under ozhki resulting solution followed by melt-forced cooling to a selected temperature at which terminates growth of the layer or layer from the melt sdergivaniem or by substitution of other melt.

The growth of the epitaxial layer of the claimed method can also be carried out by the method of molecular beam epitaxy, or by the method of gas-phase epitaxy, or other method of epitaxial growth.

The epitaxial layer can be grown on single-crystal GaAs in the form of a triple compound A ³ _x Ga _1-x As, where A ³ is an element of the 3rd group of the periodic system of elements, or a triple compound In _x Ga _1-x As, or as a triple compound GaAs _1-x B ⁵ _x , where B ⁵ is an element of the 5th group of the periodic system of elements, either as a ternary compound GaAs _1-x Sb _x , or as a quaternary compound A ³ _x Ga _1-x As _1-y B ⁵ _y .

A heteroepitaxial layer of a GaAs solid solution can be grown on a p-type GaAs substrate doped with Zn to a concentration of (1-5) 10 ¹⁸ cm ^-3 , or on an n-type GaAs substrate doped with Sn or Si to a concentration (0, 5-5.0) • 10 ¹⁸ cm ^-3 , either on a semi-insulating GaAs substrate doped with Cr or undoped, or on a p-type or n-type buffer layer, for example, GaAs or its solid solution grown on a GaAs substrate.

The fabrication of the instrument structure can be carried out either by building up one or more doped epitaxial layers on the described lightly doped epitaxial layer, or by creating a Schottky barrier on it.

Currently, the best in speed and a combination of other device characteristics are devices made from GaAs. Therefore, the proposed method was tested on the example of heteroepitaxial systems based on GaAs solid solutions and high-voltage devices based on them, such as diodes and optothyristors.

Example 1. Received diode pin structure based on a heteroepitaxial layer In _x Ga _1-x As grown on a GaAs substrate by HPE.

For diodes with a breakdown voltage of 300-500 V, layers of lightly doped material with a thickness of about 50 μm are required (according to the current production method used). According to the previously constructed calibration curves (according to the above formula for h _min , ah _max for this system, it was determined as h _max ~ 9.66 + 777 · exp (-1303 · f), the range of suitable values of the mismatch of the f layer and the substrate was determined from ~ 7.2 · 10 ^-4 to 2.2 · 10 ^-3 . Then, the composition of the solid solution layer x was determined by the relative mismatch f and the composition of the liquid phase (melt solution) was determined from the known thermodynamic relations at the temperature of onset of crystallization for the selected composition of the solid phase x (see M. B. Panish, M.Ilegems. Phase equilibria ternary systems III-V. In the collection of articles "Materials for Optoelectronics." - M .: Mir, 1976, pp. 39-92; or V.M. Andreev, L. M. Dolginov, D. N. Tretyakov. epitaxy in the technology of semiconductor devices. Edited by J.I. Alferov. - M .: Sovetskoye Radio, 1975, 328 pp.) The mismatch value f = 1.8 · 10 ^-3 (x = 0.025) was chosen. a solution of In _x Ga _1-x As with x = 0.025 50 μm thick at a given crystallization onset temperature of 900 ° C, a gap between the substrates of 0.45 mm was chosen.

In a quartz reactor in a quartz cassette of a drain type in a hydrogen atmosphere with a dew point of about -70 ° C, a preliminary two-stage annealing of the melt solution was carried out - 15 hours at a temperature of 700 ° C and 3 hours at a temperature of the onset of crystallization of the layer (900 ° C) and a stream of hydrogen through a reactor of 130 ml / min, after which this melt solution was brought into contact with GaAs p ⁺ -type substrates and crystallization of the epitaxial layer having a pin structure began by forced cooling of the growth system at a rate of about 0.5 ° C / min to room temperature ratra.

From the obtained epitaxial structures with InGaAs layers, diodes were made using standard methods of photolithography, etching, sputtering, and contact burning. The characteristics of the devices were measured in continuous and pulsed modes at room temperature (20 ° C). The parameters of the diode, including InGaAs p-i-n structure, are shown in table 1 (batch number 1).

Example 2. For comparison with p-i-n structures obtained by the proposed method (example 1), p-i-n structures were prepared in which the thickness of the epitaxial layer h and the relative mismatch f were outside the range proposed in this method.

The structures of the same thickness were grown in the same way as in Example 1, but instead of the In _x Ga _1-x As layer with the selected relative mismatch f, GaAs and In _x Ga _1-x As layers were grown on GaAs substrates, for which the value f out of the range proposed in this method. To obtain a GaAs layer with a thickness of 50 μm and a crystallization onset temperature of 900 ° C, a gap of 0.8 mm was chosen, and to obtain an In _x Ga _1-x As layer with x = 0.009 (f = 6.45 · 10 ^-4 ) 50 μm thick at the same temperature the onset of crystallization selected a gap of 0.6 mm

From the obtained epitaxial structures, diodes were made in the same way as in Example 1. Measurement of the characteristics of the devices was carried out in the same way as in Example 1. The parameters of the diode, which includes a GaAs or In _x Ga _1-x As pin structure, are shown in Table 1, batch No. 2 and 3):

Table 1 Party number U _R , U _F I _DC I _R , τ _rr (f, rel.) AT AT A mA ns 1 (1.8 · 10 ^-3 ) 250-450 1.5 (at 0.1 A) ≥10 0.1 5-10 2.5 (at 0.5 A) 2 (6.45 · 10 ^-4 ) 450-580 1.5 (at 0.1 A) ≥10 0.1 350-450 2.2 (at 0.5 A) 3 (-) 400-530 1.4 (at 0.1 A) ≥10 0.1 430-540 2.0 (at 0.5 A)

Where:

U _R - maximum voltage reverse bias (reverse bias); U _F - forward bias voltage (forward bias); I _DC - direct current (direct current); I _R - leakage currents at reverse bias (leakage current); τ _rr - diode off time (reverse recovery time).

As can be seen from the data given in the table, the use of the claimed method for the manufacture of epitaxial structures can significantly improve the speed of existing devices (samples of batches 1 compared to 2); high-voltage p-i-n diodes (batch 1) were obtained, superior in speed to the best silicon p-i-n diodes, silicon carbide diodes, and GaAs with a Schottky barrier, which are the best in speed (and a combination of other characteristics) of high-voltage rectifier diodes in the world.

In adjacent cells of a quartz cassette, several epitaxial structures can be grown simultaneously, including epitaxial layers In _x Ga _1-x As or GaAs _1-x Sb _x , which differ in composition x and thickness.

Example 3. Diode structures were prepared based on a lightly doped GaAs _1-x Sb _x heteroepitaxial layer grown on a GaAs substrate by the HPE method in a piston-type graphite cartridge.

For diodes with a breakdown voltage of 50-250 V, layers of lightly doped material (according to the used production method) with a thickness of about 20 μm are required. Using pre-constructed calibration curves (using the formulas for h _min and h _max ), we determined the range of suitable values of the mismatch f of the layer and substrate — from 1 · 10 ^-3 to 3.7 · 10 ^-3 . The mismatch value was chosen f = 1.3 · 10 ^-3 . After determining the composition of the solid phase x corresponding to the mismatch value, the composition of the liquid phase (melt solution) at the crystallization temperature for the selected composition of the solid phase x was determined from the known thermodynamic relations (see references in Example 1). When using a piston cartridge with a growth gap of 1 mm, a growing temperature range from 750 ° C to 700 ° C was chosen to obtain a GaAs _1-x Sb _x layer with a thickness of about 20 μm. A Sc sample of 0.01 at.% Was added to the charge.

In a quartz reactor in a piston-type graphite cartridge in a hydrogen atmosphere with a dew point of about -70 ° C, a preliminary annealing of the saturated melt solution was carried out for 2 hours at the temperature of the onset of crystallization of the layer (750 ° C), the melt solution was cooled by 5 ° C, after why this melt solution was brought into contact with an n-type GaAs substrate and the crystallization of a lightly doped n-type GaAs epitaxial layer began crystallization by forced cooling of the growth system at a rate of about 0.5 ° C / min to a temperature of 700 ° C, at which whether the layer grew by replacing this melt with another (the next one containing Ga, As, and Ge), i.e., starting to grow another layer in composition, namely, a heavily doped p-type GaAs layer of conductivity. Thus, a diode n ⁺ -n ⁰ -p ⁺ structure was obtained in a single epitaxial process.

From the obtained epitaxial structures with GaAsSb layers with a concentration of free electrons in a lightly doped layer of about 2 × 10 ¹⁵ cm ^-3 , diodes were made in the same way as in Example 1. The characteristics of the devices were measured in the same way as in Example 1. The parameters of the diode with the base a GaAsSb layer are shown in Table 2 (lot No. 1).

Example 4. For comparison with the diode structures obtained by the proposed method (example 3), diode structures were made in which the thickness of the epitaxial layer h and the relative mismatch f were outside the range proposed in this method.

The structures of the same thickness were grown in the same way as in Example 3, but instead of a GaAs _1-x Sb _x layer with a selected value of relative mismatch f, GaAs substrates were grown for which the value of f was outside the range proposed in this method, namely the layers GaAs.

From the obtained epitaxial structures with GaAs layers with a concentration of free electrons in a lightly doped layer of about 2 × 10 ¹⁵ cm ^-3 , diodes were made according to the same scheme as in Example 1. The characteristics of the devices were measured in the same way as in Example 1. The parameters of the diode, including GaAs n ⁺ -n ⁰ -p ⁺ structure, are shown in table 2 (batch No. 2):

table 2 Party number U _R , U _F I _DC I _R , τ _rr (f, rel.) AT AT BUT mA NA 1 (1.3 · 10 ^-3 ) 50-80 1.5 (at 0.1 A) ≥5 0.1 5-10 2.0 (at 0.5 A) 2 (-) 50-80 1.3 (at 0.1 A) ≥5 0.1 300 1.8 (at 0.5 A)

Where:

U _R - maximum voltage reverse bias (reverse bias); U _F - forward bias voltage (forward bias); I _DC - direct current (direct current); I _R - leakage currents at reverse bias (leakage current); τ _rr - diode off time (reverse recovery time).

As can be seen from the data given in the table, the use of the claimed method for the manufacture of epitaxial structures can significantly improve the performance of existing devices (samples of party 1 compared to 2).

Lightly doped GaAs _1-x Sb _x or In _x Ga _1-x As layers, different in composition and thickness, of n- or p-type conductivity, can be grown on n ⁺ or p ⁺ -type GaAs substrates, or on semi-insulating substrates , in various combinations depending on instrument applications.

There is the possibility of further improving the performance of devices based on these layers, making Schottky barriers.

Claims (13)

1. A method of manufacturing a semiconductor heterostructure based on compounds A ³ B ⁵ by the method of liquid phase epitaxy by growing an epitaxial layer of a given thickness h ₀ , mismatched according to the lattice parameter with the material on which the said layer is grown, characterized in that an experimental experiment is built for this growth system calibration curve - of the maximum thickness h _max layer, which has its epitaxial growth occurs, the magnitude of the relative error in D etok f, construct a calibration curve calculated minimum thickness h _min layer from the relative misalignment of lattices f by the expression

where b is the module of the Burgers vector, microns; ν - Poisson's ratio for the grown layer; f = (a ₁ -a ₂ ) / a ₂ - relative mismatch of the gratings; a ₁ and a ₂ are the lattice parameters of the mating materials of the heterostructure, and for a given thickness h _{0 of the} grown layer, a relative mismatch of the lattices of the mating materials f is chosen at which h ₀ satisfies the expression h _min <h ₀ <h _max , μm. 2. The method according to claim 1, characterized in that the growth of the mentioned epitaxial layer is carried out by heating the initial mixture to form a saturated solution of the melt of its components, the interaction of the solution of the melt with a gas mixture comprising hydrogen, water vapor and reaction products between hydrogen and vapor water with the aforementioned melt solution and silicon dioxide, filling the surface of at least one substrate with the obtained melt solution, followed by forced cooling to room temperature. 3. The method according to claim 2, characterized in that said epitaxial layer is grown in a drain type cartridge. 4. The method according to claim 3, characterized in that the cultivation is carried out in the aforementioned drain type cassette made of quartz. 5. The method according to claim 1, characterized in that said epitaxial layer is grown in a piston-type graphite cartridge. 6. The method according to claim 5, characterized in that the growth of the said epitaxial layer is carried out by heating to the formation of a saturated solution-melt of its components of the initial charge, comprising at least one rare-earth element in an amount of not more than 0.1 at.%, Annealing the resulting solution -melt, creating supersaturation by cooling the saturated solution-melt, filling the surface of the substrate with the obtained solution-melt, followed by forced cooling to the temperature of termination of growth of the epitaxial layer sdergivaniya by the melt from the surface of said epitaxial layer or by substitution of the molten solution with the following solution-melt. 7. The method according to claim 1, characterized in that the said epitaxial layer is grown on a substrate of single-crystal GaAs in the form of a ternary compound A ³ _x Ga _1-x As, where A ³ is an element of the 3rd group of the Periodic system of elements; x is the composition of the solid solution. 8. The method according to claim 1, characterized in that the said epitaxial layer is grown in the form of a ternary compound In _x Ga _1-x As. 9. The method according to claim 1, characterized in that said epitaxial layer is grown on a single-crystal GaAs substrate in the form of a GaAs _1-x B ⁵ _x ternary compound, where B ⁵ is an element of the 5th group of the Periodic Table of the Elements. 10. The method according to claim 9, characterized in that the said epitaxial layer is grown in the form of a ternary compound GaAs _1-x Sb _x . 11. The method according to claim 1, characterized in that said epitaxial layer is grown on a p-type GaAs substrate doped with Zn to a concentration of (1-5) · 10 ¹⁸ cm ^-3 . 12. The method according to claim 1, characterized in that said epitaxial layer is grown on an n-type GaAs substrate doped with Sn or Si to a concentration of (0.5-5.0) • 10 ¹⁸ cm ^-3 . 13. The method according to claim 1, characterized in that the said epitaxial layer is grown on a semi-insulating GaAs substrate, undoped or doped with Cr.