JP2006080341A - Nitride semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nitride semiconductor device for realizing element separation with a planar structure and a high resistance, and to provide a method for manufacturing the nitride semiconductor device. <P>SOLUTION: This nitride semiconductor device is constituted by laminating a first nitride semiconductor layer and a second nitride semiconductor layer constituted of a group III-V nitride semiconductor layer on a substrate, and an element separation region is packed with a third nitride semiconductor layer constituted of a group III-V nitride semiconductor layer with a microcrystal structure grown in a low temperature. A recess is formed in the element separation region, and then the third semiconductor is selectively regrown. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a nitride semiconductor device using a nitride semiconductor in an active layer and a method for manufacturing the same, and more particularly to a nitride semiconductor device that can perform planar element isolation and a method for manufacturing the same.

  3A is a plan view of a nitride semiconductor device made of a conventional III-V nitride semiconductor, and FIG. 3B is a cross-sectional view (a cross-sectional view of the AA ′ plane in FIG. 3A is shown in FIG. FIG. 3c shows a cross-sectional view of the plane −B ′. The nitride semiconductor device shown in FIG. 3 has a so-called HEMT structure. On the SiC substrate 11, a buffer layer 12 made of aluminum nitride (AlN), a channel layer 13 made of gallium nitride, and a spacer made of non-doped aluminum gallium nitride. A layer 14, a carrier supply layer 15 made of n-type aluminum gallium nitride (AlGaN), and a Schottky layer 16 made of non-doped aluminum gallium nitride (AlGaN) are sequentially stacked. The channel layer 13 and the spacer layer 14 Near the heterojunction interface, a two-dimensional electron gas layer consisting of a potential well and having extremely high electron mobility is formed. In the nitride semiconductor device having such a structure, by controlling the voltage applied to the gate electrode 21 (control electrode) in Schottky contact with the Schottky layer 16, carriers flowing between the source electrode 20a and the drain electrode 20b (2 Dimensional electron gas).

  Such element isolation of the nitride semiconductor device is performed by removing a semiconductor layer in a region partitioning the nitride semiconductor device formation region by a dry etching method to form a recess 18 (FIGS. 3a and 3b). In such a structure, the gate electrode 21 crosses the step of the recess 18 and the lead portion such as a pad is formed on the bottom surface of the recess 18 (FIG. 3c). The element isolation method having the structure in which the recess 18 is formed in this way is called a mesa structure, and is a method conventionally used in the manufacturing process of this type of semiconductor device.

Further, instead of etching, for example, nitrogen ions are accelerated at 20 keV, 100 keV, and the dose amount is 1 × 10 ¹⁴ cm ⁻² , so that the sheet resistance is 1 × 10 ⁸ Ω / □. A method of isolating a planar structure by forming the element isolation region is reported (Non-Patent Document 1).
Nakayama et al., “High Voltage / High Output AlGaN / GaN Recessed Gate FET with Field Plate”, IEICE Technical Report, IEICE, January 12, 2004, Vol. 103, no. 558, p. 57-62

  In such a conventional mesa element isolation, when the gate electrode (control electrode) is formed by the lift-off method, it is necessary to form a photoresist having a film thickness that is at least equal to the level difference of the concave portion 18. There was a problem that could not be formed.

  Further, in the element isolation of the planar structure reported so far, it is necessary to form an element isolation region having a large sheet resistance in order to further reduce the leakage current of the gate electrode.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a nitride semiconductor device that solves the above problems and has a planar structure and enables high-resistance element isolation, and a method for manufacturing the same.

  In order to achieve the above object, the invention according to claim 1 of the present application provides at least one group III element consisting of at least one of the group consisting of gallium, aluminum, boron and indium, and at least one of the group consisting of nitrogen, phosphorus and arsenic. In a nitride semiconductor device including a group III-V nitride semiconductor layer composed of a group V element containing nitrogen, a first nitride semiconductor layer including the group III-V nitride semiconductor layer stacked on a substrate; A second nitride semiconductor layer made of the group III-V nitride semiconductor layer stacked on the first nitride semiconductor layer, and at least the second nitride semiconductor layer and the first nitride. Instead of the second nitride semiconductor layer and the first nitride semiconductor layer in a region defining the nitride semiconductor device formation region in order to isolate the nitride semiconductor device formation region formed by the semiconductor layer , Lower deposition temperature than at least the first nitride semiconductor layer, the third nitride semiconductor layer made of the group III-V nitride semiconductor layer is characterized in that laminated.

  The invention according to claim 2 of the present application is a group III element comprising at least one group selected from the group consisting of gallium, aluminum, boron and indium, and a group V element including at least nitrogen from the group consisting of nitrogen, phosphorus and arsenic. A nitride semiconductor device comprising a group III-V nitride semiconductor layer comprising: a first nitride semiconductor layer comprising a group III-V nitride semiconductor layer stacked on a substrate; and the first nitride A second nitride semiconductor layer made of the III-V nitride semiconductor layer stacked on the nitride semiconductor layer, and at least the second nitride semiconductor layer and the first nitride semiconductor layer. In order to isolate the nitride semiconductor device formation region, a third nitride semiconductor layer made of the III-V nitride semiconductor layer having a microcrystalline structure is provided in a region partitioning the nitride semiconductor device formation region. Have And wherein the door.

  The invention according to claim 3 of the present application is a group III element comprising at least one group selected from the group consisting of gallium, aluminum, boron and indium, and a group V element including at least nitrogen from the group consisting of nitrogen, phosphorus and arsenic. Forming a first nitride semiconductor layer made of the group III-V nitride semiconductor layer on a substrate in a method for manufacturing a nitride semiconductor device made of a group III-V nitride semiconductor layer comprising: Forming a second nitride semiconductor layer comprising the group III-V nitride semiconductor layer on the first nitride semiconductor layer, and the second nitride semiconductor in the nitride semiconductor device formation region Patterning a mask material on the surface of the layer, covering the nitride semiconductor device formation region, and exposing the surface of the second nitride semiconductor layer in a region defining the nitride semiconductor device formation region; In order to separate the second nitride semiconductor layer and the nitride semiconductor device formation region formed by the first nitride semiconductor layer by using the mask material thus etched as an etching mask, A step of forming a recess in a region formed of the nitride semiconductor layer and the first nitride semiconductor layer, and at least a temperature lower than a film formation temperature of the first nitride semiconductor layer, the group III-V nitride semiconductor; Forming a third nitride semiconductor layer comprising a plurality of layers, filling the recess with the third nitride semiconductor layer, removing the mask material, and exposing the nitride semiconductor device formation region; It is characterized by including.

  Furthermore, the invention according to claim 4 is the method for manufacturing a nitride semiconductor device according to claim 3, wherein the mask material is made of silicon oxide, and the step of filling the recess with the third nitride semiconductor layer includes: The third nitride semiconductor layer is selectively deposited in the recess by MOCVD.

In the nitride semiconductor device according to the present invention, a semiconductor layer having a microcrystalline structure grown at a low temperature is used as an element isolation region, so that the sheet resistance of the element isolation region is 1 × 10 ⁹ Ω / □ or more, and a leakage current is higher than that of the related art. Can be reduced. In particular, leakage current from the gate electrode in the element isolation region having a microcrystalline structure can be reduced.

  In the method for manufacturing a nitride semiconductor device according to the present invention, a nitride semiconductor device having a desired characteristic and structure can be formed only by controlling the epitaxial growth temperature during normal selective regrowth. Thus, a nitride semiconductor device having good controllability and excellent element isolation characteristics can be manufactured with high yield.

  Hereinafter, the nitride semiconductor device of the present invention will be described in accordance with its manufacturing process.

  First, the present invention will be described in detail according to a manufacturing process, taking as an example a HEMT which is a nitride semiconductor device composed of a III-V group nitride semiconductor layer. FIG. 1 is a plan view (FIG. 1a) and a sectional view of a nitride semiconductor device according to an embodiment of the present invention (a sectional view taken along the line AA 'in FIG. 1a is shown in FIG. Is a cross-sectional view of FIG. 1c). FIG. 2 shows a manufacturing process of the nitride semiconductor device of the present invention.

  First, as shown in FIG. 2A, on a substrate 11 made of silicon carbide (SiC), a buffer layer 12 made of aluminum nitride (AlN) having a thickness of about 200 nm, and a non-doped gallium nitride (GaN having a thickness of 2.5 μm). ), A spacer layer 14 made of non-doped aluminum gallium nitride (AlGaN) having a thickness of 7 nm, a carrier supply layer 15 made of n-type aluminum gallium nitride (AlGaN) having a thickness of 15 nm, and a non-doped layer having a thickness of 3 nm. An epi wafer having a structure in which Schottky layers 16 made of aluminum gallium nitride (AlGaN) are sequentially stacked is prepared. Here, the film formation temperature of the semiconductor layer is about 1080 ° C. in a normal MOCVD method or MBE method. In this case, the channel layer 13 corresponds to the first nitride semiconductor layer, the spacer layer 14, the carrier supply layer 15, and the Schottky layer 16 correspond to the second nitride semiconductor layer.

  Next, after patterning the silicon oxide film 17 serving as a mask material for selective regrowth so as to cover the region where the nitride semiconductor device is to be formed, a region that defines the region where the nitride semiconductor device is to be formed is defined as a chlorine-based region. Etching is removed by a dry etching method such as RIE using gas to form the recess 18 (FIG. 2b). The depth of the recess 18 is set to a depth necessary for element isolation of the nitride semiconductor device. In FIG. 2b, the depth is such that a part of the channel layer 13 (first nitride semiconductor layer) is removed by etching.

Thereafter, gallium nitride is epitaxially grown at a temperature (for example, 550 ° C.) lower by about 500 ° C. than the film formation temperature of the channel layer 13 or the like by MOCVD (metal organic chemical vapor deposition). As a result, no epitaxial growth layer is formed on the surface of the silicon oxide film 17, and the low temperature growth layer 19 (corresponding to the third nitride semiconductor layer) can be selectively grown (selective regrowth) in the recess 18. . The low temperature growth layer 19 exhibits high insulating properties (sheet resistance is 1 × 10 ⁹ Ω / □ or more), and the surface thereof can be deposited so as to be flush with the HEMT formation region (FIG. 2c). The low temperature growth layer 19 has a microcrystalline structure.

  Next, the silicon oxide film 17 is removed, and a source electrode 20a and a drain electrode 20b made of a laminate of titanium (Ti) / aluminum (Al) or the like are formed on the exposed Schottky layer 16, and patterned at 800 ° C. for 30 seconds. After the ohmic contact is formed by the rapid heating process, a gate electrode 21 made of a nickel (Ni) / gold (Au) laminate or the like is patterned to form a Schottky contact with the Schottky layer 16 (FIG. 2d). ). Hereinafter, the HEMT can be completed by a normal manufacturing process.

  The nitride semiconductor device thus formed has a planar structure by providing a highly insulating low-temperature growth layer 19 in the recess 18 formed by dry etching (FIG. 1c), and the gate electrode is worried about the disconnection between steps. As a result, the yield and reliability of the manufacturing process are improved.

Further, the sheet resistance is 1 × 10 ⁹ Ω / □ or more, and an element isolation region having a sheet resistance 10 times or more larger than that of the conventionally proposed ion implantation method can be formed.

  In this embodiment, the growth temperature of the low-temperature growth layer 19 having a microcrystalline structure with excellent insulating properties is set to be higher than the growth temperature (1080 ° C.) of the epitaxial layers of the channel layer 13, the spacer layer 14, the carrier supply layer 15, and the Schottky layer 16. Since it is formed only by setting to a low temperature (for example, 550 ° C.), controllability is good. In addition, since the manufacturing method of the present invention follows a normal manufacturing process of a semiconductor device, it can be manufactured with extremely good controllability and high yield.

  Note that a sapphire substrate or a silicon substrate may be used instead of the silicon carbide (SiC) substrate used as an example. In that case, it is preferable to use low-temperature grown gallium nitride (GaN) as the buffer layer 12. In addition, the ohmic electrode is formed after the low temperature growth layer 19 is formed. However, after forming the ohmic electrode, the silicon oxide film 17 may be patterned to form the low temperature growth layer 19. This is because the contact resistance of the ohmic electrode hardly deteriorates in this case.

  In the first embodiment, the HEMT manufacturing method has been described. However, the present invention is not limited to this, and can be applied to a nitride semiconductor device having a high-resistance element isolation region. For example, a buffer layer made of aluminum nitride (AlN) having a thickness of about 200 nm and an active layer made of n-type aluminum gallium nitride (AlGaN) having a thickness of 2.0 μm are formed on a substrate made of silicon carbide (SiC). A field effect transistor (FET) in which a gate electrode in Schottky contact and a source electrode and a drain electrode in ohmic contact are formed on the active layer may be used. In this case, the buffer layer corresponds to the first nitride semiconductor layer, and the active layer corresponds to the second nitride semiconductor layer.

  By selectively depositing a nitride semiconductor layer (third nitride semiconductor layer) having a microcrystalline structure in a recess that reaches the buffer layer, it is possible to perform planar element isolation.

  As yet another embodiment, at least the outermost nitride semiconductor layer of the semiconductor layer constituting the nitride semiconductor device (including the case where the outermost semiconductor layer is the second nitride semiconductor layer of the present invention) is included. Similarly to the above-described method for manufacturing a nitride semiconductor layer having a microcrystalline structure for forming element isolation, the growth temperature may be lowered. Specifically, the present applicant has already applied (Japanese Patent Application Nos. 2004-125321, 2004-125322, and 2004-125323). The growth temperature of the second nitride semiconductor layer is set to the first temperature. Needless to say, the present invention can also be applied to a nitride semiconductor device and a method for manufacturing a nitride semiconductor device in which a control electrode of a HEMT or FET is formed at a temperature lower than the growth temperature of the nitride semiconductor layer by about 400 ° C. or more. Yes. In this case, since the nitride semiconductor layer formed at a lower growth temperature has a highly insulating microcrystalline structure, the current collapse phenomenon is caused by controlling the electrons trapped in the surface level or reducing the surface level density. Suppressed and improved high frequency characteristics are preferable.

  Further, the present invention is not limited to gallium nitride and aluminum gallium nitride, but at least one of the group III elements consisting of at least one of the group consisting of gallium, aluminum, boron and indium, and at least nitrogen of the group consisting of nitrogen, phosphorus and arsenic. The present invention can be applied to a nitride semiconductor device composed of a III-V nitride semiconductor layer composed of a group V element containing V.

  Further, the mask material used when performing selective regrowth in the recess is not limited to silicon oxide, and a material suitable for the nitride semiconductor device and its growth method may be selected. When gallium nitride is formed by MOCVD, silicon oxide is preferably selected.

  In the present invention, the low-temperature growth layer 19 has been described as having a microcrystalline structure. This is an aggregate of microcrystalline grains or a rearranged structure thereof, and includes a growth temperature, an atmospheric gas composition during growth, and a substrate to be grown. Depending on the type of crystal, the size and arrangement of crystal grains vary and can be obtained by controlling the growth temperature within a range where desired insulation characteristics can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS It is explanatory drawing of the nitride semiconductor device of this invention, (a) is a top view, (b) And (c) has shown sectional drawing. It is explanatory drawing of the manufacturing method of the nitride semiconductor device of this invention. It is explanatory drawing of this kind of conventional nitride semiconductor device, (a) is a top view, (b) And (c) has shown sectional drawing.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11; Substrate, 12; Buffer layer, 13; Channel layer, 14; Spacer layer, 15; Carrier supply layer, 16; Schottky layer, 17; Silicon oxide film, 18; Recess, 19; 20b; drain electrode, 21; gate electrode

Claims (4)

Group III-V nitride composed of a group III element consisting of at least one of the group consisting of gallium, aluminum, boron and indium and a group V element containing at least nitrogen from the group consisting of nitrogen, phosphorus and arsenic In a nitride semiconductor device composed of a semiconductor layer,
A first nitride semiconductor layer made of the group III-V nitride semiconductor layer stacked on the substrate and a group III-V nitride semiconductor layer stacked on the first nitride semiconductor layer. Two nitride semiconductor layers and at least the second nitride semiconductor layer and the nitride semiconductor device formation region formed by the first nitride semiconductor layer are separated from each other. The group III-V nitride semiconductor layer having a deposition temperature lower than at least the first nitride semiconductor layer instead of the second nitride semiconductor layer and the first nitride semiconductor layer in the partitioning region 3. A nitride semiconductor device comprising a third nitride semiconductor layer made of Group III-V nitride composed of a group III element consisting of at least one of the group consisting of gallium, aluminum, boron and indium and a group V element containing at least nitrogen from the group consisting of nitrogen, phosphorus and arsenic In a nitride semiconductor device composed of a semiconductor layer,
A first nitride semiconductor layer made of the group III-V nitride semiconductor layer stacked on the substrate and a group III-V nitride semiconductor layer stacked on the first nitride semiconductor layer. Two nitride semiconductor layers and at least the second nitride semiconductor layer and the nitride semiconductor device formation region formed by the first nitride semiconductor layer are separated from each other. A nitride semiconductor device comprising a third nitride semiconductor layer made of the group III-V nitride semiconductor layer having a microcrystalline structure in a partitioning region. Group III-V nitride composed of a group III element consisting of at least one of the group consisting of gallium, aluminum, boron and indium and a group V element containing at least nitrogen from the group consisting of nitrogen, phosphorus and arsenic In a method for manufacturing a nitride semiconductor device comprising a semiconductor layer,
Forming a first nitride semiconductor layer comprising the group III-V nitride semiconductor layer on a substrate;
Forming a second nitride semiconductor layer comprising the group III-V nitride semiconductor layer on the first nitride semiconductor layer;
A mask material is patterned on the surface of the second nitride semiconductor layer in the nitride semiconductor device formation region to cover the nitride semiconductor device formation region, and the second of the regions defining the nitride semiconductor device formation region Exposing the nitride semiconductor layer surface of
Using the patterned mask material as an etching mask, the second nitride semiconductor layer and the nitride semiconductor device formation region formed by the first nitride semiconductor layer are element-isolated. Forming a recess in a region comprising the nitride semiconductor layer and the first nitride semiconductor layer;
Forming a third nitride semiconductor layer made of the group III-V nitride semiconductor layer at a temperature lower than the film forming temperature of the first nitride semiconductor layer, and forming the recess in the third nitride semiconductor; Filling with layers;
Removing the mask material and exposing the nitride semiconductor device formation region. A method of manufacturing a nitride semiconductor device, comprising: 4. The method of manufacturing a nitride semiconductor device according to claim 3, wherein the mask material is made of silicon oxide, and the step of filling the recess with the third nitride semiconductor layer is selected in the recess by MOCVD. A method of manufacturing a nitride semiconductor device, characterized by depositing the third nitride semiconductor layer.

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