JP2006079758A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To detect insulation defect of an integrated circuit in which bit lines are formed so as to cross each other and an integrated circuit in which bit lines and a power source line are arranged parallel to each other. <P>SOLUTION: A semiconductor integrated circuit 100 is provided with, for each bit lines BL0-BL3, switching circuits 110-113 applying selectively power source voltage VDD or ground potential GND to bit lines BL0-BL3, and is also provided with a control circuit 120 switching successively selection voltage of the switching circuits 110-113 so that potential difference is caused between adjacent memory cells MC00-MC32 and between adjacent memory cell-power source lines VDD0, GND0, GND1 at least once. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technique for detecting an insulation failure between wiring patterns and memory cells formed in a semiconductor integrated circuit. The present invention is applied to, for example, detection of an insulation failure between memory cells in a semiconductor memory device or an insulation failure between the memory cell and a power supply line.

  In recent years, with the miniaturization of semiconductor integrated circuits, the interval between wiring patterns tends to be shortened. For this reason, in recent semiconductor integrated circuits, insulation failure of wiring patterns due to adhesion of dust or the like is likely to occur. Therefore, the necessity of a test for accurately detecting an insulation failure between wiring patterns in the manufacturing stage is increasing.

  As a technique for detecting an insulation failure between wiring patterns, for example, a technique described in Patent Document 1 below is known.

FIG. 10 is a conceptual diagram for explaining the test technique described in Patent Document 1. In the integrated circuit 1000 of FIG. 10, four bit lines BL0 to BL3 are arranged in parallel, and voltage application circuits 1010 to 1013 are connected to these bit lines BL0 to BL3. A voltage of 9 volts is applied to the bit lines BL0 and BL2 by the voltage application circuits 1010 and 1012, and a voltage of 0 volt is applied to the bit lines BL1 and BL3 by the voltage application circuits 1011 and 1013. Therefore, the potential differences (absolute values) between adjacent bit lines BL0-BL1, BL1-BL2, BL2-BL3 are all 9 volts. As a result, when there is an insulation failure between any of the bit lines, a current flows between the bit lines due to electrical stress. Thereby, an insulation failure between the bit lines is detected.
JP-A-6-029364

  As described above, in the technique disclosed in Patent Document 1, a high voltage (9 volts) and a low voltage (0 volts) are alternately applied to a plurality of bit lines arranged in parallel to each other between bit lines. Insulation failure is detected. However, even if the technique of Patent Document 1 is applied to an integrated circuit in which bit lines are formed so as to cross each other, or an integrated circuit in which bit lines and power supply lines are arranged in parallel, the insulation failure Cannot be detected. Hereinafter, the reason will be described with reference to FIGS.

  FIG. 11A is a conceptual diagram illustrating a configuration example of an integrated circuit formed so that bit lines intersect each other. In a semiconductor memory device, bit lines in a memory cell array may be formed so as to cross each other. In FIG. 11A, BL0 to BL3 are bit lines, and MC00 to MC32 are memory cells. In the example of FIG. 11A, adjacent bit line pairs BL0, BL1 and BL2, BL3 intersect at different locations. FIG. 11B shows an example in which 9 volts and 0 volts are alternately applied to the bit lines BL0 to BL3 in such a wiring structure. In this example, no potential difference occurs between the memory cells MC01 and MC21 (see the hatched area P). For this reason, even if insulation failure occurs in this portion, it cannot be detected.

  FIG. 12A is a conceptual diagram illustrating a configuration example of an integrated circuit in which bit lines and power supply lines are arranged in parallel. In the example of FIG. 12A, the bit lines BL0 and BL1 are sandwiched between the power supply line (ground line) GND0 and the power supply line VDD0, and the bit lines BL2 and BL3 are connected by the power supply line VDD0 and the power supply line (ground line) GND1. It is sandwiched. FIG. 12B shows an example in which 9 volts and 0 volts are alternately applied to the bit lines BL0 to BL3 in such a wiring structure. As can be seen from FIG. 12B, in this example, there is no potential difference between the wiring patterns VDD0-BL2 and between the wiring patterns BL3-GND1 (see hatched lines P1, P2). For this reason, even if insulation failure occurs in these regions P1 and P2, it cannot be detected.

  FIG. 13A is a conceptual diagram illustrating a configuration example of an integrated circuit in which bit lines are formed so as to cross each other and the bit lines and the power supply lines are arranged in parallel. In FIG. 13A, MC00 to MC32 are memory cells. In the example of FIG. 13A, the bit lines BL0, BL1 and BL2, BL3 intersect each other at two locations. Further, the bit lines BL0 and BL1 are sandwiched between the ground line GND0 and the power supply line VDD0, and the bit lines BL2 and BL3 are sandwiched between the power supply line VDD0 and the ground line GND1. FIG. 13B shows an example in which 9 volts is applied to the bit lines BL0 and BL2 and 0 volts is applied to the bit lines BL1 and BL3 in such a wiring structure. As can be seen from FIG. 13B, in this example, no potential difference occurs at the six locations indicated by the dotted lines P1 to P6. For this reason, even if the insulation defect has generate | occur | produced in these parts P1-P6, it cannot detect.

  The present invention has been made in view of the problems of the prior art as described above, and provides a semiconductor integrated circuit capable of accurately detecting an insulation failure regardless of the wiring structure of a bit line or a power supply line. For the purpose.

  (1) A semiconductor integrated circuit according to a first invention (corresponding to claim 1) includes a plurality of signal line patterns arranged in parallel to each other and any two or more intersecting each other at one or more locations, One or a plurality of power supply line patterns arranged in parallel with the signal line pattern, and a second voltage different from the first voltage or the first voltage is provided for each of the plurality of signal line patterns. A plurality of switching circuits to be selectively applied, and a switching circuit so that a potential difference occurs between adjacent signal line patterns and between adjacent signal line patterns / power supply line patterns at least once in all regions of all signal line patterns. And a control circuit for sequentially switching the selected voltages.

  (2) A semiconductor integrated circuit according to a second invention (corresponding to claim 5) includes a plurality of signal line patterns arranged in parallel to each other and any two or more intersecting each other at one or more locations, A plurality of switching circuits which are provided for each of a plurality of signal line patterns and selectively apply a first voltage or a second voltage different from the first voltage to the corresponding signal line patterns; and in all regions of all the signal line patterns. And a control circuit that sequentially switches the selection voltage of the switching circuit so as to generate a potential difference between adjacent signal line patterns at least once.

  (3) A semiconductor integrated circuit according to a third invention (corresponding to claim 9) includes a plurality of signal line patterns arranged in parallel with each other, a plurality of signal line patterns in parallel with the plurality of signal line patterns. A plurality of power supply line patterns arranged so as to sandwich part or all of the pattern and a plurality of signal line patterns are provided for each of the plurality of signal line patterns, and a first voltage or a second voltage different from the first voltage is selected for the corresponding signal line pattern Multiple switching circuits to be applied and the selection voltage of the switching circuit sequentially so that a potential difference occurs between adjacent signal line patterns and between adjacent signal line patterns / power supply line patterns at least once in all signal line patterns. And a control circuit for switching.

  In the first to third inventions, a switching circuit for switching the applied voltage to each signal line pattern between the first voltage and the second voltage is provided for each signal line pattern, and between the adjacent signal line patterns (first, In the third invention, there is provided a control circuit for sequentially switching the selection voltage of the switching circuit so that a potential difference is generated at least once between adjacent signal line patterns and between adjacent signal line patterns and power supply line patterns. Thereby, even when the bit lines are formed so as to cross each other or when the bit lines and the power supply lines are arranged in parallel, it is possible to detect an insulation failure of the semiconductor integrated circuit.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the size, shape, and arrangement relationship of each component are shown only schematically to the extent that the present invention can be understood, and the numerical conditions described below are merely examples. .

First Embodiment A semiconductor integrated circuit according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 3, taking as an example the case where the present invention is used for an insulation failure inspection of a memory array provided in a semiconductor memory device I will explain.

  FIG. 1 is a conceptual diagram showing a main configuration of a semiconductor integrated circuit 100 according to this embodiment.

  As shown in FIG. 1, the semiconductor integrated circuit 100 of this embodiment includes bit lines BL0 to BL3, memory cells MC00 to MC32, power supply lines VDD0, GND0, GND1, switching circuits 110 to 113, and a control circuit. 120 and a peripheral circuit 130.

  The bit lines BL0 to BL3 (corresponding to the signal line pattern of the present invention) are used for data writing / reading like the bit lines of a normal memory array. As shown in FIG. 1, the bit lines BL0 to BL3 are arranged in parallel to each other. Further, the bit lines BL0 and BL1 cross each other at two places. Thus, among the memory cells MC00, MC01, MC02 on the bit line BL0, MC00, MC02 are arranged in the first row of the bit line group, and MC01 is arranged in the second row. On the other hand, among the memory cells MC10, MC11, and MC12 on the bit line BL1, MC10 and MC12 are arranged in the second row and MC11 is arranged in the first row. Similarly, the bit lines BL2 and BL3 intersect each other at two places.

  Since the memory cells MC00 to MC32 are memory cells such as ordinary DRAMs, detailed description is omitted.

  The power supply lines VDD0, GND0, and GND1 are arranged in parallel with the bit lines BL0 to BL3. A first voltage (for example, a power supply voltage of 9 volts) VDD is supplied to the power supply line VDD0. On the other hand, the second voltage (ground potential, that is, 0 volt) is supplied to the power supply lines GND0 and GND1 (that is, the ground line). As shown in FIG. 1, the ground line GND0 is arranged adjacent to the first row of the memory cell array. Therefore, the memory cells MC00 and MC02 of the first bit line BL0 and the memory of the second bit line BL1. It is close to the cell MC11. Similarly, the ground line GND1 is arranged adjacent to the fourth row of the memory cell array, and therefore is close to the memory cells MC30 and MC32 of the fourth bit line BL3 and the memory cell MC21 of the third bit line BL2. ing. On the other hand, the power supply line VDD0 is arranged between the second and third rows of the memory cell array, and is therefore close to the memory cells MC10, MC01, MC12 and the memory cells MC20, MC31, MC22.

  Switching circuits 110-113 are provided corresponding to bit lines BL0-BL3. The switching circuits 110 to 113 selectively apply the first voltage VDD or the second voltage GND to the corresponding bit lines BL0 to BL3. Here, the input terminal for the second voltage is connected to the ground line for normal operation.

  The control circuit 120 selects the selection voltages of the switching circuits 110 to 113 so that a potential difference occurs between adjacent memory cells and between memory cells and power supply lines at least once in all regions of all bit lines BL0 to BL3. Switch sequentially. Details of the operation of the control circuit 120 will be described later.

  The peripheral circuit 130 is another integrated circuit block formed in the same semiconductor integrated circuit 100. The peripheral circuit 130 need not be a circuit contributing to the operation of the memory cell array, and may be any circuit other than the memory cell array. The peripheral circuit 130 receives the power supply voltage VDD for normal operation from a power supply pad (not shown) of the integrated circuit 100 and supplies it to the switching circuits 110 to 113. That is, in this embodiment, the power supply voltage VDD supplied from the power pad for normal operation is used for the insulation failure test.

Next, the operation of the semiconductor integrated circuit 100 shown in FIG. 1 will be described with reference to FIGS.
(1) Turning on the power When the integrated circuit 100 is turned on, the power supply voltage VDD is supplied from the peripheral circuit 130 to the switching circuits 110 to 113.

(2) Test 1
When the test mode is started, first, the control circuit 120 causes the odd-numbered switching circuits 110 and 112 to select the power supply voltage VDD and the even-numbered switching circuits 111 and 113 to select the ground potential GND (see FIG. 2 (A)). Thereby, in regions P101 to P112 indicated by dotted lines in FIG. 2A, potential differences occur between adjacent memory cells and between memory cells and power supply lines. On the other hand, no potential difference occurs in other regions.

  The control circuit 120 continues this state for a predetermined time. As a result, when an insulation failure exists in any of the regions P101 to P112, a current flows through the region due to electrical stress. Thereby, an insulation failure of the memory cell array is detected. The current is detected by a current detection means (not shown).

(3) Test 2
Next, the control circuit 120 causes the switching circuits 110 and 112 to select the ground potential GND, and causes the switching circuits 111 and 113 to select the power supply voltage VDD (see FIG. 2B). As a result, in the regions P201 to P212 indicated by dotted lines in FIG. 2B, potential differences occur between adjacent bit lines and between the bit lines and the power supply lines. On the other hand, no potential difference occurs in other regions.

  The control circuit 120 continues this state for a predetermined time. As a result, when an insulation failure exists in any of the regions P201 to P212, a current flows through the region due to electrical stress. Thereby, an insulation failure between adjacent bit lines and between a bit line and a power supply line in the memory cell array is detected.

  FIG. 3 is a conceptual diagram in which areas where insulation failure can be detected in the above-described tests 1 and 2 are listed. In FIG. 3, a circled number 1 indicates a bit line element that can detect an insulation failure in Test 1, and a circled number 2 indicates a bit line element that can detect an insulation failure in Test 2. As can be seen from FIG. 3, according to this embodiment, insulation failure can be tested at least once in all regions of all bit lines BL0 to BL3.

  In this embodiment, since the test power supply voltage VDD and the ground potential are supplied from the power supply pads for normal operation, there is no increase in the number of pads and the number of circuits. Therefore, the semiconductor integrated circuit 100 This is effective in reducing the area.

  In this embodiment, the case where the first invention is applied to the memory cell array is taken as an example. However, the first invention can also be applied to a normal signal line group to which no memory cells are connected.

Second Embodiment Another embodiment of the semiconductor integrated circuit according to the first invention will be described with reference to FIGS. 4 and 5 in which the present invention is used for insulation failure inspection of a memory array provided in a semiconductor memory device. Will be described.

  FIG. 4 is a conceptual diagram showing the main configuration of the semiconductor integrated circuit 400 according to this embodiment. In FIG. 4, components denoted by the same reference numerals as those in FIG. 1 are the same as those in FIG. 1.

  The switching circuits 410 to 413 are provided corresponding to the bit lines BL0 to BL3. The switching circuits 410 to 413 selectively apply the normal operation power supply voltage VDDcore, the test operation power supply voltage VDDarray (first voltage) or the ground potential GND (second voltage) to the corresponding bit lines BL0 to BL3. Apply to. That is, the ground potential GND is supplied from the same power supply pad (not shown) regardless of the normal operation / test operation.

  The power supply pad 421 is a pad for supplying the power supply potential VDDcore for normal operation to the peripheral circuit 130. The power supply pad 422 is a pad for supplying a power supply potential VDDarray for test operation to the switching circuits 410 to 413. As in the first embodiment described above, the power supply voltage supplied to the peripheral circuit 130 (in this embodiment, the power supply voltage VDDcore for normal operation) is applied from the peripheral circuit 130 to the switching circuits 410 to 413.

Next, the operation of the semiconductor integrated circuit 400 illustrated in FIG. 4 will be described with reference to FIG.
(1) Turning on the power When the integrated circuit 400 is turned on, the power supply voltage VDDcore is supplied from the peripheral circuit 130 to the switching circuits 410 to 413.

(2) Normal operation In the normal operation, the control circuit 120 causes the switching circuits 410 to 413 to select the power supply voltage VDDcore supplied from the peripheral circuit 130. The power supply line VDDcore is also supplied to the power supply line VDD0 by means not shown. As a result, the memory cell array unit such as the bit lines BL0 to BL3, the memory cells MC00 to MC32, and the power supply lines VDD0, GND0, and GND1 performs a known normal operation.

(3) Test 1
In the test mode, first, the control circuit 120 applies VDDarray to the power supply line VDD0. Further, the odd-row switching circuits 410 and 412 select the voltage VDDarray of the power supply pad 422, and the even-numbered switching circuits 411 and 413 select the ground potential GND (see FIG. 5A). As a result, in the regions indicated by dotted lines P301 to P312 in FIG. 5A, potential differences occur between adjacent memory cells and between memory cells and power supply lines. On the other hand, no potential difference occurs in other regions.

  The control circuit 120 continues this state for a predetermined time. As a result, when an insulation failure exists in any of the regions P301 to P312, a current flows through the region due to electrical stress. Thereby, an insulation failure of the memory cell array is detected. The current is detected by a current detection means (not shown).

(4) Test 2
Next, the control circuit 120 causes the switching circuits 410 and 412 to select the ground potential GND, and causes the switching circuits 411 and 413 to select the voltage VDDarray (see FIG. 5B). As a result, in the regions indicated by dotted lines P401 to P412 in FIG. 5B, potential differences occur between adjacent memory cells and between memory cells and power supply lines. On the other hand, no potential difference occurs in other regions.

  The control circuit 120 continues this state for a predetermined time. As a result, when there is an insulation failure in any of the regions P401 to P412, a current flows through the region due to electrical stress. Thereby, an insulation failure of the memory cell array is detected.

  Thus, according to this embodiment, insulation failure can be tested at least once in all regions sandwiched between the bit lines BL0 to BL3 and the power supply lines VDD0, GND0, and GND1.

  In this embodiment, the test power supply voltage VDDarray is supplied from the power supply pad 422 dedicated to the test operation. As a result, it is possible to detect only the current flowing between the bit lines BL0 to BL3 and the power supply lines VDD0, GND0, and GND1 during the insulation failure test, thus improving the accuracy and reliability of the insulation failure test. Can do.

  In this embodiment, the case where the first invention is applied to the memory cell array is taken as an example. However, the first invention can also be applied to a normal signal line group to which no memory cells are connected.

Third Embodiment Next, an embodiment of a semiconductor integrated circuit according to the second invention will be described with reference to an example in which the present invention is used for an insulation failure test of a memory array provided in a semiconductor memory device. 7 for explanation.

  FIG. 6 is a conceptual diagram showing the main configuration of the semiconductor integrated circuit 600 according to this embodiment. In FIG. 6, components denoted by the same reference numerals as those in FIG. 1 are the same as those in FIG. 1.

  This embodiment differs from the first embodiment described above in that the power supply lines VDD0, GND0, and GND1 are not provided adjacent to the bit lines BL0 to BL3.

Next, the operation of the semiconductor integrated circuit 600 shown in FIG. 6 will be described with reference to FIG.
(1) Turning on the power When the integrated circuit 600 is turned on, the power supply voltage VDD is applied from the peripheral circuit 130 to the switching circuits 110 to 113.

(2) Test 1
When the test mode is started, first, the control circuit 120 causes the odd-numbered switching circuits 110 and 112 to select the power supply voltage VDD and the even-numbered switching circuits 111 and 113 to select the ground potential GND (see FIG. 7 (A)). Thus, a potential difference between adjacent memory cells is generated in regions P501 to P508 indicated by dotted lines in FIG. On the other hand, no potential difference occurs in other regions (that is, regions sandwiched between the memory cells MC01 and MC21).

  The control circuit 120 continues this state for a predetermined time. As a result, when an insulation failure exists in any of the regions P501 to P508, a current flows through the region due to electrical stress. Thereby, an insulation failure of the memory cell array is detected. The current is detected by a current detection means (not shown).

(3) Test 2
Next, the control circuit 120 causes the first two switching circuits 110 and 111 to select the power supply voltage VDD, and causes the other two switching circuits 112 and 113 to select the ground potential GND (FIG. 7B )reference). Accordingly, a potential difference between adjacent bit lines is generated in regions P601 to P603 indicated by dotted lines in FIG. On the other hand, no potential difference occurs in other regions.

  The control circuit 120 continues this state for a predetermined time. Thereby, when there is an insulation failure in the region P601, a current flows in the region due to electrical stress. Thereby, an insulation failure of the memory cell array is detected.

  In this way, according to this embodiment, it is possible to test insulation failure at least once in all the regions sandwiched between the bit lines BL0 to BL3.

  In this embodiment, there is no increase in the number of pads or an increase in the number of circuits for the same reason as in the first embodiment, and therefore the area of the semiconductor integrated circuit 600 can be reduced. However, as in the second embodiment described above, a power pad dedicated for an insulation failure test may be provided.

  In this embodiment, the case where the second invention is applied to the memory cell array is taken as an example. However, the second invention can also be applied to a normal signal line group to which no memory cell is connected.

Fourth Embodiment Next, an embodiment of a semiconductor integrated circuit according to the third invention will be described with reference to FIGS. 8 and 9, taking the case where the present invention is applied to a signal line group as an example.

  FIG. 8 is a conceptual diagram showing the main configuration of the semiconductor integrated circuit 800 according to this embodiment. In FIG. 8, the constituent elements having the same reference numerals as those in FIG. 1 are the same as those in FIG.

  As shown in FIG. 8, the signal lines SL0 to SL3 are arranged in parallel to each other.

  The ground line GND0 is disposed adjacent to the signal line SL0. The ground line GND1 is disposed adjacent to the signal line SL3. On the other hand, the power supply line VDD0 is disposed between the signal lines SL1 and SL2.

Next, the operation of the semiconductor integrated circuit 800 illustrated in FIG. 8 will be described with reference to FIG.
(1) Turning on the power When the integrated circuit 800 is turned on, the power supply voltage VDD is applied from the peripheral circuit 130 to the switching circuits 110 to 113.

(2) Test 1
When the test mode is started, first, the control circuit 120 causes the odd-numbered switching circuits 110 and 112 to select the power supply voltage VDD and the even-numbered switching circuits 111 and 113 to select the ground potential GND (see FIG. 9 (A)). As a result, in regions P701 to P704 indicated by dotted lines in FIG. 9A, potential differences occur between adjacent signal lines and between signal lines and power supply lines. On the other hand, no potential difference occurs in other regions.

  The control circuit 120 continues this state for a predetermined time. As a result, when there is an insulation failure in any of the regions P701 to P704, a current flows through the region due to electrical stress. Thereby, an insulation failure of the signal line group is detected. The current is detected by a current detection means (not shown).

(3) Test 2
Next, the control circuit 120 causes the switching circuits 110 and 112 to select the ground potential GND, and causes the switching circuits 111 and 113 to select the power supply voltage VDD (see FIG. 9B). Accordingly, in regions P801 to P804 indicated by dotted lines in FIG. 9B, potential differences occur between adjacent signal lines and between signal lines and power supply lines. On the other hand, no potential difference occurs in other regions.

  The control circuit 120 continues this state for a predetermined time. As a result, when an insulation failure exists in any of the regions P801 to P804, a current flows through the region due to electrical stress. Thereby, an insulation failure of the signal line group is detected.

  In this way, according to this embodiment, insulation failure can be tested at least once in all regions sandwiched between the signal lines SL0 to SL3 and the power supply lines VDD0, GND0, and GND1.

  In this embodiment, there is no increase in the number of pads or an increase in the number of circuits for the same reason as in the first embodiment, so that the area of the semiconductor integrated circuit 800 can be reduced. However, as in the second embodiment described above, a power pad dedicated for an insulation failure test may be provided.

  In this embodiment, the case where the third invention is applied to a normal signal line group is taken as an example. However, the third invention is also applied to a memory cell array similar to the first to third embodiments. Can do.

1 is a circuit diagram schematically showing a configuration of a semiconductor integrated circuit according to a first embodiment. FIG. 3 is a conceptual diagram for explaining an operation of the semiconductor integrated circuit according to the first embodiment. FIG. 3 is a conceptual diagram for explaining an operation of the semiconductor integrated circuit according to the first embodiment. FIG. 6 is a circuit diagram schematically showing a configuration of a semiconductor integrated circuit according to a second embodiment. It is a conceptual diagram for demonstrating operation | movement of the semiconductor integrated circuit which concerns on 2nd Embodiment. It is a circuit diagram which shows roughly the structure of the semiconductor integrated circuit which concerns on 3rd Embodiment. It is a conceptual diagram for demonstrating operation | movement of the semiconductor integrated circuit which concerns on 3rd Embodiment. It is a circuit diagram which shows roughly the structure of the semiconductor integrated circuit which concerns on 4th Embodiment. It is a conceptual diagram for demonstrating operation | movement of the semiconductor integrated circuit which concerns on 4th Embodiment. It is a circuit diagram which shows schematically the structure of the conventional semiconductor integrated circuit. It is a circuit diagram which shows roughly the structure and operation | movement of the conventional semiconductor integrated circuit. It is a circuit diagram which shows roughly the structure and operation | movement of the conventional semiconductor integrated circuit. It is a circuit diagram which shows roughly the structure and operation | movement of the conventional semiconductor integrated circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100,400,600,800 Semiconductor integrated circuit 110-113,410-413 Switching circuit 120 Control circuit 130 Peripheral circuit 421,422 Power supply pad BL0-BL3 Bit line SL0-SL3 Signal line MC00-MC32 Memory cell VDD0, GND0, GND1 Power line

Claims (12)

A plurality of signal line patterns arranged in parallel to each other and any two or more intersect each other at one or more places;
One or more power supply line patterns arranged in parallel with the signal line pattern;
A plurality of switching circuits provided for each of the plurality of signal line patterns and selectively applying a first voltage or a second voltage different from the first voltage to the corresponding signal line pattern;
The selection voltage of the switching circuit so that a potential difference occurs between the adjacent signal line patterns and between the adjacent signal line pattern and the power supply line pattern at least once in all regions of all the signal line patterns. A control circuit for sequentially switching,
A semiconductor integrated circuit comprising:   2. The semiconductor integrated circuit according to claim 1, wherein the first voltage and the second voltage are voltages supplied from a power supply voltage supply pad for normal operation.   2. The semiconductor integrated circuit according to claim 1, wherein at least one of the first voltage and the second voltage is a voltage supplied from a power supply voltage supply pad dedicated for testing. The signal line pattern is a bit line connected to memory cells in the same row;
The switching circuit causes the potential difference between the adjacent memory cells and between the adjacent memory cells and the power supply line pattern at least once in all regions of all the signal line patterns. Switch the selection voltage sequentially.
The semiconductor integrated circuit according to claim 1, wherein: A plurality of signal line patterns arranged in parallel to each other and any two or more intersect each other at one or more places;
A plurality of switching circuits provided for each of the plurality of signal line patterns and selectively applying a first voltage or a second voltage different from the first voltage to the corresponding signal line pattern;
A control circuit for sequentially switching the selection voltage of the switching circuit so that a potential difference between the adjacent signal line patterns is generated at least once in all regions of all the signal line patterns;
A semiconductor integrated circuit comprising:   6. The semiconductor integrated circuit according to claim 5, wherein the first voltage and the second voltage are voltages supplied from a power supply voltage supply pad for normal operation.   6. The semiconductor integrated circuit according to claim 5, wherein at least one of the first voltage and the second voltage is a voltage supplied from a power supply voltage supply pad dedicated for testing. The signal line pattern is a bit line connected to memory cells in the same row;
The control circuit sequentially switches the selection voltage of the switching circuit so that a potential difference between adjacent memory cells is generated at least once in all regions of all the signal line patterns.
8. The semiconductor integrated circuit according to claim 5, wherein A plurality of signal line patterns arranged in parallel to each other;
A plurality of power line patterns arranged in parallel with the plurality of signal line patterns and sandwiching part or all of the plurality of signal line patterns;
A plurality of switching circuits provided for each of the plurality of signal line patterns and selectively applying a first voltage or a second voltage different from the first voltage to the corresponding signal line pattern;
Control for sequentially switching the selection voltage of the switching circuit so that a potential difference occurs between the adjacent signal line patterns and between the adjacent signal line pattern and the power supply line pattern at least once in all the signal line patterns. Circuit,
A semiconductor integrated circuit comprising:   10. The semiconductor integrated circuit according to claim 9, wherein the first voltage and the second voltage are voltages supplied from a power supply voltage supply pad for normal operation.   10. The semiconductor integrated circuit according to claim 9, wherein at least one of the first voltage and the second voltage is a voltage supplied from a power supply voltage supply pad dedicated for testing. The signal line pattern is a bit line connected to memory cells in the same row;
The switching circuit causes the potential difference between the adjacent memory cells and between the adjacent memory cells and the power supply line pattern at least once in all regions of all the signal line patterns. Switch the selection voltage sequentially.
The semiconductor integrated circuit according to claim 9, wherein:

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