JP2006139901A - Dram memory having common precharger - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide memory layout for a precharge circuit connected between other pair of bit lines rather than a sense amplifier. <P>SOLUTION: The two bit lines of each of the bit line pairs are connected to other precharge circuits and charged to the mutually different precharge voltage. In other words, the bit line and a bit bar line are sensed by the sense amplifier connected to each of the bit-line pairs connected to the other precharge circuits. It is possible that a sense stress test is performed by activating each address line, simultaneously with this configuration and the bit line and the bit-bar line inside each of the sense line pairs are charged to other voltage. The number of the test pads required can also be reduced by such a configuration. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a DRAM (Dynamic Random Access Memory) semiconductor memory device, and more particularly to a structure and test of a DRAM memory.

  A DRAM semiconductor memory typically includes a memory cell array, an equalization circuit, a precharge circuit, a sense amplifier, a bit line, and a word line. One commonly used structure includes twisted bit lines. FIG. 1 shows an example of a simple conventional DRAM portion. Memory elements (not shown) are arranged at intersections between the word lines WL and the bit lines 131 to 138. The bit lines 131 to 134 are twisted bit line pairs, and the bit lines 135 to 138 are not twisted. Each bit line pair has an associated equalization circuit, precharge circuits 121-128, and associated sense amplifiers 110-117. In order to improve the area efficiency, each sense amplifier is used by two memory cell arrays.

  Since process processes for integrated circuits do not always produce perfect devices, each device must be tested after the manufacturing process. Sometimes burn-in tests using high temperatures and high voltages are typically used to ensure that installed DRAMs operate according to their product application.

  A commonly used burn-in test induces a voltage difference between adjacent memory cells. For memories that do not have twisted bit lines, 0, 3, 4, and 7 word lines are enabled, and after precharging the bit lines with a high voltage, 1, 2, 5, and 6 word lines are enabled. And precharge the bit line to a low voltage.

  As shown in FIG. 1, in a memory with twisted bit lines, the test sequence described above does not induce a voltage difference between adjacent cells. FIG. 2A is a diagram illustrating application of the test voltage. FIG. 2B is a diagram illustrating a voltage appearing in a typical memory cell. As shown in FIG. 2B, bit line BL0 intersects four high voltage cells (indicated by vertical mesh circles) and bit line BL0B is in four low voltage cells (indicated by horizontal mesh circles). Intersect. As a result, the sense amplifier can sense the voltage difference between the bit lines BL0 and BL0B. Each of the bit lines BL1 and BL1B intersects two high voltage cells and two low voltage cells. As a result, if all word lines are simultaneously activated in a memory device having twisted bit lines, a suitable voltage difference between the bit lines BL1 and BL1B does not occur, and the test is not performed satisfactorily. .

Therefore, the conventional technique having the above-described problem divides the word lines into the following groups.
For sense stress testing:
WL_4k and WL_4k + 3
WL_4k + 1 and WL_4k + 2
For the write stress test:
WL_4k and WL_4k + 2
WL_4k + 1 and WL_4k + 3
Therefore, four test pads are required to properly activate the word line during testing.

An object of the present invention is to provide a semiconductor memory device capable of effectively applying a sensing stress to a twist bit line.
Another object of the present invention is to provide a wafer burn-in test method for a semiconductor memory device.

  The present invention provides a memory layout of a precharge circuit that is coupled to different bit lines than is coupled to a sense amplifier. Two bit lines in each bit line pair are connected to different precharge circuits and can be charged to different precharge voltages. That is, the bit line and the bit line sense line in each bit line pair are connected to different precharge circuits. With this configuration, a sense stress test can be performed by simultaneously activating all address lines. The bit lines and bit bar lines in each bit line pair are precharged to different voltages. Even if the bit line is twisted, the voltage can be sensed when all word lines are activated simultaneously.

  As in the prior art, a write stress test can be performed by sequentially activating even and odd word lines. This requires two test pads. However, according to the present invention, the write test is performed by simultaneously activating all word lines, and such two test pads can be used during the write test. As a result, the number of test pads required from four test pads to two test pads can be reduced.

  According to the memory device of the present invention, all word lines are enabled at a time during the wafer burn-in test, and different bit line voltages are applied to adjacent bit lines of the twist bit line structure. As a result, sensing stress is applied to adjacent bit lines without data collision on the twisted bit lines that occurred during the conventional wafer burn-in test. And since all the word lines are enabled at once to give sensing stress, the productivity of wafer burn-in test is improved. In addition, the number of pads to be probed during the wafer burn-in test can be reduced, and a plurality of chips can be tested at a time, so that productivity is further improved.

For a full understanding of the invention and the operational advantages of the invention and the objects achieved by the practice of the invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the invention and the contents described in the accompanying drawings. Must be referenced.
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote the same members.

  The layout of the first embodiment is illustrated in FIG. The embodiment shown in FIG. 3 includes three DRAM array blocks 302, 304, and 305. Six sense amplifiers 311 to 316 are arranged between the memory array blocks. Each sense amplifier is connected between the bit lines as in the prior art. An equalization circuit (indicated by a hatched block) is connected between each bit line pair as in the prior art. A typical equalization circuit is represented by reference numeral 322. However, it should be noted that an equalization circuit exists between each bit line pair.

  The precharge circuit is displayed as a rectangle of horizontal and vertical mesh lines in FIG. The vertical mesh line rectangle represents the high voltage precharger and the horizontal mesh line rectangle represents the low voltage precharger. For example, block 321 represents a low voltage precharge circuit and block 324 represents a high voltage precharge circuit. The precharge circuit, the equalization circuit, and the memory array will be specifically described below in connection with FIGS. 7A to 7C. The equalization circuit is controlled by equalization circuit control signals EQ_A and EQ_B, and the precharge circuit is controlled by precharge control signals PRE_A and PRE_B.

  Each sense amplifier is connected to a bit line pair. For example, the sense amplifier 311 is connected between the bit lines BLn and BLnB. Similarly, for example, the equalization circuit 322 is connected between the bit lines of each bit line pair. However, each bit line of each bit line pair is connected to another precharge circuit. That is, the precharge circuit is connected between the bit line pairs connected to each sense amplifier. Therefore, during the burn-in test, the two bit lines in each bit line pair can be precharged to different precharge voltages. As a result, during the burn-in test, adjacent cells have a high voltage and a low voltage as shown in FIG. 4B. The horizontal mesh line precharge circuit is connected to the low voltage line VBL_L, and the vertical mesh line precharge circuit is connected to the high voltage line VBL_H.

  The terms low voltage and high voltage are used to mean low and high voltages for special circuits within the memory array. They are the conventional low and high voltage levels used during the burn-in test. It should be noted that during normal operation, every bit line is precharged to the same voltage as before.

  During the sense stress test, all word lines are activated simultaneously as shown in FIG. 4A. The voltages on the bit lines BL0 and BL0B and the voltages on the bit lines BL1 and BL1B appear as shown in FIG. 4A. The voltage of adjacent cells is shown in FIG. 4B. As shown in FIG. 4B, each bit line senses a cell charged to a specific voltage. This is true for both untwisted bitline pairs and twisted bitline pairs.

  With the arrangement shown in FIG. 3, it is possible to precharge the bit lines and bit bar lines to different voltage levels simultaneously. That is, for example, the bit lines BL1 and BL1B are connected to other precharge circuits connected to different burn-in charge voltages VBL_H and VBL_L. The bit lines BL1 and BL1B can be charged to other voltages at the same time. This can shorten the test period as shown in FIG. 4A.

  5A and 5B show a structure for performing a wafer burn-in test. The column decoder 501 is connected to a memory array 502 including first and second array blocks 506 and 510. The sense amplifier 507 is arranged between the arrays 506 and 510. Pads 508 and 509 are coupled to an external tester to provide appropriate signals to the word lines. Specific diagrams of various embodiments of the memory 502 are provided in FIGS. 7A-7C. Wafer burn-in control signal WBE activates wafer burn-in processor 504. Sequentially, the processor 504 activates the address decoder 505.

  Two tests can be performed by the circuit shown. The two tests are a sense stress test and a write stress test. In order to provide a signal for performing such a test, only two pads 508, 509 are required. The reason why only two pads are required is that, as described above, the memory includes a precharge circuit having two voltage levels, and all the lines are simultaneously activated during the sense test. During the write test, the word lines are separated into two groups that require two test pads. However, these pads can be used to activate any line during the sense test.

  Next, how to perform two tests is described. In the sense stress test, all word lines are activated simultaneously as described above. FIG. 6A is a timing diagram showing how the sense stress test is performed. Time periods a, b, c, d appear along the horizontal axis. The word lines P_even and P-odd are activated simultaneously. The low precharge voltage VBL_L and the high precharge voltage VBL_H appear simultaneously as shown in FIG. 6A. Charging occurs between periods a and c, and sensing occurs between periods b and d.

The manner in which the address decoder 505 activates the word line during the write stress test is shown in FIG. 5B. Every word line is activated by two signals P_even and P_odd connected to pads 508 and 509.
During the write stress test, as before, the word lines are divided into two groups of even lines and odd lines as follows.
1) WL_4k and WL_4k + 2
2) WL_4k + 1 and WL_4k + 3

During the sense stress test, all word lines are activated simultaneously. This is because the two groups are combined into one group as follows.
WL_4k, WL_4k + 1, WL_4k + 2 and WL_4k + 3
Therefore, both the sense stress test and the write stress test can be performed using only two test pads. This is in contrast to requiring four test pads in the prior art.

As shown in FIG. 5B, the two test signals P_even, P_odd provide inputs for gates 561-564 to generate signals PWBE0, PWBE1, PWBE2, PWBE3. Signals PWBE0, PWBE1, PWBE2, and PWBE3 activate the word lines as follows.
PWBE0 lines 0, 4, 8, 12
PWBE1 Line 1, 5, 9, 13
PWBE2 lines 2, 6, 10, 14
PWBE3 Line 3, 7, 11, 15

  The operation timing is shown in FIG. 6B. As in the detailed timing diagram, time periods a, b, c, etc. appear along the horizontal axis. In this case, the word line signals P_even and P_odd are generated at different time periods. However, the bit line signals VBL_L and VBL_H are generated at different times. Data is written to the cells of the lines WL_4k and WL_4k + 2 in the time period a. Data is written to the cells on the lines WL_4k + 1 and WL_4k + 3 in the time period b.

  Diagrams of three other embodiments are shown in FIGS. 7A-7C. In the embodiment shown in FIG. 7A, there is an equalization circuit and a precharge circuit for each bit line pair in each array of memory cells. In the embodiment shown in FIG. 7B, there is a common equalization circuit for the bit lines in the two arrays connected to each sense amplifier. In the embodiment shown in FIG. 7B, there is a precharge circuit for each bit line pair in each array of memory cells. In the embodiment shown in FIG. 7C, there is a common equalization circuit and a common precharge circuit for the bit lines in the two arrays connected to each sense amplifier.

  In summary, in the embodiment shown in FIG. 7A, there is an equalization circuit and a precharge circuit for the bit line pair in each array of cells. In the embodiment of FIG. 7B, there is a common equalization circuit. In the embodiment of FIG. 7C, there is a common equalization circuit and a common precharge circuit.

  The configuration of the equalization circuit and the precharge circuit in FIGS. 7A to 7C will be described later. It should be noted that although only one precharge and equalization circuit is described in detail, such description applies equally to equalization and precharge circuits at other locations. Each individual precharge circuit and each individual equalization circuit is comprised of conventional transistors coupled as shown.

  The embodiment shown in FIG. 7A includes DRAM cell arrays 701, 706, and 708. The sense amplifier 705 is disposed between the arrays 701 and 706. The sense amplifier 707 is disposed between the arrays 706 and 708. The memory cell array 701 includes a precharge circuit 702A and an equalization circuit 703A. The memory cell array 706 includes a precharge circuit 702B and an equalization circuit 703B. The precharge circuit is connected to the low voltage line VBL_L and the high voltage line VBL_H described above. A precharge circuit and an equalization circuit having the same structure are arranged between the arrays 706 and 708.

  The embodiment shown in FIG. 7B includes DRAM cell arrays 721, 725, and 728. The sense amplifier 722 is disposed between the arrays 721 and 725. The sense amplifier 726 is disposed between the arrays 725 and 728. Precharge circuit 722 A is associated with array 721 and precharge circuit 722 B is associated with array 725. The equalization circuit 723 is provided to both the memory cell arrays 721 and 725. A precharge circuit and an equalization circuit having the same structure appear between the arrays 725 and 728.

  The embodiment shown in FIG. 7C includes DRAM cell arrays 751, 755, and 759. The sense amplifier 752 is arranged between the arrays 751 and 755. The sense amplifier 756 is disposed between the arrays 755 and 759. The precharge circuit 753A is disposed between the memory cell arrays 751 and 755, and is provided to both the memory cell arrays. Similarly, the equalization circuit 754A is disposed between the memory cell arrays 751 and 755, and is provided to both the memory cell arrays. Precharge circuit 753B and equalization circuit 754B are provided to arrays 755 and 759.

  3 and 7A to 7C, only three memory cell array blocks are shown. The three memory cell array blocks are shown for convenience of explanation. Other embodiments may include a variety of other numbers of memory cell array blocks. Furthermore, it should be noted that the overall size of the memory is not shown in the drawings. The remaining part of the memory is structured similarly to the part of the memory described.

  Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and various modifications and equivalent other embodiments may be made by those skilled in the art. You will understand that. Therefore, the true technical protection scope of the present invention must be determined by the technical idea of the claims.

  The present invention is applicable to a technical field related to a semiconductor memory device that can effectively apply a sensing stress to a twist bit line.

It is a diagram of a simple conventional DRAM. It is a diagram illustrating the problem that hinders efficient memory testing. It is a diagram illustrating the problem that hinders efficient memory testing. It is a block diagram of a 1st embodiment. It is a diagram which shows the voltage of the adjacent cell in 1st Embodiment. It is a diagram which shows the voltage of the adjacent cell in 1st Embodiment. It is a figure explaining the structure of a test mode. It is a figure explaining the structure of a test mode. It is a timing diagram. It is a timing diagram. It is a diagram explaining other embodiment of this invention. It is a diagram explaining other embodiment of this invention. It is a diagram explaining other embodiment of this invention.

Explanation of symbols

302, 304, 305 DRAM array block 311-316 Sense amplifier 322 Equalizer EQ_A, EQ_B Equalizer control signal VBL_L Low voltage line VBL_H High voltage line PRE_A, PRE_B Precharge control signal

Claims (20)

A plurality of memory cells arranged in rows and columns to form a matrix and divided into a plurality of memory cell blocks;
A plurality of word lines arranged in a first direction of the matrix;
A plurality of bit lines arranged in a second direction of the matrix, the first and second bit lines forming a bit line pair;
One of the memory cells arranged at an intersection of the word line and one of the first and second bit lines;
Another pair of the bit lines twisted between adjacent arrays of the memory cells;
A sense amplifier connected to each bit line pair for sensing a voltage difference between the bit lines;
A semiconductor memory device comprising: a plurality of precharge circuits for precharging two bit lines in each bit line pair to different voltages. The precharge circuit is
The semiconductor memory device according to claim 1, wherein the semiconductor memory device is disposed between the bit line pair. The semiconductor memory device includes:
2. The semiconductor memory device according to claim 1, wherein the precharge circuit precharges two bit lines in each bit line pair to different voltages during a sense test. The semiconductor memory device includes:
4. The semiconductor memory device according to claim 3, wherein all word lines are simultaneously enabled during the sense test. The semiconductor memory device includes:
5. The semiconductor memory device according to claim 4, wherein every memory cell sensed by each bit line is precharged to the same voltage during the sense test. The memory cell is
The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a DRAM memory cell. The semiconductor memory device includes:
The semiconductor memory device of claim 1, further comprising an equalization circuit associated with each bit line. The semiconductor memory device includes:
8. The semiconductor memory device of claim 7, further comprising a separate precharge circuit and a separate equalization circuit associated with each memory array. The semiconductor memory device includes:
8. The semiconductor memory device according to claim 7, further comprising: a separate precharge circuit associated with each memory array; and an equalization circuit shared by the bit lines in the two memory arrays. The semiconductor memory device includes:
8. The semiconductor memory device according to claim 7, wherein the precharge circuit and the equalization circuit are shared by the bit lines in two memory arrays. The semiconductor memory device includes:
The precharge circuit is arranged in two sets of prechargers, and the two lines in each bit line pair are connected to prechargers in different sets of prechargers;
2. The semiconductor memory device according to claim 1, wherein the set of prechargers can precharge the two bit lines in the bit line pairs to different voltages during a test operation. A plurality of memory cells, a plurality of word lines, a bit line pair having two bit lines, and a sense amplifier for sensing a voltage of the bit line pair, the bit line pair being twisted between adjacent memory cell arrays In a semiconductor memory device
A precharge circuit disposed between adjacent bit line pairs;
Each precharge circuit is connected to one bitline in the two adjacent bitline pairs, and the precharge circuit charges two bitlines of each bitline pair during a test operation,
A semiconductor memory device, wherein all the word lines are simultaneously activated during a burn-in sense test, and a voltage appears on every bit line. The semiconductor memory device includes:
13. The semiconductor memory device according to claim 12, wherein the precharge circuit charges the bit line to the same precharge voltage during a normal operation. The semiconductor memory device includes:
13. The semiconductor memory device of claim 12, further comprising an equalization circuit for each of the bit line pairs. The semiconductor memory device includes:
15. The semiconductor memory device of claim 14, comprising a separate set of precharge circuits associated with each memory array and a separate set of equalization circuits. The semiconductor memory device includes:
15. The semiconductor memory device of claim 14, comprising a separate set of precharge circuits associated with each memory array and an equalization circuit shared by bit lines in the two memory arrays. . The semiconductor memory device includes:
The semiconductor memory device according to claim 14, wherein the precharge circuit and the equalization circuit are shared by the bit lines in two memory arrays. A memory cell located at the intersection of a word line and a bit line;
The bit line comprising a bit line pair having a bit line and a bit bar line;
Each word line intersecting the memory cell on the bit line and the bit bar line in the bit line pair;
A memory cell array in which the memory cells are arranged and having a plurality of cell blocks;
Each bit line pair twisted between the array blocks and having a sense amplifier;
A precharge circuit that is connected to one bit line in the two bit line pairs and is charged to charge the two bit lines in each bit line pair to different voltages during a burn-in sense test. A semiconductor memory device. The precharge circuit is
During a selected test operation, charging the bit lines in each bit line pair to a different voltage;
19. The semiconductor memory device according to claim 18, wherein the bit lines in each of the bit line pairs are precharged to the same voltage during a normal test operation. The semiconductor memory device includes:
19. The semiconductor memory device of claim 18, further comprising: a logic circuit that simultaneously activates every even word line and every odd word line during a write test operation; and two test pads.

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