JP2004355720A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress test costs by enabling a DC burn-in test using an equalizer circuit in place of a dynamic burn-in test. <P>SOLUTION: A plurality of bit lines for inputting/outputting data for a memory cell 1 arranged in a matrix form are constituted of a plurality of bit line pairs BLP1 to BLP4 repeatedly arranged by setting two bit lines connected to the same sense amplifier as a pair. The two bit lines constituting the bit line pair are connected to different voltage supply lines 14 and 15 through bit line connection control transistors 11 and 12. Thus, the freedom of setting a burn-in voltage level is high, and a burn-in voltage (electric stress) is applied among all the bit lines. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to, for example, a semiconductor memory device capable of applying a DC electrical stress between bit lines as a test instead of a dynamic burn-in test and screening for bit line workability defects.
[0002]
[Prior art]
With the miniaturization of semiconductor integrated circuits, there is an increasing concern that insulation failure occurs in and between elements. There is known an accelerated test in which not only a defective element but also an element having a high probability of becoming defective can be detected from the beginning by applying an electric stress when screening for this defect.
[0003]
For example, in the field of semiconductor memory devices in which extremely fine elements such as DRAMs are integrated, a wafer burn-in (Wafer Burn In) stress test for performing a stress acceleration test on a semiconductor chip at a wafer level has been introduced.
As an example of a wafer burn-in stress test, a higher voltage may be applied to the gate oxide film of the transistors that make up the memory cell array than during normal operation to apply electrical stress, resulting in insulation failure or the possibility of insulation failure leading to failure. A test is known in which a transistor having a high value is placed in a state in which it can be screened. In addition, when a voltage higher than that during normal operation is applied between the wiring intervals formed in the minimum size of the process, for example, the gate electrodes of the transistors constituting the memory cell array, the processability between the gate electrodes can be similarly screened. Testing is known.
[0004]
FIG. 1 shows an example in which a burn-in stress test of a gate oxide film is applied to a memory cell array having a twisted bit line structure.
In the memory cell array 1, near the intersection of a plurality of bit lines and a plurality of word lines, a memory cell MC shown in FIG. 1B is formed. In the case of a DRAM, the memory cell MC includes a cell selection transistor ST having a gate connected to a word line WL and a drain connected to one of bit lines BLi (i = 1, 2, 3, 4,...); The memory capacitor CAP is connected between the source of the select transistor ST and a predetermined voltage supply line (not shown).
The bit lines for inputting / outputting data to / from the memory cell MC are configured by a pair of bit lines connected to the sense amplifier (S / A) 2 by combining two bit lines. In the illustrated example, a bit line pair BLP1 is constituted by the bit line BL1 and the bit auxiliary line / BL1. Similarly, bit line pair BLP2 is formed from bit line BL2 and bit auxiliary line / BL2, bit line pair BLP3 is formed from bit line BL3 and bit auxiliary line / BL3, and bit line BL4 and bit auxiliary line / BL4 are formed. These form a bit line pair BLP4. As the bit line pairs, for example, only even-numbered bit line pairs (BLP2, BLP4,...) Are twisted bit line pairs in which the bit line positions are switched within each bit line pair. As a result, noise between adjacent bit line pairs is canceled to reduce the noise level, thereby preventing malfunction.
[0005]
Each bit line pair is provided with a precharge and equalize circuit (hereinafter simply referred to as an equalize circuit) 100 having the same configuration. The equalizing circuit 100 includes a first transistor 101 connected between an equalizing voltage (equalizing level: V_Eq) supply line 104 and a bit line BLi, and an equalizing voltage supply line 104 between the equalizing voltage supply line 104 and a bit auxiliary line / BLi. A second transistor 102 is connected, and a third transistor 103 is connected between the bit line BLi and the auxiliary bit line / BLi. These three transistors 101 to 103 are controlled by an equalization control signal (Eq_On) applied to a common equalization control line 105.
[0006]
This semiconductor memory device is provided with a burn-in control circuit (WBI. CONT) 110 for controlling a voltage required at the time of wafer burn-in. When the burn-in control signal (WBI_On) is input, the burn-in control circuit 110 activates (On) the equalize control signal (Eq_On) while keeping the sense amplifier control signal (SA_On) inactive (Off). The equalizing level (V_Eq) is set to a “low (L)” level (eg, a GND level), and the word line applied voltage level (V_WL) is set to a “high (H)” level (a level higher than the level during normal operation). . As a result, an “H” level voltage (V_WL) is applied to the portion indicated by the arrow with a circle in FIG. 1B, whereby an electrical stress (burn-in voltage) is applied to the gate oxide film.
[0007]
As memory cells have been miniaturized as in recent years, it is not sufficient to apply a voltage to this gate oxide film alone as burn-in, and it is necessary to apply a voltage stress between gate electrodes and further between bit lines. In the above-described burn-in method, the stress between the gate electrodes can be applied simultaneously if different potentials of “H” and “L” are alternately applied to the word line, but the potential of the bit line is all “L (GND)” level. Since it is constant, no stress can be applied between the bit lines.
[0008]
FIG. 2 shows a burn-in method corresponding to the application of stress between bit lines. In this method, a known voltage application method (for example, see Patent Document 1) is applied to a memory having a twist bit line structure.
As shown in FIG. 2A, the configuration of the equalizing circuit 100 for controlling the bit line voltage of the memory cell array 1 and the connection relationship between the voltage and the control signal supply lines 104 and 105 are the same as those in FIG. Is the same as In this method, the method of providing the equalizing voltage (V_Eq) is different from the above method. The burn-in control circuit 120 of this example shown in FIG. 2B activates (On) the equalization control signal (Eq_On) while the sense amplifier control signal (SA_On) is inactive (Off), and sets the even-numbered Equalization level (V1_Eq) supplied to the bit line pair is set to "L" level (for example, GND level), and the equalization level (V2_Eq) supplied to odd-numbered bit line pairs is set to "H" level (for example, power supply voltage Vcc). . Also, the level (V_WL) of the word line applied voltage is set to the “H” level (a level higher than the level during normal operation). As a result, an electric stress is applied between the odd-numbered bit line pair and the even-numbered bit line pair, and the “L” level voltage (V1_Eq) belonging to the selected memory cell row is applied. In the memory cells connected to the even-numbered bit line pairs, an electrical stress is applied to the gate oxide film.
Next, the magnitude relationship between the potentials of the equalizing levels (V1_Eq) and (V2_Eq) is exchanged, and the above-described sequence of the voltage supply to the bit lines and the word lines is repeated. As a result, electrical stress is applied to the gate oxide film also in the memory cell rows connected to the odd-numbered bit line pairs.
[0009]
[Patent Document 1]
JP-A-10-340598
[0010]
[Problems to be solved by the invention]
However, in the method shown in FIG. 2, the potential between the two bit lines constituting the bit line pair is always fixed, and the bit line is indicated by the "x" arrow shown in FIG. No electrical stress can be applied in between.
[0011]
Therefore, conventionally, stress acceleration is performed by a burn-in test (dynamic burn-in) close to the actual operation of the DRAM, and screening for a portion with poor workability is performed by a memory tester.
[0012]
FIG. 3 shows a diagram to which bit line potentials in the dynamic burn-in test are additionally shown.
In the dynamic burn-in test, a bit line voltage is not supplied by the equalizing circuit 100, but a combination of test voltages (test pattern) is supplied to the bit lines as data from the sense amplifier 2 side by a normal writing circuit (not shown). I do.
For example, using the first test pattern, a burn-in voltage of “H” level is applied to the bit lines (BL1, BL2, BL3, BL4,...) Of each bit line pair, and the hit auxiliary lines (/ BL1, / BL2, / BL3, / BL4,...) Are applied with an “L” level burn-in voltage. At this time, adjacent cell complementary lines (/ BL1 and / BL2, / BL3 and / BL4,...) And adjacent bit lines (BL2 and BL3) in the cell array region 1R on the right side of the drawing from the bit line twist position. Have the same potential, and no electrical stress is applied during that time.
Next, the burn-in voltage is applied by using a test pattern in which the burn-in voltages “H” and “L” are exchanged in the even-numbered bit line pairs of the twisted structure. The potential at this time is shown in parentheses in FIG. As shown, at this time, in the cell array region 1L on the left side of the drawing from the twist position of the bit line, adjacent bit complementary lines and bit lines (/ BL1 and BL2, / BL2 and BL3, / BL3 and BL4,...) Have the same potential, and no electrical stress is applied during that time.
By a combination of these two types of test voltages, a test pattern is formed in which electric stress is applied to a wiring portion to which no electric stress is applied, and thereafter, the test pattern is repeated to increase stress application efficiency. The application of stress to the gate oxide film is performed by appropriately applying an “H” level voltage to the word line in the above sequence.
[0013]
In such a dynamic burn-in test, a large number of combinations (test patterns) of bit line voltages are prepared and a complicated test is performed, so that there is a disadvantage that a test time is increased and a test throughput is reduced.
In addition, since a high-performance tester having a memory function for generating test patterns and controlling the entire DRAM is required, there is a disadvantage that an initial investment becomes large, and the test cost is reduced due to a decrease in throughput. Has led to a rise.
[0014]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device having a configuration in which a DC burn-in test using an equalizing circuit can be performed in place of a dynamic burn-in test and test cost can be suppressed.
[0015]
[Means for Solving the Problems]
In the semiconductor memory device according to the present invention, a plurality of bit lines for inputting and outputting data to and from memory cells arranged in a matrix are repeatedly arranged as pairs of two bit lines connected to the same sense amplifier. It is composed of a plurality of bit line pairs. Also, each of the two bit lines forming the bit line pair is connected to a different voltage supply line via a bit line connection control transistor.
When an equalizing transistor for short-circuiting between two bit lines in a bit line pair is provided, the control line of the transistor for controlling bit line connection is preferably provided separately from the control line of the equalizing transistor.
[0016]
Preferably, a plurality of bit lines including four bit lines constituting two adjacent bit line pairs are used as a unit, and when voltage application of a plurality of combinations is repeated, the voltage is applied within the unit and between the adjacent units. And a burn-in control circuit for repeatedly applying different combinations of voltages to a plurality of bit line pairs so that a predetermined burn-in voltage is applied between all the bit lines.
The burn-in control circuit is preferably connected to a pad for inputting a mode switching signal for normal operation and test operation, and to an input pad for at least one control signal among control signals applied to the semiconductor memory device during normal operation. Have been. When the mode switching signal indicates the test mode, the burn-in control circuit decodes a bit signal input from an input pad of at least one control signal, and responds to the result of the decoding among at least four bit lines. This is a circuit for applying a high-level voltage to a combination of bit lines.
[0017]
In the semiconductor memory device according to the present invention configured as described above, a signal that is input to a built-in burn-in control circuit is input to a combination of voltages corresponding to a test pattern generated by an expensive tester having a memory function. Generated by decoding. When a mode switching signal is input to a pad connected to the burn-in control circuit and the signal indicates the test mode, the semiconductor memory device stops the normal operation mode and enters the test mode. In the test mode, a bit signal input from another pad is decoded by the burn-in control circuit, and this bit signal is supplied using an input pad of various control signals provided in a normal operation. As a result of decoding by the burn-in control circuit, a combination of burn-in voltages corresponding to a so-called test pattern is generated in units of a plurality of bit lines including four bit lines constituting two adjacent bit line pairs. The burn-in control circuit is configured to apply a predetermined burn-in voltage between all the bit lines within the unit including at least four bit lines and between adjacent units when the application of the generated voltage is repeated. , Voltage generation and application are repeated. Therefore, electrical stress is applied between all the bit lines.
In order to apply an electrical stress between all the bit lines in such a DC test, in the present invention, each of the two bit lines forming the bit line pair has a different voltage via a bit line connection control transistor. Connected to the supply line. When an equalizing transistor for short-circuiting between two bit lines in a bit line pair is provided, a control line of a transistor for controlling bit line connection is provided separately from a control line of the equalizing transistor. As a result, once set voltages of different levels are not equalized and do not change to the same potential.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings, taking a DRAM as an example.
[0019]
[First Embodiment]
FIG. 4 shows a configuration of the semiconductor memory device according to the first embodiment.
In the memory cell array 1, near the intersection of a plurality of bit lines and a plurality of word lines, a memory cell MC shown in FIG. 4B is formed. In the case of a DRAM, the memory cell MC includes a cell selection transistor ST having a gate connected to a word line WL and a drain connected to one of bit lines BLi (i = 1, 2, 3, 4,...); The memory capacitor CAP is connected between the source of the select transistor ST and a predetermined voltage supply line (not shown).
The bit lines for inputting / outputting data to / from the memory cell MC are configured by a pair of bit lines connected to the sense amplifier (S / A) 2 by combining two bit lines. In the illustrated example, a bit line pair BLP1 is constituted by the bit line BL1 and the bit auxiliary line / BL1. Similarly, bit line pair BLP2 is formed from bit line BL2 and bit auxiliary line / BL2, bit line pair BLP3 is formed from bit line BL3 and bit auxiliary line / BL3, and bit line BL4 and bit auxiliary line / BL4 are formed. These form a bit line pair BLP4.
[0020]
Each bit line pair is provided with a precharge / equalize circuit (hereinafter simply referred to as an equalize circuit) 10 having the same configuration. The equalizing circuit 10 is provided, for example, in a control circuit provided in a normal memory device.
In the present embodiment, a line for supplying a voltage at the time of precharge or burn-in to the equalizing circuit is separated on the bit line side and the bit auxiliary line side, and is also separated from the equalizing control line. Different from circuit.
The equalizing circuit 10 includes a first transistor 11 connected between a supply line 14 for a burn-in voltage level (V_Eq) and a bit line BLi, a supply line 15 for a burn-in voltage level (/ V_Eq), and a bit auxiliary line / BLi. And a third transistor 13 connected between the bit line BLi and the auxiliary bit line / BLi. The burn-in voltage levels (V-Eq) and (/ V_Eq) are complementary voltages. When one of the burn-in voltages is at the "H" level, the other is at the "L" level ground potential GND.
Of these three transistors 11 to 13, the first and second transistors 11 and 12 for controlling bit line connection at the time of precharge or burn-in are controlled by a common bit line connection control line 16, and are used for equalization. The third transistor 13 is controlled by an equalization control line 17. At this time, the signal applied to the bit line connection control line 16 is called a precharge control signal (Pre_On) for convenience, and the signal applied to the equalization control line 17 is called an equalization control signal (Eq_On).
[0021]
This semiconductor memory device is provided with a burn-in control circuit (WBI. CONT) 20 for generating and controlling a required voltage during wafer burn-in. When the burn-in control signal (WBI_On) is input and detected from the pad 21, the burn-in control circuit 20 stops the normal operation mode and switches to the test mode. In the test mode, when the bit signal SB input from the pad 22 is, for example, “1”, the burn-in control circuit 20 keeps the sense amplifier control signal (SA_On) inactive (Off) and the equalize control signal (Eq_On). ) Is activated (On), the burn-in voltage level (V_Eq) is at “H” level, the burn-in voltage level (/ V_Eq) is at “L” level, and the applied voltage levels (V_WL) of all word lines are at “H”. Set to the level (higher than the level during normal operation). Thereby, as shown in FIG. 4A, “H”, “L”, “H”, “L”, “H”, “L”, “H”, “L”, Are set in the bit line pairs, whereby the burn-in voltage is applied between all the bit lines. At this time, electrical stress (gate burn-in voltage) is applied to the gate oxide film of the memory cell connected to the bit line having the potential “L”.
[0022]
Next, when the burn-in control circuit 20 detects "0" of the bit signal SB input from the pad 22, it inverts the levels "H" and "L" of the burn-in voltage levels (V_Eq) and (/ V_Eq). In a similar sequence, the bit line voltage is set again. As a result, as shown in parentheses in FIG. 4A, "L", "H", "L", "H", "L", "H", "L", "L" are sequentially provided from the bit line BL1. H ”... Are set to the bit line pairs, whereby a burn-in voltage is applied between all the bit lines. At this time, electrical stress (gate burn-in voltage) is applied to the gate oxide film of the memory cell connected to the bit line having the potential “L”.
By these two burn-in voltage settings, an electric stress is applied between all the bit lines and the gate oxide films of all the cells.
Although the voltage level applied to all the word lines is set to the “H” level, an operation of alternately setting the adjacent word lines to “H” and “L” can be performed. This makes it possible to apply stress simultaneously between the bit lines and between the gate electrodes, as well as between the gate electrodes.
[0023]
With such a simple control, it is possible to apply DC stress between all the bit lines, and the test time at this time is shorter than that of the conventional dynamic burn-in test, and the power consumption is small. Further, a high-performance and expensive tester such as a conventional dynamic burn-in test is not required.
Note that the burn-in control circuit 20 can perform these two sequences in the test mode in accordance with a predetermined program procedure. In this case, it is unnecessary to input the bit signal SB via the pad 22. Become. Further, even when the bit signal SB is input, the bit signal SB is supplied by using the control signal input pad 22 in the normal operation in which the operation is stopped, so that the number of control pins does not increase.
[0024]
[Second embodiment]
The second embodiment is a case where the present invention is provided to a DRAM having a memory cell array having a twisted bit line structure.
[0025]
FIG. 5 shows a configuration of the semiconductor memory device according to the second embodiment.
This semiconductor memory device is different from the configuration of the first embodiment in that, for example, only the even-numbered bit line pairs (BLP2, BLP4,...) Differ from the twisted bit line pairs in which the bit line positions are exchanged within each bit line pair. It is becoming. As a result, noise between adjacent bit line pairs is canceled to reduce the noise level, thereby preventing malfunction. By employing the twist bit line structure, the generation of the burn-in voltage level is slightly more complicated than in the first embodiment, and accordingly, the burn-in control circuit 30 of the present example shown in FIG. I have. Other configurations are the same as those of the first embodiment, and a description thereof will not be repeated. However, the equalizing voltage level to be given differs depending on whether the bit line or the bit auxiliary line belongs to the even-numbered bit line pair or the odd-numbered bit line pair. Here, the burn-in voltage level applied to the bit lines (BL1, BL3,...) Of the odd-numbered bit line pairs of the non-twist structure is (V1_Eq_T), and the burn-in voltage applied to the auxiliary bit lines (/ BL1, / BL3,. The level is given to (V1_Eq_B), the burn-in voltage level given to the bit lines (BL2, BL4,...) Of the even-numbered bit line pairs of the twisted structure is given to (V2_Eq_T), and the bit complement lines (/ BL2, / BL4,. The burn-in voltage level is defined as (V2_Eq_B). In the bit line pairs of the even-numbered columns, the connection relationship between the sense amplifier 2 and the supply lines 14 and 15 of the burn-in voltage level is replaced with that in FIG. In the twisted structure, which bit line is used as the bit line or as the bit auxiliary line is arbitrary. In this case, only the twisted bit line pair is connected to the lower node of the sense amplifier 2 and the upper bit line is connected to the upper node. Corresponds to the fact that the bit supplementary line is connected to the node.
[0026]
Here, two examples of the method of generating (decoding) the voltage of the burn-in control circuit of the present example, the method shown in FIG. 6 and the method shown in FIG. 7, are shown.
In the method shown in FIG. 6, the burn-in voltage of the "H" level is applied to any one of the units in units of four bit lines constituting an odd-numbered bit line pair and an adjacent even-numbered bit line pair. Set to. For this reason, voltage application in which one of the burn-in voltage levels (V1_Eq_T, V1_Eq_B, V2_Eq_T, V2_Eq_B) is set to “H” and the other is set to “L” is performed in four combinations. Two bit signals defining four combinations are required. In this method, the burn-in voltage level is determined by a combination uniquely determined by decoding the 2-bit information indicated by the bit signals SBA and SBB.
In this method, when one bit line or bit auxiliary line is "H", two adjacent bit lines are always "L", and all bit lines and bit auxiliary lines are always "H" at least once. , A burn-in voltage is applied between all the bit lines.
[0027]
In the method shown in FIG. 7, a burn-in voltage can be applied between all the bit lines by two combinations of voltages. Therefore, the bit signal need only be SBA. FIG. 8A shows how the bit line voltage is applied when the bit signal SBA is “L”, and FIG. 8B shows how the bit line voltage is applied when the bit line signal SBA is “H”. , Respectively.
When the bit signal SBA is "L", the burn-in voltage levels (V1_Eq_T, V1_Eq_B, V2_Eq_T, V2_Eq_B) are sequentially "Vcc (H)", "GND (L)", "Vcc (H)", "GND (L)". ) ". Therefore, as shown in FIG. 8A, in the cell array region 1L, there are three places where adjacent bit lines have the same potential in the illustrated example. There are several methods for applying a burn-in voltage to these three locations, but here, this is achieved by exchanging the potential of the twisted bit line pair. As another method, there is a method of exchanging the bit line potential of the non-twist structure. In addition, although three combinations (two bit signals) are required, the bit line potential of the twisted structure is set to “H” and “H” while the bit line potential of the non-twisted structure is kept as it is, and further, “L” And "L". Or, conversely, various methods are adopted such as setting the bit line potential of the non-twisted structure to “H” and “H” and setting the potential of the bit line of the non-twisted structure to “L” and “L” while keeping the bit line potential of the twisted structure as it is. it can.
[0028]
Next, a configuration example of the burn-in control circuit will be described with reference to an example in which the sequence of FIG. 6 is achieved.
FIG. 9 is a circuit diagram of the burn-in control circuit.
The burn-in control circuit 30 is provided in the control unit of the memory together with the control circuit 40 during normal operation. Also, some functions of the row-related control circuit 50 are included in the burn-in control circuit 30. The word line selection circuit 51 in the row control circuit 50 is usually built in a row decoder.
[0029]
Burn-in control circuit 30 is roughly divided into a circuit 34 for decoding 2-bit information indicated by two bit signals SBA and SBB, and a voltage for switching and outputting power supply voltage Vcc (burn-in voltage level) and ground potential GND based on the decoding result. A supply circuit 35 and an output control circuit 36 for selecting an output terminal of the burn-in voltage level and another control signal output from the control circuit 40 and stopping the output of the burn-in voltage level during normal operation.
[0030]
The decoding circuit includes two inverters I1 and I2 and four AND gates A1 to A4. When (SBA, SBB) is (L, L), “H” is output only from AND gate A1, and when (L, H), “H” is output only from AND gate A2, and (H, L) )), "H" is output only from the AND gate A3, and (H, H), "H" is output only from the AND gate A4.
[0031]
The voltage supply circuit 35 includes four selectors S1 to S4, and the output control circuit 36 includes eight selectors S5 to S11. These selectors select the input terminal A (INA) side when the signal applied to the control terminal is "H" as shown in the explanatory diagram surrounded by the broken line in the figure, and select the selected side. An input signal is output from an output terminal (OUT). When the signal is "L", the input terminal B (INB) is selected, and an input signal on the selected side is output from the output terminal (OUT). .
The selector S1 outputs the power supply voltage Vcc (BL) at the time of burn-in when (the level of the bit signal SBA, the level of the bit signal SBB) is (H, H). This is because the burn-in control signal On (WBI_On) is " The signal is output as a burn-in voltage level (V1_Eq_T) via the selector S7 that selects the B input side at “H”. The other burn-in voltage levels are similarly output via any of the selectors S2 to S4 and any of the selectors S8 to S10.
On the other hand, when the burn-in control signal On (WBI_On) is “H”, the selector S5 sets the equalize control signal (Eq_On) to the ground potential GND (“L” level, that is, inactive level), and sets the burn-in control signal On (WBI_On). Is "L", the equalization control signal (Eq_On) output from the control circuit 40 is output as it is. Similarly, the selector S11 sets the sense amplifier control signal (SA_On) to the ground potential GND (“L” level, ie, inactive level) during burn-in, and the sense amplifier control signal (SA_On) output from the control circuit 40 during normal operation. Is output as is. The selector S6 outputs a predetermined high-level signal as a precharge control signal (Pre_On) during burn-in, and outputs the precharge control signal (Pre_On) output from the control circuit 40 as it is during normal operation. The selector S12 outputs a predetermined high-level signal as a word line voltage (V_WL) at the time of burn-in, for example, a boosted power supply voltage Vppb (WL). Is output as a word line voltage (V_WL).
With such a circuit, various voltage settings shown in FIG. 6 can be made.
[0032]
In the above-described first and second embodiments, the unit for applying a voltage to a bit line is divided into two or four systems. However, the burn-in voltage is applied in units of the other number of bit lines. It is possible. For example, if two twists are made with a combination of different bit lines among three bit lines and another bit line exists between the twisted two bit lines, these three bit lines are used as a unit. Is set as the burn-in voltage between the bit lines. In this case, if there are six combinations of adjacent bit lines, six combinations of burn-in voltage application voltages may be generated.
[0033]
According to the embodiment of the present invention, it is possible to detect a defective portion between bit lines at an early stage, to improve a test throughput accompanying a reduction in screening time, and to reduce a test cost. Further, depending on the defective part, it can be replaced by the redundant part and the chip can be relieved. As a result, an improvement in yield can be expected.
In addition, the existing control terminal input pad is used to prevent an increase in the number of control pins, and together with the improvement in the above-mentioned throughput and the reduction in test cost by not using a high-performance tester, ultimately the chip The unit price can be reduced.
[0034]
【The invention's effect】
According to the semiconductor memory device of the first aspect of the present invention, each of the two bit lines forming the bit line pair is connected to a different voltage supply line via a bit line connection control transistor. By applying voltages of different levels to this voltage supply line, a burn-in voltage can be applied between the bit line pairs. This makes it possible to apply the burn-in voltage to all the defective portions between the bit lines or to a portion where the probability of the defectiveness is high by applying the DC voltage through the transistor for controlling the connection of the bit lines, thereby performing the screening. Become. As a result, a high-performance and expensive tester such as a burn-in test by a dynamic operation is not required, and a burn-in test in which a test time can be shortened compared to a burn-in test by a dynamic operation can be performed.
[0035]
According to the semiconductor memory device of the second aspect of the present invention, when the equalizing transistor for short-circuiting between two bit lines in the bit line pair is provided, the control line of the bit line connection control transistor is connected to the equalizing transistor. Since it is provided separately from the control line, it is possible to maintain the applied state of different level voltages between the bit line pairs, and it is possible to apply the burn-in voltage.
[0036]
According to the semiconductor memory device according to the third and fourth aspects of the present invention, the semiconductor memory device has a burn-in control circuit for generating a combination of voltages for applying a burn-in voltage between all the bit lines, and is a source of the voltage generation. Since the bit signal is supplied from the input pad of the control signal used in the normal operation, it is not necessary to newly provide a bit signal pad. As a result, a burn-in test between bit lines can be performed with the number of input pins of the semiconductor memory device kept as it is. It should be noted that the burn-in control circuit is a circuit that only decodes a signal of several bits, and the increase in area is so small that it is ignored.
[Brief description of the drawings]
FIG. 1 is a circuit and block diagram showing an example in which a burn-in stress test of a gate oxide film is applied to a memory cell array having a twist bit line structure in a conventional burn-in test.
FIG. 2 is a circuit and block diagram showing a burn-in method corresponding to the application of stress between bit lines as another conventional burn-in test.
FIG. 3 is a circuit block diagram to which bit line potentials of a conventional dynamic burn-in test are added.
FIG. 4 is a circuit and block diagram showing a configuration of the semiconductor memory device according to the first embodiment of the present invention.
FIG. 5 is a circuit and block diagram showing a configuration of a semiconductor memory device according to a second embodiment of the present invention.
FIG. 6 is a chart showing voltages generated by a first method by a burn-in control circuit in a second embodiment.
FIG. 7 is a table showing voltages generated by a second method by a burn-in control circuit in the second embodiment.
8 is a diagram schematically showing the state of application of a bit line voltage when a bit signal is “L” and “H” in the case of the second method shown in FIG. 7;
FIG. 9 is a circuit diagram showing a configuration example of a burn-in control circuit in a second embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Sense amplifier, 10 ... Equalize circuit, 11 and 12 ... Bit line connection control transistor, 13 ... Equalize transistor, 14 and 15 ... Bit line voltage (burn-in voltage level) supply line, 16 ... Precharge control line, 17 ... Equalize control line, 20, 30 ... Burn-in control circuit, 21, 22, 31-33 ... Pad

Claims (6)

A semiconductor memory device having a plurality of bit lines for inputting and outputting data to and from memory cells arranged in a matrix,
The plurality of bit lines are constituted by a plurality of bit line pairs in which two bit lines connected to the same sense amplifier are repeatedly arranged as a pair,
A semiconductor memory device in which each of the two bit lines forming a bit line pair is connected to a different voltage supply line via a bit line connection control transistor. When there is an equalizing transistor for short-circuiting between two bit lines in the pair of bit lines, a control line of the transistor for controlling bit line connection is provided separately from a control line of the equalizing transistor. 2. The semiconductor memory device according to claim 1. When a plurality of combinations of voltage application are repeated using a plurality of bit lines including four bit lines constituting two adjacent bit line pairs as a unit, all the bit lines within the unit and between the adjacent units are repeated. 2. The semiconductor memory device according to claim 1, further comprising a burn-in control circuit that repeatedly applies a different combination of voltages to the plurality of bit line pairs so that a predetermined burn-in voltage is applied therebetween. The burn-in control circuit is connected to a pad for inputting a mode switching signal for normal operation and test operation, and an input pad for at least one control signal among control signals applied to the semiconductor memory device during normal operation, When the mode switching signal indicates the test mode, a bit signal input from the input pad of the at least one control signal is decoded, and a bit line of a combination according to the decoding result among the at least four bit lines is decoded. 4. The semiconductor memory device according to claim 3, wherein the semiconductor memory device is a circuit for applying a high-level voltage to the circuit. The plurality of bit line pairs has a twisted bit line pair in which two bit lines cross in the middle and the bit line positions are switched,
When the twisted bit line pair and the non-twisted bit line pair are adjacent to each other, a plurality of combinations are made in units of a plurality of bit lines including four bit lines forming the two bit line pairs. Are repeatedly applied to the plurality of bit line pairs so that a predetermined burn-in voltage is applied between all the bit lines within the unit and between adjacent units when the voltage application is repeated. 2. The semiconductor memory device according to claim 1, further comprising a burn-in control circuit. The burn-in control circuit is connected to a pad for inputting a mode switching signal for normal operation and test operation, and an input pad for at least one control signal among control signals applied to the semiconductor memory device during normal operation, When the mode switching signal indicates the test mode, a bit signal input from the input pad of the at least one control signal is decoded, and a bit line of a combination according to the decoding result among the at least four bit lines is decoded. 6. The semiconductor memory device according to claim 5, wherein said semiconductor memory device is a circuit for applying a high-level voltage to said circuit.

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