KR100881189B1 - Line detection circuit for detecting weak line - Google Patents

Abstract

The present invention is directed to a wiring detection circuit for detecting a weak wiring. The wiring detection circuit includes a plurality of wirings and first drivers disposed at one end of each of the wirings and sequentially driving corresponding wirings in a first voltage or a second voltage in response to the plurality of control signals. . The wiring detection circuit includes a second driver disposed at the other end of each of the wirings and drives the wirings to the second voltage in response to the stress signal. Since the wiring detection circuit screens whether wirings are defective by sequentially generated control signals, it is easy to detect a weak wiring. In addition, the wire detection circuitry filters out early defects that may be present in contacts or via holes in long wires connected by metal jumpers.

Wiring detection circuit, weak wiring, stress, first and second drivers, first power supply, second power supply, third power supply

Description

Line detection circuit for detecting weak line

1 is a view illustrating whether wirings are defective.

2 is a diagram for explaining a wiring detection circuit according to the first embodiment of the present invention.

3 is a diagram for explaining a wiring detection circuit according to the second embodiment of the present invention.

4 is a diagram for explaining a wiring detection circuit according to the third embodiment of the present invention.

5 is a diagram for explaining a wiring detection circuit according to the fourth embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to circuits for detecting fragile wiring.

As semiconductor devices are highly integrated, the widths of the wirings and the gaps between the wirings become narrower. Accordingly, test methods for detecting whether the wirings are defective are considered.

In general, semiconductor devices are classified into initial failures, incidental failures, and wear-out failure periods when the defects are listed in chronological order. . The initial failure is a defect caused during the manufacturing process of the semiconductor device, which is certainly filtered out during the testing of the semiconductor device. As the semiconductor device is used and operated, ancillary defects occur, and as the life of the semiconductor device expires, it is treated as abrasion failure.

Preferably, the semiconductor device should be used at a time when an accompanying failure occurs. In order to provide a reliable semiconductor device, there is a burn-in test method that accelerates the operation of a semiconductor device for a certain time to make it out of date and detect whether it is defective. The burn-in test method operates the semiconductor device in a high temperature and high voltage state to lead to early wear failure of the semiconductor device.

In FIG. 1, a plurality of interconnects 110, 120, 130 are arranged on a fabricated processed product, such as a memory cell array, formed on a semiconductor substrate. The first wiring 110 has a width of a normal wiring. Since the second wiring 120 is in an open state A, it is filtered out as an initial failure. The third wiring 130 is formed with an uneven wiring width (B). The third wiring 130 is not filtered due to an initial failure, but causes an accessory failure or a wear failure shortly after shipment of the product, leading to a failure in reliability of a semiconductor device.

On the other hand, the burn-in test method of the wiring, such as the third wiring 130, there is a method to form a current path in the rising section and the falling section of the stress application signal. This method has a problem in that the current duty becomes 5; 5 so that the stress applying effect is not large.

SUMMARY OF THE INVENTION An object of the present invention is to provide a wiring detection circuit which can increase the stress application effect on a weak wiring.

In order to achieve the above object, a wiring detection circuit according to an aspect of the present invention, the first drive unit is disposed at one end of one wiring and drives the wiring to the first voltage or the second voltage in response to a control signal; And a second driver disposed at the other end of the wire and driving the wire at a second voltage in response to a stress signal.

According to embodiments of the present invention, the first voltage may be set to the power supply voltage and the second voltage to the ground voltage.

According to the embodiments of the present invention, the first driver includes a PMOS transistor having a control signal connected to the gate thereof, a first voltage connected to the source thereof, and one side of the wiring connected to the drain thereof; And an NMOS transistor connected to the gate, the second voltage connected to the source thereof, and one side of the wiring connected to the drain thereof.

According to embodiments of the present invention, the second driver may be configured as an NMOS transistor having a stress signal connected to the gate thereof, a second voltage connected to the source thereof, and the other side of the wiring connected to the drain thereof. .

According to embodiments of the present invention, the control signal and the stress signal may be provided in a burn-in test mode.

According to embodiments of the present invention, the wiring may have a structure in which the first conductive layer and the second conductive layer are connected to each other through a contact or via hole.

In accordance with embodiments of the present invention, the wiring can be used to select the bit lines of the memory cell array.

In order to achieve the above object, a wiring detection circuit according to another aspect of the present invention, the first drive unit disposed at one end of one wiring and for driving the wiring to the first voltage or the second voltage in response to a control signal; And a second driver disposed at the other end of the wiring and driving the wiring to a third voltage in response to a stress signal.

According to embodiments of the present invention, the first voltage may be set to a boosted voltage higher than the power supply voltage, the second voltage to the ground voltage, and the third voltage to the power supply voltage.

According to embodiments of the present disclosure, the second driver may be configured as a PMOS transistor having a stress signal connected to the gate thereof, a second voltage connected to the source thereof, and the other side of the wiring connected to the drain thereof. .

In order to achieve the above object, a wiring detection circuit according to another aspect of the present invention is arranged at one end of each of a plurality of wires and wires and sequentially corresponding to each of the plurality of control signals. First driving parts driving at a first voltage or a second voltage, and second driving parts disposed at the other end of each wiring line and driving corresponding wirings at a second voltage in response to a stress signal.

In order to achieve the above object, a wiring detection circuit according to still another aspect of the present invention is arranged at one end of each of a plurality of wirings and wirings and sequentially corresponding to each of the plurality of control signals. First driving units driving the first voltage or the second voltage, and second driving units disposed at the other end of each of the wirings and driving the corresponding wirings to the third voltage in response to the stress signal.

Therefore, the wiring detection circuit of the present invention, in the wafer burn-in test mode or the package burn-in test mode, applies a strong current to the wirings for a short time to increase the stress effect. Further, since the wiring detection circuit screens whether the wirings are defective by sequentially generated control signals, it is easy to detect a weak wiring. In addition, the wire detection circuitry filters out early defects that may be present in contacts or via holes in long wires connected by metal jumpers.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings that describe exemplary embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

2 is a diagram for explaining a wiring detection circuit according to the first embodiment of the present invention. Referring to FIG. 2, a plurality of wirings 210, 220, and 330 are arranged on a semiconductor substrate, for example, on a pattern 100 such as a memory cell array. The wirings 210, 220, and 230 may be lines for selecting word lines of the memory cell array or lines for selecting bit lines. The wiring detection circuit 200 is connected to the wirings 210, 220, and 230 between the first driving units 212, 222, and 232 and the second driving units 218, 228, and 238. The first drivers 212, 222, and 223 and the second drivers 218, 228, and 238 are disposed at both ends of the wirings 210, 220, and 230, respectively.

The first drivers 212, 222, and 232 may be column select line drivers or word line drivers. In the present exemplary embodiment, the first drivers 212, 222, and 232 are column select line drivers, and the wirings 210, 220, and 230 are column select lines. It is apparent to those skilled in the art that the column select line driver selectively connects a predetermined bit line in the memory cell array with a bit line sense amplifier in response to the column select signal.

Typically, the first driver 212 drives the first wiring 210 in response to the first control signal C [0], and the first PMOS transistor 214 and the first NMOS transistor 216. It consists of. In the first PMOS transistor 214, a power supply voltage VDD is connected to a source thereof, a first control signal C [0] is connected to a gate thereof, and a first wiring 210 is connected to a drain thereof. . In the first NMOS transistor 216, a first wire 210 is connected to a drain thereof, a first control signal C [0] is connected to a gate thereof, and a ground voltage VSS is connected to a source thereof. . The second driver 218 is configured as an NMOS transistor connected between the first wiring 210 and the ground voltage VSS and to which a stress signal STRESS is applied to the gate thereof.

Each of the remaining first drivers 222 and 232 drives the second and third wires 220 and 230 in response to the second and third control signals C [1] and C [2]. do. The first to third control signals C [0], C [1], and C [2] correspond to column select signals.

The wiring detection circuit 200 is provided with the first to third control signals C [0] -C [2] sequentially supplied to logic low when in the test mode, for example, in the wafer burn-in test mode, and under stress. The signal STRESS is applied to logic high. The first to third wires 210 to 230 are connected from the power supply voltage VDD of the first drivers 212, 222, and 232 to the ground voltage VSS of the second drivers 218, 228, and 238. Current paths are formed sequentially. In the first to third wirings 210 to 230, a strong current flows for a short time, thereby increasing the stress effect. Therefore, the wiring with the weak part C, such as the second wiring 220, is opened by a strong current and is treated as a defect. In addition, since the wire detection circuit 200 sequentially tests whether the first to third wires 210 to 230 are defective, it is easy to detect a bad wire.

3 is a diagram for explaining a wiring detection circuit according to the second embodiment of the present invention. The wire detection circuit 300 is used to early filter out defects that may be present in contacts or via holes in long wires connected by metal jumpers. Referring to FIG. 3, in the wiring detection circuit 300, the first to third wirings 310, 320, and 330 differ from the lower conductive layer 340 in comparison with the wiring detection circuit 200 of FIG. 2. The conductive layer 360 has a structure connected to each other through the contacts or via holes 350. The remaining components of the wiring detection circuit 300 are the same as those of FIG. 2 and have the same function. In order to avoid duplication of explanation, descriptions of the remaining components are omitted.

The lower conductive layer 340 may be, for example, a first metal layer, and the upper conductive layer 360 may be, for example, a second metal layer formed directly on the first metal layer. Alternatively, the lower conductive layer 340 may be the lowermost metal layer, and the upper conductive layer 360 may be the uppermost metal layer. In this case, the lowermost metal layer and the uppermost metal layer may be stacked with contacts or via holes for interconnection with a plurality of metal layers existing therebetween.

In the test mode 300, the first to third control signals C [0] to C [2] are sequentially supplied to the logic low in the test mode, and the stress signal STRESS is applied to the logic high. The first to third wires 310 to 330 may be formed from the power supply voltage VDD of the first driving units 212, 222, and 232 to the ground voltage VSS of the second driving units 218, 228, and 238. The current paths of are formed sequentially. In the first to third wirings 310-330, a strong current flows for a short time, thereby increasing the stress effect. As a result, the contacts or via holes 350 having the defects are broken by the strong current, and the first to third wirings 310 to 330 are opened to be treated as defects.

4 is a diagram for explaining a wiring detection circuit according to the third embodiment of the present invention. Referring to FIG. 4, the wiring detection circuit 400 may include wirings 410, 420, and 430 between the first driving units 412, 422, and 432 and the second driving units 418, 428, and 438. Connected with In the present exemplary embodiment, the first drivers 412, 422, and 432 are word line drivers, and the wirings 410, 420, and 430 are word lines.

Typically, the first driver 412 drives the first wiring 410 in response to the first control signal C [0], and the first PMOS transistor 414 and the first NMOS transistor 416. It consists of. The first PMOS transistor 414 has a boosted voltage VPP connected to its source, a first control signal C [0] connected to its gate, and a first wiring 410 connected to its drain. . In the first NMOS transistor 416, a first wire 410 is connected to a drain thereof, a first control signal C [0] is connected to a gate thereof, and a ground voltage VSS is connected to a source thereof. . The second driver 418 is formed of a PMOS transistor connected between the power supply voltage VDD and the first wiring 410 0 and a stress signal STRESS is applied to the gate thereof.

Each of the remaining first drivers 422 and 432 drives the second and third wires 420 and 430 in response to the second and third control signals C [1] and C [2]. do. The first to third control signals C [0], C [1], and C [2] correspond to word line driving signals.

In the test mode, the first to third control signals C [0] -C [2] are sequentially supplied with a logic high in the test mode, particularly in the package burn-in test mode, and are stressed. The signal STRESS is applied to logic low. The first to third wires 410-430 may be connected from the power supply voltage VDD of the second driving units 418, 428, and 438 to the ground voltage VSS of the first driving units 212, 222, and 232. Current paths are formed sequentially. In the first to third wirings 410-430, a strong current flows for a short time, thereby increasing the stress effect. Therefore, the wiring with the weak portion C, such as the second wiring 420, is opened by a strong current and is treated as defective. In addition, since the wire detection circuit 400 sequentially tests whether the first to third wires 210 to 230 are defective, it is easy to detect a bad wire. In addition, since the wiring detection circuit 400 does not form a current path connected to the boost voltage VPP in the package burn-in test mode, the level of the boost voltage VPP is stable.

In the wiring detection circuit 400, in the wafer burn-in test mode, the first to third control signals C [0] -C [2] are sequentially supplied to the logic low, and the stress signal STRESS is applied. Applied to logic low. The first to third wires 410 to 430 may be provided from the boosted voltage VDD of the first drivers 212, 222, and 232 to the power supply voltage VDD of the second drivers 418, 428, and 438. Current paths are formed sequentially. The wiring with the vulnerable portion C, such as the second wiring 420, is opened by the current and treated as defective. In addition, since the boost voltage VPP is externally applied through the pad in the wafer burn-in test mode, the wiring detection circuit 400 may boost the boost voltage VPP even when a current path connected to the boost voltage VPP is formed. The level of is stabilized.

5 is a diagram for explaining a wiring detection circuit according to the fourth embodiment of the present invention. Referring to FIG. 5, in the wiring detection circuit 500, the first to third wirings 510, 520, and 530 differ from the lower conductive layer 540 in comparison with the wiring detection circuit 400 of FIG. 4. The conductive layer 560 has a structure connected to each other through the contacts or via holes 550. The remaining components of the wiring detection circuit 500 are the same as those in FIG. 4 and have the same function. In order to avoid duplication of explanation, descriptions of the remaining components are omitted.

The lower conductive layer 540 may be, for example, a first metal layer, and the upper conductive layer 560 may be, for example, a second metal layer formed directly on the first metal layer. Alternatively, the lower conductive layer 540 may be the lowest metal layer, and the upper conductive layer 560 may be the highest metal layer. In this case, the lowermost metal layer and the uppermost metal layer may be stacked with contacts or via holes for interconnection with a plurality of metal layers existing therebetween.

In the test mode 500, the first to third control signals C [0] to C [2] are sequentially supplied to the logic high in the test mode, and the stress signal STRESS is applied to the logic low. The first to third wirings 510 to 530 are connected to the ground voltage VSS of the first driving units 412, 422, and 432 from the power supply voltage VDD of the second driving units 418, 428, and 438. The current paths of are formed sequentially. In the first to third wirings 510 to 530, a strong current flows for a short time, thereby increasing a stress effect. Accordingly, the contacts or via holes 550 having the defect are broken by the strong current, and the first to third wirings 510 to 530 are opened to be treated as failures.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

In the above-described wiring detection circuit of the present invention, in the wafer burn-in test mode or the package burn-in test mode, a strong current flows through the wirings for a short time to increase the stress effect. Further, since the wiring detection circuit screens whether the wirings are defective by sequentially generated control signals, it is easy to detect a weak wiring. In addition, the wire detection circuitry filters out early defects that may be present in contacts or via holes in long wires connected by metal jumpers.

Claims (33)

A first driver disposed at one end of one wire and driving the wire at a first voltage or a second voltage in response to a control signal; And A second driver disposed at the other end of the wiring and driving the wiring to a second voltage in response to a stress signal; The control signal and the stress signal are provided in a burn-in test mode. The method of claim 1, wherein the first drive unit A PMOS transistor having the control signal connected to a gate thereof, the first voltage connected to a source thereof, and one side of the wiring connected to a drain thereof; And And an NMOS transistor, wherein the control signal is connected to a gate thereof, the second voltage is connected to a source thereof, and one side of the wiring is connected to a drain thereof. The method of claim 1, wherein the second drive unit And an NMOS transistor, wherein the stress signal is connected to a gate thereof, the second voltage is connected to a source thereof, and the other side of the wiring is connected to a drain thereof. delete Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1, wherein the wiring And a first conductive layer and a second conductive layer connected to each other through a contact or via hole. The method of claim 1, wherein the wiring And a wiring detection circuit on the memory cell array pattern. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 6, wherein the wiring And select a bit line of said memory cell array. Claim 8 was abandoned when the registration fee was paid. The method of claim 1, And the first voltage is a power supply voltage, and the second voltage is a ground voltage. A first driver disposed at one end of one wire and driving the wire at a first voltage or a second voltage in response to a control signal; And And a second driver disposed at the other end of the wiring and configured to drive the wiring with a third voltage in response to a stress signal. The method of claim 9, wherein the first drive unit A PMOS transistor having the control signal connected to a gate thereof, the first voltage connected to a source thereof, and one side of the wiring connected to a drain thereof; And And an NMOS transistor, wherein the control signal is connected to a gate thereof, the second voltage is connected to a source thereof, and one side of the wiring is connected to a drain thereof. The method of claim 9, wherein the second drive unit And a PMOS transistor, wherein the stress signal is connected to a gate thereof, the third voltage is connected to a source thereof, and the other side of the wiring is connected to a drain thereof. The method of claim 9, wherein the control signal and the stress signal is And a wire detection circuit provided in the burn-in test mode. Claim 13 was abandoned upon payment of a registration fee. The method of claim 9, wherein the wiring Claim 14 was abandoned when the registration fee was paid. The method of claim 9, wherein the wiring And a wiring detection circuit on the memory cell array pattern. Claim 15 was abandoned upon payment of a registration fee. The method of claim 14, wherein the wiring And select a word line of said memory cell array. Claim 16 was abandoned upon payment of a setup registration fee. The method of claim 9, And the first voltage is a boosted voltage higher than a power supply voltage, the second voltage is a ground voltage, and the third voltage is the power supply voltage. A plurality of wirings; First drivers disposed at one end of each of the wires and sequentially driving corresponding wires in response to each of a plurality of control signals with a first voltage or a second voltage; And A second driver disposed at the other end of each of the wires and configured to drive the corresponding wires to the second voltage in response to a stress signal; The control signal and the stress signal are provided in a burn-in test mode. Claim 18 was abandoned upon payment of a set-up fee. The method of claim 17, wherein each of the control signals And activating sequentially to sequentially drive the corresponding wirings. Claim 19 was abandoned upon payment of a registration fee. The method of claim 17, wherein each of the first drive unit A PMOS transistor having a control signal corresponding to each of the wirings connected to a gate thereof, a first voltage connected to a source thereof, and one side of the corresponding wiring connected to a drain thereof; And And an NMOS transistor, wherein the corresponding control signal is connected to a gate thereof, the second voltage is connected to a source thereof, and one side of the corresponding wiring is connected to a drain thereof. Claim 20 was abandoned upon payment of a registration fee. The method of claim 17, wherein each of the second drive unit And an NMOS transistor, wherein the stress signal is connected to a gate thereof, the second voltage is connected to a source thereof, and the other side of the corresponding wiring is connected to a drain thereof. delete Claim 22 was abandoned upon payment of a registration fee. The method of claim 17, wherein each of the wirings And a first conductive layer and a second conductive layer connected to each other through a contact or via hole. Claim 23 was abandoned upon payment of a set-up fee. The method of claim 17, wherein the wirings And a wiring detection circuit on the memory cell array pattern. Claim 24 was abandoned when the setup registration fee was paid. The method of claim 17, wherein each of the wirings And select bit lines of the memory cell array. Claim 25 was abandoned upon payment of a registration fee. The method of claim 17, And the first voltage is a power supply voltage, and the second voltage is a ground voltage. A plurality of wirings; First drivers disposed at one end of each of the wires and sequentially driving corresponding wires in response to each of a plurality of control signals with a first voltage or a second voltage; And And second drivers disposed at the other end of each of the wires and configured to drive the corresponding wires to a third voltage in response to a stress signal. Claim 27 was abandoned upon payment of a registration fee. The method of claim 26, wherein each of the first drive unit A PMOS transistor having a control signal corresponding to each of the wirings connected to a gate thereof, a first voltage connected to a source thereof, and one side of the corresponding wiring connected to a drain thereof; And And an NMOS transistor, wherein the corresponding control signal is connected to a gate thereof, the second voltage is connected to a source thereof, and one side of the corresponding wiring is connected to a drain thereof. Claim 28 was abandoned upon payment of a registration fee. The method of claim 26, wherein each of the second drive unit And a PMOS transistor, wherein the stress signal is connected to a gate thereof, the third voltage is connected to a source thereof, and the other side of the corresponding wiring is connected to a drain thereof. Claim 29 was abandoned upon payment of a set-up fee. 27. The method of claim 26, wherein the control signals and the stress signal are And a wire detection circuit provided in the burn-in test mode. Claim 30 was abandoned upon payment of a registration fee. The method of claim 26, wherein each of the wirings And a first conductive layer and a second conductive layer connected to each other through a contact or via hole. Claim 31 was abandoned upon payment of a registration fee. 27. The device of claim 26, wherein the wires are And a wiring detection circuit on the memory cell array pattern. Claim 32 was abandoned upon payment of a registration fee. The method of claim 31, wherein each of the wirings And select word lines of said memory cell array. Claim 33 was abandoned upon payment of a registration fee. The method of claim 26, And the first voltage is a boosted voltage higher than a power supply voltage, the second voltage is a ground voltage, and the third voltage is the power supply voltage.

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