JP6708962B2 - Semiconductor memory device and control method thereof - Google Patents

Description

The present invention relates to a semiconductor memory device and its control method.

There is known a non-volatile memory that reads out data stored in a plurality of non-volatile memory cells such as NAND cells via a current flowing through a bit line. In such a non-volatile memory, the back gate voltage applied to the well in which the memory cell is formed can be controlled to a predetermined value to suppress the leak current flowing through the bit line when reading data from the memory cell. It is known (for example, refer to Patent Documents 1 to 3).

Japanese Patent Publication No. 2010-514196 International Publication No. 2006/059375 JP, 2013-84318, A

However, since the leak current flowing in the bit line depends on the manufacturing conditions of the semiconductor memory device, etc., when controlling the back gate voltage to a predetermined value, a leak current of a desired magnitude or more flows in the bit line, and the macro cell May not be able to read data from.

An object of one embodiment is to provide a semiconductor memory device capable of suppressing the magnitude of a leak current flowing through a bit line to a predetermined value or less.

According to one aspect, a semiconductor memory device includes a plurality of memory cells arranged in an array, a first selection circuit that selects any one of the plurality of memory cells arranged in a row direction, and a bit line. A second selection circuit for selecting any one of the above. The semiconductor memory device further includes a leak current determination circuit, a back gate voltage storage circuit, and a back gate voltage supply circuit. The leak current determination circuit determines whether or not the magnitude of the leak current flowing through the bit line in which all the connected memory cells are in the non-selected state is equal to or smaller than the reference current value. The back gate voltage storage circuit stores one or more back gate voltage information indicating the back gate voltage, and the back gate voltage supply circuit can apply the back gate voltage to the back gates of the plurality of memory cells.

In one embodiment, the magnitude of the leak current flowing through the bit line can be suppressed to a predetermined value or less.

3 is a circuit block diagram of the semiconductor memory device according to the first embodiment. FIG. 3 is an internal circuit block diagram of the memory core shown in FIG. 1. FIG. (A) is a more detailed internal circuit block diagram of the first sector shown in FIG. 1, (b) is an internal circuit block diagram of the memory cell shown in (a), and (c) is shown in (a). It is an internal circuit block diagram of a column switch. FIG. 3 is an internal circuit diagram of the leak current determination circuit shown in FIG. 1. 5 is a timing chart showing the operation of the leak current determination circuit shown in FIG. 4. 2 is an internal circuit diagram of the back gate voltage supply circuit shown in FIG. 1. FIG. FIG. 3 is a block diagram of a back gate voltage setting device that sets a back back gate voltage of the semiconductor memory device shown in FIG. 1. 9 is a flowchart of a back gate voltage setting process by the back gate voltage setting device shown in FIG. 7. FIG. 9 is a diagram for explaining an example of the back gate voltage determination process shown in FIG. 8. FIG. 6 is a circuit block diagram of a semiconductor memory device according to a second embodiment. FIG. 11 is a block diagram of an internal circuit of the memory core shown in FIG. 10. FIG. 11 is a block diagram of a back gate voltage setting device that sets a back back gate voltage of the semiconductor memory device shown in FIG. 10. 13 is a flowchart of a back gate voltage setting process by the back gate voltage setting device shown in FIG. 12. FIG. 9 is a circuit block diagram of a semiconductor memory device according to a third embodiment. FIG. 15 is an internal circuit block diagram of the memory core shown in FIG. 14. FIG. 16 is a more detailed internal circuit block diagram of the first sector shown in FIG. 15. FIG. 15 is a block diagram of a back gate voltage setting device that sets a back back gate voltage of the semiconductor memory device shown in FIG. 14. 18 is a flowchart of a back gate voltage setting process by the back gate voltage setting device shown in FIG. It is a circuit block diagram of a semiconductor memory device concerning a 4th embodiment. FIG. 20 is an internal circuit block diagram of the memory core shown in FIG. 19. FIG. 21 is an internal circuit block diagram of the column switch shown in FIG. 20. FIG. 20 is a block diagram of a back gate voltage setting device that sets a back back gate voltage of the semiconductor memory device shown in FIG. 19. 23 is a flowchart of a back gate voltage setting process by the back gate voltage setting device shown in FIG. 22. It is a figure which shows the 1st modification of the macrocell which the semiconductor memory device which concerns on embodiment has. It is a figure which shows the 2nd modification of the macrocell which the semiconductor memory device which concerns on embodiment has. FIG. 26 is a more detailed internal circuit block diagram of the first sector shown in FIG. 25.

A semiconductor memory device and a control method thereof will be described below with reference to the drawings. However, it should be noted that the technical scope of the present invention is not limited to those embodiments and covers equivalents to the invention described in the claims. The semiconductor memory device according to the embodiment provides a leak current determination circuit that determines the magnitude of a leakage current flowing in a bit line connected to a memory cell that is not selected by a selection signal, and back gate voltage information that indicates a back gate voltage. And a back gate voltage storage circuit for storing. This semiconductor memory device stores back gate voltage information in which a leak current is equal to or less than a predetermined value, and a back gate voltage corresponding to the stored back gate voltage information is applied to a back gate of a memory cell to flow to a bit line. The leak current can be suppressed to a predetermined value or less.

(Semiconductor Memory Device According to First Embodiment)
FIG. 1 is a circuit block diagram of the semiconductor memory device according to the first embodiment.

The semiconductor memory device 1 includes a command generation circuit 10, an internal voltage generation circuit 11, a memory core control circuit 12, an address generation circuit 13, a data input/output circuit 14, and a memory core 15.

The command generation circuit 10 generates various control signals and mode signals in response to the input of various command signals such as the chip enable signal CEX and the write enable signal WEX, and the internal voltage generation circuit 11 and the memory core control circuit. 12 and the address generation circuit 13. The internal voltage generation circuit 11 generates an internal power supply voltage according to the control signal and the mode signal input from the command generation circuit 10, and supplies the generated internal power supply voltage to the memory core 15. The memory core control circuit 12 outputs various memory core control signals MCnt to the memory core 15 according to the control signal and the mode signal input from the command generation circuit 10. The address generation circuit 13 outputs the row address signal RA and the column address signal CA to the memory core according to the control signal and the mode signal input from the command generation circuit 10 and the address signal input from the outside. The data input/output circuit 14 outputs an input data signal input from the outside to the memory core 15, and outputs an output data signal input from the memory core 15 to the outside.

FIG. 2 is a block diagram of the internal circuit of the memory core 15.

The memory core 15 includes a first sector 21, a second sector 22, a GBL selector 23, an amplifier circuit 24, a leak current determination circuit 25, a back gate voltage storage circuit 26, and a back gate voltage supply circuit 27. Have. The first sector 21 and the second sector 22 are blocks having the same constituent elements as each other and capable of independently erasing data, and are formed in N wells separated from each other. The memory core 15 has two sectors, the first sector 21 and the second sector 22, but in the semiconductor memory device according to the embodiment, the memory core may have one sector or three or more sectors.

Each of the first sector 21 and the second sector 22 has a row decoder 31, a column switch 32, and a memory cell array 33 in which unillustrated memory cells formed in the N well are arranged in an array. The row decoder 31 selects one memory cell (not shown) arranged in the memory cell array 33 for each row by the row selection signals SG0 to SG2 according to the row address signal RA. The column switch 32 selects any one of the bit lines BL0 to BL3 connected to a memory cell (not shown) arranged in the memory cell array 33 according to the column address signal CA.

The GBL selector 23 is connected to the first sector 21 and the second sector 22 via a plurality of global bit lines GBL. The GBL selector 23 inputs/outputs data from/to the main bit line MBL having a smaller number of wirings than the global bit wiring GBL according to the memory core control signal MCnt and the column address signal CA.

The amplifier circuit 24 includes a read amplifier and a write amplifier (not shown), and amplifies the data written in the memory cell (not shown) and the data read from the memory cell (not shown).

The leak current determination circuit 25 is connected to the main bit line MBL, and receives the reference current Ib and the current application instruction signal BC. Leakage current determination circuit 25 outputs an output signal OUT indicating the result of comparison between the magnitude of reference current Ib and the magnitude of leak current flowing in each of bit lines BL0 to BL3 input via main bit line MBL.

The back gate voltage storage circuit 26 includes a register. The back gate voltage storage circuit 26 stores back gate voltage information indicating a back gate voltage applied to an N well in which a memory cell (not shown) arranged in the memory cell array 33 is formed, according to the input of the setting signal SET. To do. Before the back gate voltage information is determined, the back gate voltage storage circuit 26 outputs back gate voltage information corresponding to the back gate voltage information signal input from the outside to the back gate voltage supply circuit 27. After the back gate voltage information is determined, the back gate voltage information is stored in a partial area of this semiconductor memory device or a predetermined nonvolatile memory area such as an external nonvolatile memory device. The back gate voltage information stored in the predetermined nonvolatile memory area is transferred to the back gate voltage memory circuit 26 when the semiconductor memory device is activated, and the back gate voltage memory circuit 26 outputs the back gate voltage information to the back gate voltage supply circuit 27. To do.

The back gate voltage supply circuit 27 applies a back gate voltage corresponding to the back gate voltage information input from the back gate voltage storage circuit 26 to an N well in which memory cells (not shown) arranged in the memory cell array 33 are formed. ..

3A is a more detailed internal circuit block diagram of the first sector 21, FIG. 3B is an internal circuit block diagram of the memory cell shown in FIG. 3A, and FIG. FIG. 4 is an internal circuit block diagram of the column switch shown in FIG.

The row decoder 31 outputs the row selection signals SG0 to SG2 and the cell control signal CG0 to the memory cells MC arranged in the memory cell array 33 according to the row address signal RA and the memory core control signal MCnt.

The column switch 32 selects any one of the bit lines BL0 to BL3 in accordance with the column address signal CA and the memory core control signal MCnt, and connects it to the global bit line GBL.

In the memory cell array 33, 12 macro cells MC arranged in 3 rows and 4 columns are arranged in an array. Although the memory cells MC are arranged in 3 rows and 4 columns in the memory cell array 33, in the semiconductor memory device according to the embodiment, the memory cells MC may be arranged in 4 rows or more, or may be arranged in 5 rows or more. Good.

The memory cell MC has a selection transistor M1 formed in each N well and a non-volatile memory transistor M2 connected in series to the selection transistor M1. The back gate voltage VNW is applied to the selection transistor M1 and the N well in which the selection transistor M1 is formed. The selection transistor M1 is a p-type MOS transistor in which the row selection signal SG is input to the gate, the source is connected to the drain of the nonvolatile memory transistor M2, and the drain is connected to the bit line BL. Here, the row selection signal SG indicates any one of the row selection signals SG0 to SG2, and the bit line BL indicates any one of the bit lines BL0 to BL3. The selection transistor M1 is turned on when the signal value corresponding to the row selection signal SG is “0”, and a current according to the data stored in the nonvolatile memory transistor M2 is passed through the bit line BL. The selection transistor M1 turns off when the signal value corresponding to the row selection signal SG is "1".

The cell control signal CG0 is input to the gate and the source voltage SRC is applied to the source of the nonvolatile memory transistor M2. The nonvolatile memory transistor M2 outputs a relatively small current when the signal value "1" is stored and when the selection transistor M1 is turned on, and the selection transistor M1 is turned on when the signal value "0" is stored. When it does, it outputs a relatively large current.

FIG. 4 is an internal circuit diagram of the leak current determination circuit 25.

The leak current determination circuit 25 includes a first leak transistor 41 to an eighth leak transistor 48. The first leak transistor 41 has a gate to which the current application instruction signal BC is input, a source connected to the drain of the second leak transistor 42, and a drain connected to the main bit line MBL. The first leak transistor 41 is turned on when the current application instruction signal BC is input, and flows the leak current Ilk flowing through the bit line to which the selection transistor M1 turned off by the row selection signal SG is connected. The second leak transistor 42 and the third leak transistor 43 form a current mirror circuit, and a leak current Ilk that flows when the first leak transistor 41 is turned on flows between the source and the drain of the third leak transistor 43.

The fourth leak transistor 44 and the fifth leak transistor 45 form a current mirror circuit. The sixth leak transistor 46 has a gate to which the current application instruction signal BC is input, a source connected to the drain of the fifth leak transistor 45, and a drain connected to the seventh leak transistor 47. The sixth leak transistor 46 causes the reference current Ib input to the drain of the fourth leak transistor 44 to flow between the source and drain of the third leak transistor 43 when the current application instruction signal BC is input to the gate. .. The seventh leak transistor 47 and the eighth leak transistor 48 form a current mirror circuit.

The leak current determination circuit 25 determines the magnitude of the leak current Ilk and the magnitude of the reference current Ib when the current application instruction signal BC having the signal value “1” is input to the gates of the first leak transistor 41 and the sixth leak transistor 46. To compare. The leak current determination circuit 25 outputs an output signal OUT indicating a comparison result of comparing the magnitude of the leak current Ilk and the magnitude of the reference current Ib. The signal value of the output signal OUT becomes “0” when the magnitude of the leak current Ilk is larger than the magnitude of the reference current Ib, and the signal of the output signal OUT when the magnitude of the leak current Ilk is smaller than the magnitude of the reference current Ib. The value becomes "1". Further, when the magnitude of the leak current Ilk is equal to the magnitude of the reference current Ib, the signal value of the output signal OUT becomes the intermediate potential.

FIG. 5 is a timing chart showing the operation of the leak current determination circuit 25. In FIG. 5, the signal value corresponding to the row selection signal SG input to the selection transistor M1 of the memory cell MC connected to the selected bit line BL is “1”, which is input to the nonvolatile memory transistor M2. The cell control signal CG has the same voltage as the source voltage SRC. The signal value stored in the memory transistor M2 is preferably “0” in order to make the leak large.

At the time point indicated by the arrow A, the signal value of the output signal OUT transits in response to the signal value corresponding to the current application instruction signal BC transiting from “0” to “1”. When the magnitude of the leak current Ilk is larger than the magnitude of the reference current Ib, the signal value of the output signal OUT maintains “0” although it slightly changes. On the other hand, when the magnitude of the leak current Ilk is smaller than the magnitude of the reference current Ib, the signal value of the output signal OUT transits from “0” to “1”.

FIG. 6 is an internal circuit diagram of the back gate voltage supply circuit 27.

The back gate voltage supply circuit 27 is a constant voltage generation circuit having a voltage generation operational amplifier 51, a voltage generation transistor 52, a voltage generation resistor 53, and a voltage generation selection circuit 54.

In the voltage generation operational amplifier 51, the voltage generation reference voltage VREF is input to one input terminal, the output terminal of the voltage generation selection circuit 54 is connected to the other input terminal, and the gate of the voltage generation transistor 52 is connected to the output terminal. .. The voltage generation transistor 52 is a p-type MOS transistor, the voltage generation power supply VEXT is applied to the source, and one end of the voltage generation resistor 53 and the output terminal are connected to the drain. The power supply voltage VEXT for voltage generation is a voltage capable of supplying a desired back gate charge VNW to the N well of the memory cell array 33. The other end of the voltage generating resistor 53 is grounded. The voltage generating resistor 53 is a resistance element having a resistance value of Rtotal. The voltage generation selection circuit 54 receives the back gate voltage signal indicating the back gate voltage information stored in the back gate voltage storage circuit 26, and the partial resistance value of the resistance value Rtotal of the voltage generation resistor 53 according to the back gate voltage information. Get Rs.

The back gate voltage VNW is calculated based on the voltage generation reference voltage VREF, the resistance value Rtotal of the voltage generation resistor 53, and the partial resistance value Rs acquired by the voltage generation selection circuit 54.
VNW = VREF x Rtotal/Rs
Indicated by.

(Backgate voltage setting device for setting the backback gate voltage of the semiconductor memory device according to the first embodiment)
FIG. 7 is a block diagram of a back gate voltage setting device that sets the back back gate voltage of the semiconductor memory device 1. The back gate voltage setting device shown in FIG. 7 is, for example, a tester that tests the operation of the semiconductor memory device 1 when the semiconductor memory device 1 is shipped.

The back gate voltage setting device 101 includes an input unit 111, an output unit 112, a storage unit 113, a signal input/output unit 114, and a processing unit 120.

The input unit 111 may be any device capable of inputting data, such as a touch panel or a keyboard. The operator can input characters, numbers, symbols, etc. using the input unit 111. When the operator operates the input unit 111, the input unit 111 generates a signal corresponding to the operation. Then, the generated signal is supplied to the processing unit 120 as an instruction of the worker.

The output unit 112 may be any device as long as it can display images and images, and is, for example, a liquid crystal display or an organic EL (Electro-Luminescence) display. The output unit 112 displays an image according to the image data supplied from the processing unit 120, an image according to the image data, and the like. The output unit 112 may also be an output device that prints images, images, characters, or the like on a display medium such as paper.

The storage unit 113 includes, for example, at least one of a semiconductor storage device, a magnetic tape device, a magnetic disk device, or an optical disk device. The storage unit 113 stores an operating system program, a driver program, an application program, data and the like used in the processing of the processing unit 120. The application program may be installed in the storage unit 113 from a computer-readable portable recording medium such as a CD-ROM or a DVD-ROM using a known setup program or the like.

The storage unit 113 also stores various data used in the process of the back gate voltage setting device 101. Further, the storage unit 113 may temporarily store temporary data related to a predetermined process.

The signal input/output unit 114 inputs the input signals such as the chip enable signal CEX and the address signal to the semiconductor memory device 1, and also receives the output signals such as the output signal OUT output from the semiconductor memory device 1.

The processing unit 120 has one or more processors and their peripheral circuits. The processing unit 120 centrally controls the overall operation of the back gate voltage setting device 101, and is, for example, a CPU. The processing unit 120 executes processing based on programs (driver program, operating system program, application program, etc.) stored in the storage unit 113. Moreover, the processing unit 120 can execute a plurality of programs (application programs and the like) in parallel.

The processing unit 120 has an address setting unit 121, a back gate voltage determination unit 122, an end determination unit 123, a back gate voltage determination unit 124, and a back gate voltage setting unit 125. Each of these units is a functional module implemented by a program executed by a processor included in the processing unit 120. Alternatively, each of these units may be implemented in the back gate voltage setting device 101 as firmware.

FIG. 8 is a flowchart of the back gate voltage setting process by the back gate voltage setting device 101. The back gate voltage setting process shown in FIG. 8 is executed mainly by the processing unit 120 in cooperation with each element of the back gate voltage setting device 101 based on a program stored in the storage unit 113 in advance.

First, the address setting unit 121 sets a memory core control signal MCnt including a row address signal RA, a column address signal CA and a test signal (not shown) so as to detect the leak current Ilk of the bit line BL0 of the first sector 21. Yes (S101). Specifically, the address setting unit 121 sets the row address signal RA and the memory core control signal MCnt so as not to select all the memory cells MC connected to the bit line BL0 of the first sector 21. Further, the address setting unit 121 sets the column address signal CA so as to connect the bit line BL0 of the first sector 21 to the main bit line MBL.

Next, the back gate voltage determination unit 122 determines the back gate voltage at which the magnitude of the leak current Ilk of the bit line BL0 of the first sector 21 becomes smaller than the magnitude of the reference current Ib (S102). Specifically, the back gate voltage determination unit 122 outputs the output signal while changing the back gate voltage information signal in a state where the signal value corresponding to the current application instruction signal BC is set to “1” and the reference current Ib is input. Whether or not OUT has changed is determined.

FIG. 9 is a diagram for explaining an example of the back gate voltage determination processing.

The back gate voltage determination unit 122 changes the back gate voltage information signal so as to gradually increase the back gate voltage, and the back gate voltage at which the signal value corresponding to the output signal OUT changes from “0” to “1”. To search. When the back gate voltage rises to the voltage indicated by the arrow A, the magnitude of the leak current Ilk becomes smaller than the magnitude of the reference current Ib, and the output signal OUT of the leak current determination circuit 25 transits from “0” to “1”. .. The back gate voltage determination unit 122 determines the back gate voltage immediately after the signal value corresponding to the output signal OUT transits from “0” to “1” as the leakage current Ilk of the bit line BL0 of the first sector 21. The back gate voltage is determined to be smaller than the magnitude of the reference current Ib. The back gate voltage determination unit 122 stores back gate voltage information corresponding to the determined back gate voltage in the storage unit 113.

Next, the end determination unit 123 determines whether or not the process of determining the back gate voltage has been executed for all bit lines BL up to the bit line BL3 of the second sector 22 (S103). The address setting unit 121, the back gate voltage determination unit 122, and the end determination unit 123 repeat the processes of S101 to S103 until it is determined that the back gate voltage determination process has been executed for all the bit lines BL (S103-YES). ..

When the back gate voltage determining unit 124 determines that the back gate voltage determining process has been executed for all the bit lines BL (S103-YES), the back gate voltage determining unit 124 determines the back gate voltage applied to the N well during the operation of the memory cell MC. Yes (S104). Specifically, the back gate voltage determination unit 124 applies the maximum value of the back gate voltage determined in each of the bit line BL0 of the first sector 21 to the bit line BL3 of the second sector 22 during the operation of the memory cell MC. Determine the back gate voltage to be used.

Then, the back gate voltage setting unit 125 outputs the back gate voltage information signal BGV indicating the back gate voltage determined in the process of S104 and the setting signal SET to the back gate voltage storage circuit 26 to set the back gate voltage. .. .. In addition, the back gate voltage setting unit 155 stores the determined back gate voltage information in a predetermined nonvolatile storage area (S105).

(Semiconductor Memory Device According to Second Embodiment)
FIG. 10 is a circuit block diagram of the semiconductor memory device according to the second embodiment.

The semiconductor memory device 2 differs from the semiconductor memory device 1 in that the memory core 16 is arranged instead of the memory core 15. The configurations and functions of the components of the semiconductor memory device 2 other than the memory core 16 are the same as the configurations and functions of the components of the semiconductor memory device 1 designated by the same reference numerals, and thus detailed description thereof is omitted here.

FIG. 11 is a block diagram of the internal circuit of the memory core 16.

In the memory core 16, the low temperature back gate voltage storage circuit 61, the high temperature back gate voltage storage circuit 62, the temperature sensor 63 and the back gate voltage selection circuit 64 are arranged instead of the back gate voltage storage circuit 26. Be different. The configurations and functions of the components of the memory core 16 other than the low-temperature back gate voltage storage circuit 61, the temperature sensor 63, and the back gate voltage selection circuit 64 are the same as the configurations and functions of the components of the memory core 15 designated by the same reference numerals. Therefore, detailed description is omitted here.

The low temperature back gate voltage storage circuit 61 includes a register. The low temperature back gate voltage storage circuit 61 stores low temperature back gate voltage information indicating the low temperature back gate voltage applied to the N well in which the memory cell MC is formed, according to the input of the setting signal SET. Before the low temperature back gate voltage information is determined, the low temperature back gate voltage storage circuit 61 outputs the low temperature back gate voltage information corresponding to the low temperature back gate voltage information signal input from the outside to the back gate voltage selection circuit 64. .. After the back gate voltage information is determined, the low temperature back gate voltage information is stored in a part of the semiconductor memory device or a predetermined nonvolatile memory area such as an external nonvolatile memory device. The low temperature back gate voltage information stored in a predetermined nonvolatile storage area is transferred to the low temperature back gate voltage storage circuit 61 when the semiconductor storage device is activated, and the low temperature back gate voltage storage circuit 61 selects the low temperature back gate voltage information as the back gate voltage. Output to the circuit 64.

The high temperature back gate voltage storage circuit 62 includes a register. The high temperature back gate voltage storage circuit 62 stores high temperature back gate voltage information indicating the high temperature back gate voltage applied to the N well in which the memory cell MC is formed, in response to the input of the setting signal SET. The high temperature back gate voltage is a voltage higher than the high temperature back gate voltage. Before the setting signal SET is input, the high temperature back gate voltage storage circuit 62 outputs high temperature back gate voltage information corresponding to the high temperature back gate voltage information signal input from the outside to the back gate voltage selection circuit 64. Further, after the back gate voltage information is determined, the high temperature back gate voltage information is stored in a part of the semiconductor memory device or a predetermined nonvolatile memory area such as an external nonvolatile memory device. The high temperature back gate voltage information stored in a predetermined nonvolatile storage area is transferred to the high temperature back gate voltage storage circuit 62 when the semiconductor storage device is activated, and the high temperature back gate voltage storage circuit 62 selects the high temperature back gate voltage information as the back gate voltage. Output to the circuit 64.

The temperature sensor 63 has a PN junction part whose voltage across both ends changes in accordance with a change in temperature, and a comparator which compares the voltage across the PN junction part with a temperature reference voltage. The temperature sensor 63 outputs a temperature selection signal indicating a signal value “0” when the temperature of the PN junction is lower than a predetermined threshold temperature, and when the temperature of the PN junction is equal to or higher than the predetermined threshold temperature. The temperature selection signal indicating the signal value "1" is output to.

The back gate voltage selection circuit 64 outputs the low temperature back gate voltage information signal input from the low temperature back gate voltage storage circuit 61 to the back gate voltage supply circuit 27 when the temperature selection signal indicating the signal value “0” is input. To do. Further, the back gate voltage selection circuit 64 receives the high temperature back gate voltage information signal input from the high temperature back gate voltage storage circuit 62 when the temperature selection signal indicating the signal value “1” is input. Output to.

(Backgate voltage setting device for setting the backback gate voltage of the semiconductor memory device according to the second embodiment)
FIG. 12 is a block diagram of a back gate voltage setting device for setting the back back gate voltage of the semiconductor memory device 2. The back gate voltage setting device shown in FIG. 12 is, for example, a tester that tests the operation of the semiconductor memory device 2 when the semiconductor memory device 2 is shipped.

The back gate voltage setting device 102 is different from the back gate voltage setting device 101 in that the processing unit 130 is arranged instead of the processing unit 120. The configurations and functions of the components of the back gate voltage setting device 102 other than the processing unit 130 are the same as the components and functions of the back gate voltage setting device 101 denoted by the same reference numerals, and thus detailed description thereof is omitted here. To do.

The processing unit 130 has one or more processors and their peripheral circuits. The processing unit 130 integrally controls the overall operation of the back gate voltage setting device 102, and is, for example, a CPU. The processing unit 130 executes processing based on a program (driver program, operating system program, application program, etc.) stored in the storage unit 113. Moreover, the processing unit 130 can execute a plurality of programs (application programs and the like) in parallel.

The processing unit 130 includes an address setting unit 131, a back gate voltage determination unit 132, an end determination unit 133, a back gate voltage determination unit 134, and a back gate voltage setting unit 135. Each of these units is a functional module implemented by a program executed by a processor included in the processing unit 130. Alternatively, each of these units may be implemented in the back gate voltage setting device 102 as firmware.

FIG. 13 is a flowchart of a back gate voltage setting process by the back gate voltage setting device 102. The back gate voltage setting process shown in FIG. 13 is executed mainly by the processing unit 130 in cooperation with each element of the back gate voltage setting device 102 based on a program stored in the storage unit 113 in advance.

First, the address setting unit 131 sets the temperature of the semiconductor memory device 2 to the first temperature (S201). Since the processing of S202 to S205 is the same as the processing of S101 to S104, detailed description will be omitted here. After the processing of S205, the back gate voltage setting unit 135 outputs the back gate voltage information signal BGV indicating the low temperature back gate voltage determined in the processing of S205 and the setting signal SET to the low temperature back gate voltage storage circuit 61, Set the low temperature back gate voltage. Further, the back gate voltage setting unit 135 stores the determined low temperature back gate voltage information in a predetermined nonvolatile storage area (S206).

Next, the address setting unit 131 sets the temperature of the semiconductor memory device 2 to a temperature higher than the first temperature by 2 (S207). The processing of S207 to S211 is the same as the processing of S101 to S104, and thus detailed description thereof is omitted here. After the processing of S211, the back gate voltage setting unit 135 outputs the high temperature back gate voltage information signal BGV indicating the high temperature back gate voltage determined by the processing of S211 and the setting signal SET to the high temperature back gate voltage storage circuit 62. , Set the high temperature back gate voltage. The back gate voltage setting unit 135 also stores the determined high temperature back gate voltage information in a predetermined nonvolatile storage area (S212).

(Semiconductor Memory Device According to Third Embodiment)
FIG. 14 is a circuit block diagram of the semiconductor memory device according to the third embodiment.

The semiconductor memory device 3 differs from the semiconductor memory device 1 in that the memory core 17 is arranged instead of the memory core 15. The configurations and functions of the components of the semiconductor memory device 3 other than the memory core 17 are the same as the configurations and functions of the components of the semiconductor memory device 1 designated by the same reference numerals, and thus detailed description thereof is omitted here.

FIG. 15 is a block diagram of the internal circuit of the memory core 17.

The memory core 17 differs from the memory core 15 in that the first sector 71 and the second sector 72 are arranged instead of the first sector 21 and the second sector 22. The configurations and functions of the components of the memory core 17 other than the first sector 71 and the second sector 72 are the same as the configurations and functions of the components of the memory core 15 to which the same reference numerals are assigned, and thus detailed description thereof is omitted here. To do. The first sector 71 and the second sector 72 are blocks having the same constituent elements and capable of independently erasing data, and are formed in N wells separated from each other. The first sector 71 and the second sector 72 are different from the semiconductor memory device 1 in that a row decoder 73, a column switch 74, and a memory cell array 75 are arranged instead of the row decoder 31, the column switch 32, and the memory cell array 33.

FIG. 16 is a more detailed internal circuit block diagram of the first sector 71.

The row decoder 73 outputs the row selection signals SG0 to SG2 and the cell control signal CG0 to the memory cells MC arranged in the memory cell array 75 according to the row address signal RA and the memory core control signal MCnt. The column switch 74 selects any one of the bit lines BL0 to BL4 according to the column address signal CA and the memory core control signal MCnt and connects the selected bit line to the global bit line GBL.

In the memory cell array 75, 15 macro cells MC are arranged in an array so that three macro cells MC are arranged in the row direction and five macro cells MC are arranged in the column direction. The three macro cells MC connected to the bit line BL4 are spare macro cells. The macro cell MC connected to the bit line BL4 is connected to the bit line whose leak current is the upper limit current value when it is determined that the leak current of any of the bit lines BL0 to BL3 is equal to or higher than the upper limit current value. The address of the connected macro cell MC is assigned alternatively.

(Back Gate Voltage Setting Device for Setting Back Back Gate Voltage of Semiconductor Memory Device According to Third Embodiment)
FIG. 17 is a block diagram of a back gate voltage setting device for setting the back back gate voltage of the semiconductor memory device 3. The back gate voltage setting device shown in FIG. 17 is, for example, a tester that tests the operation of the semiconductor memory device 3 when the semiconductor memory device 3 is shipped.

The back gate voltage setting device 103 differs from the back gate voltage setting device 101 in that the processing unit 140 is arranged instead of the processing unit 120. The configurations and functions of the components of the back gate voltage setting device 103 other than the processing unit 140 are the same as the components and functions of the back gate voltage setting device 101 denoted by the same reference numerals, and thus detailed description thereof is omitted here. To do.

The processing unit 140 includes one or more processors and their peripheral circuits. The processing unit 140 centrally controls the overall operation of the back gate voltage setting device 103, and is, for example, a CPU. The processing unit 140 executes processing based on a program (driver program, operating system program, application program, etc.) stored in the storage unit 113. Further, the processing unit 140 can execute a plurality of programs (application programs and the like) in parallel.

The processing unit 140 includes an address setting unit 141, a leak current determination unit 142, a back gate voltage determination unit 143, an end determination unit 144, a back gate voltage determination unit 145, and a back gate voltage setting unit 146. Each of these units is a functional module implemented by a program executed by a processor included in the processing unit 140. Alternatively, each of these units may be implemented as firmware in the back gate voltage setting device 103.

FIG. 18 is a flowchart of the back gate voltage setting process by the back gate voltage setting device 103. The back gate voltage setting process shown in FIG. 18 is executed mainly by the processing unit 140 in cooperation with each element of the back gate voltage setting device 103 based on a program stored in the storage unit 113 in advance.

First, the address setting unit 141 sets the row address signal RA, the column address signal CA, and the memory core control signal MCnt so as to detect the leak current Ilk of the bit line BL0 of the first sector 21 (S301). Specifically, the address setting unit 141 sets the row address signal RA so as not to select all the memory cells MC connected to the bit line BL0 of the first sector 21. In addition, the address setting unit 141 sets the column address signal CA and the memory core control signal MCnt so that the bit line BL0 of the first sector 21 is connected to the main bit line MBL.

Next, the leak current determination unit 142 determines whether or not the magnitude of the leak current Ilk of the bit line BL0 of the first sector 71 is equal to or larger than a predetermined upper limit current value (S302). The leakage current determination unit 142 inputs the upper limit current into the leakage current determination circuit 25 instead of the reference current Ib, and determines whether the magnitude of the leakage current Ilk of the bit line BL0 of the first sector 71 is equal to or larger than the upper limit current value. To determine.

When the leak current determination unit 142 determines that the magnitude of the leak current Ilk of the bit line BL0 is equal to or larger than the upper limit current value, the address of the memory cell MC connected to the bit line BL0 is the memory cell connected to the bit line BL4. The address is switched to MC (S303). The leak current determination unit 142 switches the address of the memory cell MC connected to the bit line BL0 to exclude the bit line BL0 from the bit lines for which the back gate voltage determination process is performed.

The leakage current determination unit 142 repeats the processing of S301 to S304 until it determines that the comparison processing of the magnitude of the leakage current Ilk and the upper limit current value has been executed for all the bit lines BL (S304-YES). When it is determined that the comparison process has been executed for all the bit lines BL (S304-YES), the address setting unit 141 sets an address so that the leak current Ilk of the bit line BL0 of the first sector 21 is detected again. Yes (S305). Since the processes of S305 to S309 are similar to the processes of S101 to S105, detailed description thereof will be omitted here.

(Semiconductor Memory Device According to Fourth Embodiment)
FIG. 19 is a circuit block diagram of the semiconductor memory device according to the fourth embodiment.

The semiconductor memory device 4 differs from the semiconductor memory device 1 in that the memory core 18 is arranged instead of the memory core 15. The configurations and functions of the components of the semiconductor memory device 4 other than the memory core 18 are the same as the configurations and functions of the components of the semiconductor memory device 1 designated by the same reference numerals, and thus detailed description thereof will be omitted here.

FIG. 20 is a block diagram of the internal circuit of the memory core 18.

The memory core 18 differs from the memory core 15 in that a leak current determination circuit 80 is arranged instead of the leak current determination circuit 25. Further, the memory core 18 is different from the memory core 15 in that the column switch 81 is arranged instead of the column switch 32. The configurations and functions of the components of the memory core 18 other than the leak current determination circuit 80 and the column switch 81 are the same as the configurations and functions of the components of the memory core 15 to which the same reference numerals are assigned, and thus detailed description thereof is omitted here. To do.

The bit line selection signal BSL, the reference current Ib_2, and the current application instruction signal BC are input to the leak current determination circuit 80. The bit selection signal BSL selects either the bit lines BL0 and BL1 or the bit lines BL2 and BL3. The current value of the reference current Ib_2 is twice the current value of the reference current Ib or less than twice the current value of the reference current Ib. The leak current determination circuit 80 outputs an output signal OUT indicating the result of comparison between the leak current flowing through any two bit lines BL0 and BL1 or any two bit lines BL2 and BL3 and the reference current IbL_2.

FIG. 21 is a block diagram of the internal circuit of the column switch 81.

The column switch 81 selects one of the bit lines BL0 to BL3 according to the test signal tes4, the column address signal CA and the memory core control signal MCnt included in the memory core control signal MCnt, and connects the selected bit line to the global bit line GBL. To do. Specifically, the column switch 81 executes the back gate voltage setting process when the signal value corresponding to the test signal tes4 is “H”. When performing the back gate voltage setting process, the column switch 81 connects both the bit lines BL0 and BL1 to the global bit line GBL0 and connects both the bit lines BL2 and BL3 to the global bit line GBL0. When the signal value corresponding to the test signal tes4 is “L”, the column switch 81 connects each of the bit lines BL0 to BL3 to a predetermined global bit line GL in order to execute normal read processing and write processing. ..

(Back Gate Voltage Setting Device for Setting Back Back Gate Voltage of Semiconductor Memory Device According to Fourth Embodiment)
FIG. 22 is a block diagram of a back gate voltage setting device that sets the back back gate voltage of the semiconductor memory device 4. The back gate voltage setting device shown in FIG. 22 is, for example, a tester that tests the operation of the semiconductor memory device 4 when the semiconductor memory device 4 is shipped.

The back gate voltage setting device 104 differs from the back gate voltage setting device 101 in that the processing unit 150 is arranged instead of the processing unit 120. The configurations and functions of the components of the back gate voltage setting device 104 other than the processing unit 150 are the same as the components and functions of the back gate voltage setting device 101 denoted by the same reference numerals, and thus detailed description thereof is omitted here. To do.

The processing unit 150 has one or more processors and their peripheral circuits. The processing unit 150 centrally controls the overall operation of the back gate voltage setting device 104, and is, for example, a CPU. The processing unit 150 executes processing based on a program (driver program, operating system program, application program, etc.) stored in the storage unit 113. Further, the processing unit 150 can execute a plurality of programs (application programs and the like) in parallel.

The processing unit 150 includes an address setting unit 151, a back gate voltage determination unit 152, an end determination unit 153, a back gate voltage determination unit 154, and a back gate voltage setting unit 155. Each of these units is a functional module implemented by a program executed by a processor included in the processing unit 150. Alternatively, each of these units may be implemented in the back gate voltage setting device 104 as firmware.

FIG. 23 is a flowchart of the back gate voltage setting process by the back gate voltage setting device 104. The back gate voltage setting process shown in FIG. 23 is executed mainly by the processing unit 150 in cooperation with each element of the back gate voltage setting device 104 based on a program stored in the storage unit 113 in advance.

First, the address setting unit 151 sets the row address signal RA, the column address signal CA, and the memory core control signal MCnt so as to detect the leak currents Ilk of the bit lines BL0 and BL1 of the first sector 21 (S401). Specifically, the address setting unit 131 sets the row address signal RA and the memory core control signal MCnt so as not to select all the memory cells MC connected to the bit lines BL0 and BL1 of the first sector 21. Next, the address setting unit 151 outputs the bit selection signal BSL indicating that the bit lines BL0 and BL1 are selected, and selects the bit lines BL0 and BL1 in the leak current determination circuit 80 (S402).

Next, the back gate voltage determination unit 152 determines the back gate voltage at which the total magnitude of the leak currents Ilk of the bit lines BL0 and BL1 of the first sector 21 becomes smaller than the magnitude of the reference current Ib_2 (S403).

Next, the end determination unit 153 determines whether or not the process of determining the back gate voltage has been executed for all the bit lines BL up to the bit line BL3 of the second sector 22 (S405). The address setting unit 151, the back gate voltage determination unit 152, and the end determination unit 153 repeat the processes of S401 to S405 until it is determined that the back gate voltage determination process has been executed for all the bit lines BL (S405-YES). ..

When the back gate voltage determination unit 154 determines that the back gate voltage determination processing has been executed for all the bit lines BL (S405-YES), it determines the back gate voltage applied during the operation of the memory cell MC (S406). ). Specifically, the back gate voltage determination unit 154 sets the maximum value of the back gate voltage determined in each pair of the bit line BL0 of the first sector 21 to the bit line BL3 of the second sector 22 to the operation of the memory cell MC. The back gate voltage applied at times is determined.

Then, the back gate voltage setting unit 155 sets the back gate voltage (S407). The back gate voltage setting unit 155 outputs the back gate voltage information signal BGV indicating the back gate voltage determined in the process of S406 and the setting signal SET to the back gate voltage storage circuit 26 to set the back gate voltage. In addition, the back gate voltage setting unit 155 stores the determined back gate voltage information in a predetermined nonvolatile storage area.

(Function and Effect of Semiconductor Memory Device According to Embodiment)
The semiconductor memory devices 1 to 4 determine and store back gate voltage information in which the leak current is equal to or less than the reference current value. By applying a back gate voltage corresponding to the stored back gate voltage information to the back gate of the memory cell, the semiconductor memory devices 1 to 4 can suppress the leak current flowing in the bit line to a predetermined value or less.

Further, the semiconductor memory device 2 switches the back gate voltage applied to the memory cell in accordance with the temperature change of the semiconductor memory device 2 detected by the temperature sensor, so that the back gate voltage suitable for the temperature of the semiconductor memory device 2 is changed. Can be selected. Since the leak current of the bit line BL rises as the temperature rises, the back gate voltage is set high at a high temperature in order to suppress the leak current below a predetermined value. On the other hand, since the on-current of the selection transistor M1 decreases as the back gate voltage increases, the back gate voltage is set low at low temperatures.

Further, the semiconductor memory device 3 substitutes the address of the macro cell connected to the bit line for which the leak current is determined to be equal to or higher than the upper limit current value, to the macro cell connected to the spare bit line. The semiconductor memory device 3 excludes the bit line for which the leak current is determined to be equal to or higher than the upper limit current value, so that when the back gate voltage at which the leak current becomes equal to or lower than the reference current value is determined, A bit line having a large leak current can be excluded from the determination target. The semiconductor memory device 3 can reduce the processing time of the back gate voltage determination processing by removing the bit line having a large leak current from the determination target.

Further, the semiconductor memory device 4 can collectively detect leak currents flowing through a plurality of bit lines and determine the back gate voltage, thereby shortening the processing time of the back gate voltage determination processing.

(Modification of the semiconductor memory device according to the embodiment)
In the semiconductor memory devices 1 to 4, the macro cell MC is a flash memory having the non-volatile memory transistor M1. However, the semiconductor memory device according to the embodiment may be another memory cell such as a single-ended SRAM and DRAM. ..

Further, in the semiconductor memory devices 1 to 4, a single back gate voltage is applied to the macro cells MC arranged in a plurality of sectors. However, in the semiconductor memory device according to the embodiment, a different back gate voltage may be applied to each macro cell MC arranged in each of the plurality of sectors.

FIG. 24 is a diagram showing a first modification of the macro cell included in the semiconductor memory device according to the embodiment.

The memory core 19 differs from the memory core 15 in that the back gate voltage storage circuits 126 and 226 and the back gate voltage supply circuits 127 and 227 are arranged instead of the back gate voltage storage circuit 26 and the back gate voltage supply circuit 227. .. The configurations and functions of the components of the memory core 19 other than the back gate voltage storage circuits 126 and 226 and the back gate voltage supply circuits 127 and 227 are the same as the configurations and functions of the components of the memory core 15 designated by the same reference numerals. The detailed description is omitted here.

The back gate voltage storage circuit 126 includes a register. The back gate voltage storage circuit 126 inputs the back gate voltage information indicating the back gate voltage applied to the N well in which the memory cells MC arranged in the memory cell array 33 of the first sector 21 are input, to the setting signal SET. Memorize accordingly. Before the back gate voltage information is determined, the back gate voltage storage circuit 126 outputs back gate voltage information corresponding to the back gate voltage information signal input from the outside to the back gate voltage supply circuit 127. After the back gate voltage information is determined, the back gate voltage information is stored in a partial area of this semiconductor memory device or a predetermined nonvolatile memory area such as an external nonvolatile memory device. The back gate voltage information stored in the predetermined nonvolatile memory area is transferred to the back gate voltage memory circuit 126 when the semiconductor memory device is activated, and the back gate voltage memory circuit 126 outputs the back gate voltage information to the back gate voltage supply circuit 127. To do.

The back gate voltage supply circuit 127 has memory cells (not shown) in which the back gate voltage corresponding to the back gate voltage information input from the back gate voltage storage circuit 126 is arranged in the memory cell array 33 of the first sector 21. Apply to N-well.

The back gate voltage supply circuit 127 has memory cells (not shown) in which the back gate voltage corresponding to the back gate voltage information input from the back gate voltage storage circuit 126 is arranged in the memory cell array 33 of the first sector 21. Apply to N-well.

The back gate voltage storage circuit 226 includes a register. The back gate voltage storage circuit 226 provides back gate voltage information indicating the back gate voltage applied to the N well in which the memory cells MC arranged in the memory cell array of the second sector 22 are formed, in response to the input of the setting signal SET. To remember. Before the back gate voltage information is determined, the back gate voltage storage circuit 226 outputs back gate voltage information corresponding to the back gate voltage information signal input from the outside to the back gate voltage supply circuit 227. After the back gate voltage information is determined, the back gate voltage information is stored in a partial area of this semiconductor memory device or a predetermined nonvolatile memory area such as an external nonvolatile memory device. The back gate voltage information stored in the predetermined nonvolatile memory area is transferred to the back gate voltage memory circuit 226 when the semiconductor memory device is activated, and the back gate voltage memory circuit 226 outputs the back gate voltage information to the back gate voltage supply circuit 227. To do.

The back gate voltage supply circuit 227 has memory cells (not shown) in which the back gate voltage corresponding to the back gate voltage information input from the back gate voltage storage circuit 226 is arranged in the memory cell array 33 of the second sector 22. Apply to N-well.

Further, in the semiconductor memory devices 1 to 4, a single back gate voltage is applied to the macro cell MC arranged in the sector. However, in the semiconductor memory device according to the embodiment, a different back gate voltage may be applied to each macro cell MC arranged in the sector.

FIG. 25 is a diagram showing a second modification of the macro cell included in the semiconductor memory device according to the embodiment. In FIG. 25, the back voltage supply circuit and the back voltage storage circuit for supplying the back gate voltage to the second sector are omitted for the sake of simplicity.

The memory core 20 differs from the memory core 15 in that the first sector 91 and the second sector 92 are arranged instead of the first sector 21 and the second sector 22. In the memory core 20, the back gate voltage storage circuits 326 to 626 and the back gate voltage supply circuits 327 to 627 are arranged in place of the back gate voltage storage circuit 26 and the back gate voltage supply circuit 227. Be different. The configurations and functions of the constituent elements of the memory core 20 other than the first sector 91, the second sector 92, the back gate voltage storage circuits 326 to 626, and the back gate voltage supply circuits 327 to 627 are the same. This is the same as the configuration and function of the constituent elements of. Detailed description of the configurations and functions of the components of the memory core 20 other than the first sector 91, the second sector 92, the back gate voltage storage circuits 326 to 626, and the back gate voltage supply circuits 327 to 627 will be omitted here. The first sector 91 and the second sector 92 are different from the first sector 21 and the second sector 22 in that the memory cell array 93 is arranged instead of the memory cell array 33. The configurations and functions of the components of the first sector 91 and the second sector 92 other than the first sector 91 and the second sector 92 are the same as those of the components of the first sector 21 and the second sector 22 to which the same reference numerals are assigned. Since the function is the same, detailed description is omitted here.

The configurations and functions of the back gate voltage storage circuits 326 to 626 are similar to those of the back gate voltage storage circuit 26, and therefore detailed description thereof is omitted here. Further, the configurations and functions of the back gate voltage supply circuits 327 to 627 are similar to those of the back gate voltage supply circuit 27, and therefore detailed description thereof will be omitted here.

FIG. 26 is a more detailed internal circuit block diagram of the first sector 91.

In the memory cell array 93, four N wells N wells 910 to N913 are formed. Three macro cells MC connected to the bit line BL0 are formed in the N well 910, and three macro cells MC connected to the bit line BL1 are formed in the N well 911. In addition, three macro cells MC connected to the bit line BL2 are formed in the N well 912, and three macro cells MC connected to the bit line BL3 are formed in the N well 913. The back gate voltage VNW0 is applied from the back gate voltage supply circuit 327 to the N well 910, and the back gate voltage VNW1 is applied from the back gate voltage supply circuit 427 to the N well 911. The back gate voltage VNW2 is applied from the back gate voltage supply circuit 527 to the N well 912, and the back gate voltage VNW3 is applied from the back gate voltage supply circuit 627 to the N well 913.

Further, the semiconductor memory device 2 has two back gate voltage memory circuits, but the semiconductor memory device according to the embodiment may have three or more back gate voltage memory circuits depending on the temperature. Since the semiconductor memory device according to the embodiment has three or more back gate voltage memory circuits according to temperature, the back gate voltage can be controlled with high accuracy according to temperature.

1 to 4 semiconductor memory device 15 to 20 memory core 25 leak current determination circuit 26 back gate voltage memory circuit 27 back gate voltage supply circuit 31 row decoder (first selection circuit)
32 column switch (second selection circuit)
33 memory cell array MC memory cell M1 selection transistor (selection switch)
M2 Non-volatile memory transistor (memory element)

Claims (7)

A plurality of memory cells arranged in an array and each having a memory element and a selection switch for connecting between any one of a plurality of bit lines extending in the first direction and the memory element according to a selection signal. When,
A first selection circuit that outputs the selection signal that selects one of the plurality of memory cells arranged in a second direction orthogonal to the first direction;
A second selection circuit for selecting any one of the plurality of bit lines;
In at least one bit line of the plurality of bit lines, in the state where all the memory cells connected to the bit line of the plurality of memory cells are not selected by the selection signal, A leakage current determination circuit that determines whether or not the magnitude of the flowing leakage current is less than or equal to a reference current value,
A back gate voltage supply circuit capable of applying a back gate voltage to the back gates of the plurality of memory cells;
A back gate voltage storage circuit that stores one or more back gate voltage information indicating the back gate voltage,
A semiconductor memory device having a. A temperature sensor for detecting the temperature of the semiconductor memory device;
A back gate voltage to be output to the back gate voltage supply circuit by selecting one of the two or more back gate voltages stored in the back gate voltage storage circuit according to the temperature detected by the temperature sensor. A selection circuit,
The semiconductor memory device according to claim 1, further comprising: 3. The semiconductor memory device according to claim 1, wherein the leak current determination circuit collectively detects leak currents flowing in the plurality of bit lines. The plurality of memory cells are arranged in a plurality of sectors in which wells are separated,
The semiconductor memory device according to claim 1, wherein the back gate voltage supply circuit supplies the back gate voltage to each of the plurality of sectors. The plurality of memory cells are formed in a plurality of wells separated along the first direction in which the plurality of bit lines extend,
The semiconductor memory device according to claim 1, wherein the back gate voltage supply circuit supplies the back gate voltage to each of the plurality of wells. A plurality of memory cells arranged in an array and each having a memory element and a selection switch for connecting between the memory element and one of a plurality of bit lines extending in the first direction according to a selection signal. A method for controlling a semiconductor memory device including:
In at least one bit line of the plurality of bit lines, when all the memory cells connected to the bit line of the plurality of memory cells are not selected by the selection signal, Detects the leak current that flows,
The back gate voltage is determined such that the magnitude of the leakage current is equal to or less than a predetermined reference current value,
Storing back gate voltage information indicating the back gate voltage,
Outputting the back gate voltage to the back gate of the memory cell,
A method for controlling a semiconductor memory device including: It is determined whether the magnitude of the leak current is equal to or more than a predetermined upper limit current value,
The bit line determined to have a magnitude of the leakage current equal to or larger than a predetermined upper limit current value is excluded from the bit lines determining the back gate voltage.
7. The method for controlling a semiconductor memory device according to claim 6, further comprising:

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