JP2006072391A - Source line drive circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a source line drive circuit which is capable of shortening times required for charging/discharging source lines to prescribed levels, by reducing current consumption when charging/discharging parasitic capacitances, and is capable of implementing noise countermeasures. <P>SOLUTION: A source driver part 20 as a source driving circuit includes source drivers SD 1 to SDm for applying voltages to source lines S1 to Sm; first switches SWA1 to SWAm for electrically connecting the source lines S1 to Sm and the source drivers SD1 to SDm during a first period; an electrode to which a prescribed potential Vcom is given; and second switches SWB1 SWBm for electrically connecting the source lines S1 to Sm and the electrode during a second period that differs from the first period. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a driving circuit and a driving method for a liquid crystal display device using an active matrix panel, and more particularly, to reduce current consumption in a TFT (thin film transistor) type liquid crystal panel driving method and to output multi-grayscale. The present invention relates to a source line driving circuit that shortens the convergence time of a source driver output to a target value.

  In the active matrix display system, a non-linear active element is disposed in each pixel, so that interference of extra signals can be eliminated and high image quality can be realized.

  In the conventional active matrix display system, a matrix electrode, a plurality of liquid crystal capacitors (pixel capacitors) are arranged on the inward surface of one electrode substrate, and, for example, a TFT element is arranged as a switching element for each liquid crystal capacitor. Matrix driving is performed, and each liquid crystal capacitance is switched through a switching element.

  FIG. 18 is a diagram showing a configuration of a dot inversion driving circuit of a conventional TFT type liquid crystal panel.

  In FIG. 18, reference numeral 1 denotes a liquid crystal panel (hereinafter referred to as an LCD panel). The LCD panel 1 includes switch transistors TR11 to TRnm, liquid crystal electrodes CX11 to CXnm, and a common electrode (not shown) for applying a voltage level Vcom. Liquid crystal pixels are configured, and the pixels are arranged in a matrix.

  The driving circuit for driving the LCD panel 1 includes gate drivers GD1 to GDn for driving the gate lines G1 to Gn, source lines S1 to Sm, and parasitic capacitances CC1 to CCm parasitic on the source lines S1 to Sm. Although the capacitors CC1 to CCm may not be touched, the source drivers SD1 to SDm are configured to drive the source lines).

  FIG. 19 is a diagram of a TFT type liquid crystal panel similar to FIG. 18, and shows parasitic capacitances CC1 to CCn parasitic to the gate lines G1 to Gn.

  As an example, the drive circuits in FIGS. 18 and 19 are driven with a gate driver drive waveform shown in FIG. 20 and a source driver drive waveform shown in FIG.

  Since the brightness (color) of a predetermined dot of the TFT type liquid crystal is determined by the potential level charged in the liquid crystal capacitor, the source drivers SD1 to SDm operate to output an output voltage corresponding to the video signal. The gate drivers GD1 to GDn operate to output gate drive pulse signals with sequentially shifted phases to the gate lines G1 to Gn to output levels for turning on / off the switch transistors TR11 to TRnm.

  The operation will be briefly described with reference to FIGS.

  In FIG. 20, it is assumed that the source drivers SD1 to SDm can output 64 gradation levels (hereinafter, unless otherwise specified, the source driver will describe an example of 64 gradations) arbitrary source driver SDk-1 (k is 1). (Any number of .about.m) outputs one selected level (higher than Vcom) of predetermined 64 analog levels higher than Vcom, and charges the source line Sk-1 to a predetermined level.

  At the same time, the source driver SDk adjacent to SDk-1 outputs one level (lower than Vcom) selected from the predetermined 64 analog levels lower than Vcom, and charges the source line Sk to the predetermined level. . In this way, the source drivers SD1 to SDm charge the source lines S1 to Sm so that the polarities of adjacent source lines are reversed with reference to the Vcom level. At the same time, the gate line G1 becomes H level by the gate driver GD1.

  By this operation, the switch transistors TR11 to TR1m are turned on, and the output levels of the source drivers SD1 to SDm are charged to the liquid crystal capacitors CX11 to CΧ1m through the source lines S1 to Sm, respectively. Next, the gate driver GD1 sets the gate line G1 to the L level, and the gate driver GD2 sets the gate line G2 to the Η level. At the same time, the source drivers SD1 to SDm are charged with the liquid crystal capacitors CΧ21 to CΧ2m. Driven by.

  At this time, as shown in FIG. 21, the level set for the source line has a polarity opposite to that of the Vcom level when G1 is at the heel level.

  For example, in the source line S1, when the gate line G1 is at H level, the liquid crystal capacitor is charged with a level higher than Vcom, but when G1 becomes L level and G2 becomes H level, the level lower than Vcom is set. It becomes operation to charge.

  By repeating this operation, the gate line Gi (i is an arbitrary number from 1 to n) is set to H level, and a predetermined potential level is written to all the liquid crystal capacitors CX11 to CXnm. In the next frame, AC driving is performed by writing a level opposite in polarity to Vcom with respect to the liquid crystal capacitance.

  However, such a conventional liquid crystal display device has the following problems.

  That is, in the above operation, when the gate line G1 is at the low level, if the liquid crystal capacitor CX11 is charged with a level higher than Vcom through the source line S1, the liquid crystal is displayed when G1 becomes L level and G2 becomes H level. The capacitor CX11 is charged with a level lower than Vcom through the source line S1. Usually, the parasitic capacitance CC1 of the source line S1 is about 150 pF, and the liquid crystal capacitance CX11 is about 8 pF. Therefore, the source driver SD1 discharges the parasitic capacitance CC1 of the source line S1 charged at a level higher than Vcom to a level lower than Vcom. There is a need.

  Therefore, a large amount of current is consumed when charging / discharging the parasitic capacitance, and it takes time to charge / discharge the source line to a predetermined level. Furthermore, noise is generated due to the consumption current when charging / discharging the parasitic capacitance. There was a problem that there was.

  Further, as shown in FIG. 19, since each of the gate lines G1 to Gn has parasitic capacitances CC1 to CCn, it is necessary to design the gate drivers GD1 to GDn so that the parasitic capacitances CC1 to CCn can be charged and discharged. This leads to an increase in the size of the gate driver. Further, accompanying the charging / discharging of the parasitic capacitance, an increase in current consumption or power consumption has been caused.

  In addition, it takes time to charge / discharge the gate line to a predetermined level, and noise may occur due to current consumption during charging / discharging of the parasitic capacitance.

  The present invention provides a source line driving circuit for a liquid crystal display device that can reduce current consumption during charging / discharging of a parasitic capacitance and can shorten the time for charging / discharging the source line to a predetermined level. The purpose is to do.

  It is another object of the present invention to provide a source line driving circuit of a liquid crystal display device capable of taking noise countermeasures by controlling charging / discharging of parasitic capacitance.

  The source line driver circuit of the present invention includes a source driver that applies a voltage to the source line, a first switch that electrically connects the source line and the source driver in a first period, and a predetermined potential. An electrode provided; and a second switch for electrically connecting the source line and the electrode in a second period different from the first period.

  The driving circuit of the liquid crystal display device of the reference example drives the gate line in the driving circuit of the liquid crystal display device that drives a liquid crystal display unit having a switching element and a liquid crystal capacitor at each intersection of a plurality of gate lines and a plurality of source lines. A gate line driving unit, a source driver electrically disconnected from the source line by a first switch in a certain period, and a source line and a node to which a predetermined potential is applied. And a second line switch electrically connecting the node and a source line driving unit.

  The driving method of the liquid crystal display device of the reference example includes a source driver that drives the source line of the liquid crystal display unit, a first switch provided between the source driver and the source line, one end connected to the source driver, and the other A driving method of a liquid crystal display device having a source line driving unit configured by a second switch connected to a node to which a predetermined potential is applied, and driving the liquid crystal driving unit. During the period, the first switch is turned on and the second switch is turned off. During the second period, the first switch is turned off and the second switch is turned on. It is characterized by.

  The liquid crystal display device of the reference example is a liquid crystal display device having a source driver for driving the source line of the liquid crystal display unit, the first switch for electrically disconnecting the source driver and the source line in a certain period, and the period And a second switch for applying a predetermined potential to the source driver.

  In the source line driving circuit according to the present invention, in the first period, the source driver and the source line are connected by the first switch, and the source line is separated from the electrode to which a predetermined potential is applied by the second switch. In the second period, the source line is disconnected from the source driver by the first switch, and the source line is connected to the electrode to which the predetermined potential is applied by the second switch. Current consumption can be reduced, and the time for charging / discharging the source line to a predetermined level can be shortened. In addition, since a source line driving unit having a smaller driving capability can be used, the size and cost of the source line driving unit can be reduced.

  The source line driver circuit according to the present invention can be applied to a liquid crystal display device used in a liquid crystal television or the like.

First Embodiment FIG. 1 is a block diagram showing a configuration of a liquid crystal display device according to a first embodiment of the present invention. In the description of the drive circuit and the drive method of the liquid crystal display device according to the present embodiment, the same components as those in FIG.

  In FIG. 1, reference numeral 1 denotes an LCD panel. The LCD panel 1 is parasitic on the gate driver (GD1 to GDn) portion 10 for driving the gate lines G1 to Gn, the source lines S1 to Sm, and the source lines S1 to Sm. The source driver section 20 drives the parasitic capacitors CC1 to CCm.

  The LCD panel 1 includes liquid crystal pixels each composed of switch transistors TR11 to TRnm, liquid crystal electrodes CX11 to CXnm, and a common electrode (not shown) for applying a voltage level Vcom, and the pixels are arranged in a matrix. .

  The source driver unit 20 includes source drivers SD1 to SDm for driving the source lines S1 to Sm and parasitic capacitances CC1 to CCm parasitic to the source lines S1 to Sm, and outputs of the source drivers SD1 to SDm from the source lines S1 to Sm. The switches SWA1 to SWAm and SWB1 to SWBm are short-circuited to the potential Vcom of the separation common electrode. These switches can be easily built in the driver by transistors such as FETs.

  In this way, the LCD panel 1, the gate driver unit 10 including the gate drivers GD1 to GDn for driving the gate lines G1 to Gn, and the switch SWA1 that enables the outputs of the source drivers SD1 to SDm to be connected to the source lines S1 to Sm. To SWAm and SWB1 to SWBm, the source driver unit 20 is configured to connect the potential Vcom of the common electrode and the source lines S1 to Sm. In the source driver unit 20, the source lines S1 to Sm are connected at a predetermined timing. By short-circuiting the Vcom level, current consumption is reduced and the time for charging / discharging the source lines S1 to Sm to a predetermined level is shortened.

  Hereinafter, the operation of the liquid crystal display device configured as described above will be described.

  2 is a waveform diagram showing drive waveforms of the gate driver section, FIG. 3 is a waveform chart showing drive waveforms of the source drivers SD1 to SDm of the source driver section, and FIG. 2 is the same as FIG.

  The driving circuit of the present liquid crystal display device is driven by the gate driver driving waveform shown in FIG. 2 and the source driver driving waveform shown in FIG. In this embodiment, a case where 64-gradation display is performed will be described as an example.

  First, in FIG. 2, assuming that a source driver can output 64 gradation levels as an example, an arbitrary source driver SDk-1 is selected from a predetermined 64 analog levels higher than the potential Vcom of the common electrode. A level (higher than Vcom) is output and the source line Sk-1 is charged to a predetermined level. At the same time, the source driver SDk adjacent to SDk-1 outputs one level (lower than Vcom) selected from the predetermined 64 analog levels lower than Vcom, and charges the source line Sk to the predetermined level. That is, in this state, the switches SWA1 to SWAm are in the on state, and the switches SWB1 to SWBm are in the off state.

  Thus, the source drivers SD1 to SDm charge the source lines S1 to Sm so that the polarities of the adjacent source lines are reversed with reference to the Vcom level. At the same time, the gate line G1 becomes H level by the gate driver GD1. By this operation, the transistors TR11 to TR1m are turned on, and the output levels of the source drivers SD1 to SDm are charged into the liquid crystal capacitors CΧ11 to CX1m through the source lines S1 to Sm, respectively.

  Next, the gate line G1 is set to L level by the gate driver GD1, G2 is set to low level by GD2, the switches SWA1 to SWAm as the components of the source driver unit 20 are turned off, and the switches SWB1 to SWBm are turned on. By doing so, all the source lines S1 to Sm are short-circuited to the potential level Vcom of the common electrode.

  At this time, the number of source lines in which charges higher than Vcom are stored and the number of source lines in which charges lower than Vcom are stored are halved. Since the operation of charging the level is also an operation of moving the charge through Vcom (depending on the state of the source level at that time), the charge is canceled to some extent.

  Thereafter, the switches SWA1 to SWAm are turned off and the switches SWB1 to SWBm are turned on, and the source drivers SD1 to SDm1 output a predetermined level and charge the source lines S1 to Sm to the level for charging the next liquid crystal capacitance. . Since operations other than the operation of disconnecting the source drivers SD1 to SDm and shorting them to the Vcom level before writing the next level to the source lines S1 to Sm are the same as those of the conventional example, the description of the subsequent operations is omitted.

  As described above, the driving circuit and the driving method for the liquid crystal display device according to the first embodiment include the LCD panel 1 and the gate driver unit 10 including the gate drivers GD1 to GDn for driving the gate lines G1 to Gn. The source driver unit 20 enables connection of the potential Vcom of the common electrode and the source lines S1 to Sm via the switches SWA1 to SWAm and SWB1 to SWBm that allow the outputs of the source drivers SD1 to SDm to be connected to the source lines S1 to Sm. Since the outputs of the source drivers SD1 to SDm are separated from the source lines S1 to Sm by the switches SWA1 to SWAm and SWB1 to SWBm at the initial stage of writing to the liquid crystal capacitor, they are short-circuited to the common electrode potential Vcom. Charge due to short-circuiting to the Vcom level of the charge accumulated in all source lines Since it is performed by movement, current consumption can be reduced as compared with the case where the source driver charges all the source lines to a level opposite to the Vcom level.

  That is, in the conventional example, the charges accumulated in all the source lines (particularly, the charges of the parasitic capacitances CC1 to CCm) are moved by the capability of the source driver, and then the source lines S1 to Sm are driven. The source driver required greater driving capability and associated current consumption. On the other hand, in this driving method, the charges accumulated in all the source lines (particularly, the charges of the parasitic capacitances CC1 to CCm) are disconnected from the source drivers SD1 to SDm before the next level is written, and the source lines S1 to Sm are connected. Since the source line S1 to Sm is driven after the charge is extinguished by short-circuiting with the Vcom level, the source driver only needs to have the drive capability of the source line S1 to Sm. It becomes possible to do. Further, it is possible to reduce the size and cost of the source driver.

  Further, by performing charge transfer with a resistance lower than the output impedance of the source driver, the time required for setting the source line to a predetermined level can be shortened.

  In the present embodiment, an example in which a liquid crystal capacitor that is always adjacent to each other on one gate line is charged with a potential having a polarity opposite to that of Vcom is described. However, for each arbitrary dot, Vcom is described. However, it goes without saying that the same effect can be obtained by charging a potential having the opposite polarity.

Second Embodiment FIG. 4 is a block diagram showing a configuration of a liquid crystal display device according to a second embodiment of the present invention. In the description of the drive circuit and the drive method of the liquid crystal display device according to the present embodiment, the same components as those in FIG.

  In FIG. 4, reference numeral 1 denotes an LCD panel. The LCD panel 1 is parasitic on the gate driver (GD1 to GDn) section 10 for driving the gate lines G1 to Gn, the source lines S1 to Sm, and the source lines S1 to Sm. The source driver unit 30 drives the parasitic capacitors CC1 to CCm.

  The source driver unit 30 includes source drivers SD1 to SDm for driving the source lines S1 to Sm and parasitic capacitances CC1 to CCm parasitic to the source lines S1 to Sm, and outputs of the source drivers SD1 to SDm from the source lines S1 to Sm. It is composed of switches SWC1 to SWCm and SWD1 to SWDm-1 for separating and shorting adjacent source lines.

  As described above, the LCD panel 1, the gate driver section 10 including the gate drivers GD1 to GDn for driving the gate lines G1 to Gn, and the outputs of the source drivers SD1 to SDm are passed through the switches SWC1 to SWCm and SWD1 to SWDm-1. The source driver unit 20 is connected to the driver output next to the adjacent driver output. In the source driver unit 20, the switches SWC1 to SWCm are turned off and the SWD1 to SWDm-1 are turned on at a predetermined timing, thereby reducing current consumption. In addition, the time for charging / discharging the source lines S1 to Sm to a predetermined level is shortened. In this configuration, it is not necessary to supply the Vcom level to the source driver unit as in the first embodiment described above.

  Hereinafter, the operation of the liquid crystal display device configured as described above will be described.

  The driving circuit of the present liquid crystal display device is driven by the gate driver driving waveform shown in FIG. 2 and the source driver driving waveform shown in FIG. In this embodiment, a case where 64-gradation display is performed will be described as an example.

  First, in FIG. 2, an arbitrary source driver SDk-1 outputs a predetermined level higher than the potential Vcom of the common electrode, and charges the source line Sk-1 to a predetermined level. At the same time, the source driver SDk next to SDk-1 outputs a predetermined level lower than Vcom and charges the source line Sk to a predetermined level. Thus, the source drivers SD1 to SDm charge the source lines S1 to Sm so that the polarities of the adjacent source lines are reversed with reference to the Vcom level. At the same time, the gate line G1 becomes H level by the gate driver GD1. That is, in this state, the switches SWC1 to SWCm are in an on state, and the switches SWD1 to SWDm-1 are in an off state.

  By this operation, the transistors TR11 to TR1m are turned on, and the output levels of the source drivers SD1 to SDm are charged to the liquid crystal capacitors CX11 to CΧ1m through the source lines S1 to Sm, respectively.

  Next, the gate line G1 is set to L level by the gate driver GD1, the gate line G2 is set to low level by the gate driver GD2, and the switches SWC1 to SWCm that are components of the source driver unit 30 are turned off, and the switches SWD1 to SWD1 All source lines are short-circuited by turning on SWDm-1.

  At this time, since the number of source lines in which charges higher than Vcom are stored and the number of source lines in which charges lower than Vcom are stored are halved, charge transfer occurs (the source level at that time). The charge is canceled out (depending on the state of (1)) and becomes a level close to Vcom rather than the level of the original source line.

  Thereafter, the switches SWC1 to SWCm are turned off, the switches SWD1 to SWDm-1 are turned on, and the source drivers SD1 to SDm1 output a predetermined level to charge the source lines S1 to Sm to a level for charging the next liquid crystal capacitance. . Since the operation other than the operation of disconnecting the source driver and shorting it to the Vcom level before writing the next level to this source line is the same as the conventional example, the description of the subsequent operations is omitted.

  As described above, in the liquid crystal display device driving circuit and the driving method thereof according to the second embodiment, the switch SWC1 that disconnects the outputs of the source drivers SD1 to SDm from the source lines S1 to Sm and shorts adjacent source lines. Source driver section 30 having SWCm and SWD1 to SWDm-1, and source driver section 30 has source lines S1 to Sm so that the polarity of adjacent source lines S1 to Sm is reversed with respect to the potential of the common electrode. In the case of the driving method for driving the liquid crystal capacitor, the outputs of the source drivers SD1 to SDm are disconnected from the source lines S1 to Sm at the initial stage of writing to the liquid crystal capacitor, and the adjacent source lines S1 to Sm are short-circuited. As in the first embodiment, the source driver charges the entire source line to a level opposite to the Vcom level. It is possible to reduce the current consumption than that.

  In particular, in the present embodiment, the charge accumulated in all source lines is charged to near the Vcom level by charge transfer due to a short circuit between the source lines, so that the Vcom level is set in the source driver section as in the first embodiment. The current consumption can be reduced without supply. Further, by performing charge transfer with a resistance lower than the output impedance of the source driver, the time required for setting the source line to a predetermined level can be shortened.

  Furthermore, the liquid crystal display device according to the present embodiment includes switches SWC1 to SWCm for disconnecting the outputs of the source drivers SD1 to SDm from the source lines S1 to Sm, in addition to the switches SWD1 to SWDm-1 that short-circuit the source lines. ON / OFF timing of the switches described above, that is, the switches SWC1 to SWCm are first turned on and the switches SWD1 to SWDm-1 are turned off so that the adjacent source lines have opposite polarities with reference to the Vcom level. The drivers SD1 to SDm charge the source lines S1 to Sm, then turn off the switches SWC1 to SWCm and turn on the switches SWD1 to SWDm-1, thereby shorting all the source lines. In this way, before writing the next level to the source line, the source driver is disconnected and shorted to the Vcom level.

  Therefore, the adjacent source lines are not simply short-circuited by a switch, but the source lines are short-circuited after the source driver output is separated from the source lines. (Differences in wiring resistance, wiring capacity, etc. leading to each source driver) are not received.

  In the present embodiment, an example in which a liquid crystal capacitor that is always adjacent to each other on one gate line is charged with a potential having a polarity opposite to that of Vcom is described. However, for each arbitrary dot, Vcom is described. However, it goes without saying that the same effect can be obtained by charging a potential of opposite polarity.

Third Embodiment FIG. 5 is a block diagram showing a configuration of a liquid crystal display device according to a third embodiment of the present invention. In the description of the drive circuit and the drive method of the liquid crystal display device according to the present embodiment, the same components as those in FIG.

  In FIG. 5, reference numeral 1 denotes an LCD panel. The LCD panel 1 is parasitic on the gate driver (GD1 to GDn) unit 10 for driving the gate lines G1 to Gn, the source lines S1 to Sm, and the source lines S1 to Sm. The source driver unit 40 drives the parasitic capacitors CC1 to CCm.

  The source driver section 40 includes source drivers SD1 to SDm for driving the source lines S1 to Sm and parasitic capacitances CC1 to CCm parasitic to the source lines S1 to Sm, and outputs of the source drivers SD1 to SDm from the source lines S1 to Sm. It is composed of switches SWC1 to SWCm and SWD1 to SWDm-1 for separating and shorting adjacent source lines. Further, the switches SWD1 to SWDm-1 are installed every other one instead of connecting all the source driver outputs as in the second embodiment.

  In this way, in the driving system in which the adjacent liquid crystal capacitors are always charged with a potential having a polarity opposite to that of Vcom, the gate driver unit comprising the LCD panel 1 and the gate drivers GD1 to GDn for driving the gate lines G1 to Gn. 10 and the output of the source drivers SD1 to SDm are composed of every other driver output 30 connected to the adjacent driver output via the switches SWC1 to SWCm and SWD1 to SWDm-1. By turning off the switches SWC1 to SWCm and turning on the SWD1 to SWDm-1 at the timing, the current consumption is reduced and the time for charging / discharging the source lines S1 to Sm to a predetermined level is shortened. In this configuration, it is not necessary to supply the Vcom level to the source driver unit as in the first embodiment, and the number of switches for connecting to the adjacent driver is reduced to half compared to the second embodiment. it can.

  Hereinafter, the operation of the liquid crystal display device configured as described above will be described.

  The driving circuit of the present liquid crystal display device is driven by the gate driver driving waveform shown in FIG. 2 and the source driver driving waveform shown in FIG. In this embodiment, a case where 64-gradation display is performed will be described as an example.

  First, in FIG. 2, an arbitrary source driver SDk-1 outputs a predetermined level higher than the potential Vcom of the common electrode, and charges the source line Sk-1 to a predetermined level. At the same time, the source driver SDk next to SDk-1 outputs a predetermined level lower than Vcom and charges the source line Sk to a predetermined level. Thus, the source drivers SD1 to SDm charge the source lines S1 to Sm so that the polarities of the adjacent source lines are reversed with reference to the Vcom level. At the same time, the gate line G1 is set to the low level by the gate driver GD1. That is, in this state, the switches SWC1 to SWCm are in an on state, and the switches SWD1 to SWDm-1 are in an off state.

  By this operation, the transistors TR11 to TR1m are turned on, and the output levels of the source drivers SD1 to SDm are charged to the liquid crystal capacitors CX11 to CX1m through the source lines S1 to Sm, respectively.

  Next, the gate line G1 is set to the L level by the gate driver GD1, the gate line G2 is set to the low level by the gate driver GD2, SWC1 to SWCm which are the components of the source driver are turned off, and SWD1 to SWDm-1 are set. All source lines are shorted by turning them on.

  At this time, since the number of source lines in which charges higher than Vcom are stored and the number of source lines in which charges lower than Vcom are stored are halved, charge transfer occurs (the source level at that time). The charge is canceled out (depending on the state) and becomes a level closer to Vcom than the original source line level, and is stabilized.

  Thereafter, the switches SWC1 to SWCm are turned off, the switches SWD1 to SWDm-1 are turned on, and the source drivers SD1 to SDm output a predetermined level to charge the source lines S1 to Sm to a level for charging the next liquid crystal capacitance. To do.

  Other than the operation of disconnecting the source driver and shorting it to the Vcom level before writing the next level to the source lines S1 to Sm, it is the same as the conventional example.

  As described above, the driving circuit and the driving method of the liquid crystal display device according to the third embodiment are based on the premise that the driving method is such that the adjacent liquid crystal capacitor is charged with a potential having a polarity opposite to that of Vcom. The driver unit 40 includes switches SWC1 to SWCm and SWD1 to SWDm-1 that disconnect the outputs of the source drivers SD1 to SDm from the source lines S1 to Sm and short-circuit adjacent source lines, and every other switch SWD1 to SWDm-1 Since the number of switches SWC1 to SWCm is half the number so that the adjacent source driver outputs are short-circuited, the source driver sets all the source lines to a phase opposite to the Vcom level as in the second embodiment. Current consumption can be reduced compared to charging, and charge transfer is performed with resistance lower than the output impedance of the source driver. By performing the above, it is possible to shorten the time until the source line is set to a predetermined level.

  In particular, in the present embodiment, every other switch SWD1 to SWDm-1 for short-circuiting the driver output is installed, so that the number of switches SWD1 to SWDm-1 can be halved compared to the second embodiment. it can.

Fourth Embodiment FIG. 6 is a block diagram showing a configuration of a liquid crystal display device according to a fourth embodiment of the present invention. In the description of the driving circuit and the driving method of the liquid crystal display device according to the present embodiment, the same components as those in FIG.

  In FIG. 6, reference numeral 1 denotes an LCD panel. The LCD panel 1 is parasitic on the gate driver (GD1 to GDn) section 10 for driving the gate lines G1 to Gn, the source lines S1 to Sm, and the source lines S1 to Sm. The source driver unit 50 drives the parasitic capacitors CC1 to CCm.

  The source driver unit 50 includes source drivers SD1 to SDm for driving the source lines S1 to Sm and parasitic capacitances CC1 to CCm parasitic to the source lines S1 to Sm, and outputs of the source drivers SD1 to SDm from the source lines S1 to Sm. The switches SWA1 to SWAm and SWB1 to SWBm are separated from each other, and the source lines S1 to Sm are short-circuited to the potential Vcom of the common electrode via the resistor R1.

  As described above, the LCD panel 1, the gate driver unit 10 including the gate drivers GD1 to GDn for driving the gate lines G1 to Gn, and the switch SWA1 that enables the outputs of the source drivers SD1 to SDm to be connected to the source lines S1 to Sm. Is composed of a source driver unit 50 that can be connected to the potential Vcom of the common electrode via SWAm and SWB1 to SWBm. In the source driver unit 50, a source is connected via a resistor R1 by turning on a switch at a predetermined timing. The charge accumulated in the lines S1 to Sm is moved to reduce the peak current during discharge and take measures against noise.

  Hereinafter, the operation of the liquid crystal display device configured as described above will be described.

  The driving circuit of the present liquid crystal display device is driven by the gate driver driving waveform shown in FIG. 2 and the source driver driving waveform shown in FIG. In this embodiment, a case where 64-gradation display is performed will be described as an example.

  2 and 6, the gate line GD1 is set to L level by the gate driver GD1, and G2 is set to H level by the gate driver GD2, so that the switches SWA1 to SWAm that are components of the source driver unit 50 are turned off. All the source lines S1 to Sm are short-circuited with the potential level Vcom of the common electrode by turning on SWB1 to SWBm. At this time, if the charge is moved too quickly, the level of the gate line is affected by the parasitic capacitance between the lines at the intersection of the source line and the gate line, which may cause a malfunction. This phenomenon is likely to occur in a switch transistor far from the gate driver. In order to avoid this situation, in the present embodiment, the charge movement is controlled through the resistor R1, thereby controlling the charge movement and suppressing the peak current. In addition, by making this switch and resistor with a transistor, it can be easily built into the bag C.

  As described above, in the driving circuit and the driving method for the liquid crystal display device according to the fourth embodiment, charge transfer to the vicinity of the Vcom level of charges accumulated in all source lines is performed via the resistor R1. Therefore, malfunction due to the line capacitance of the source line and the gate line can be prevented.

Fifth Embodiment FIG. 7 is a block diagram showing a configuration of a liquid crystal display device according to a fifth embodiment of the present invention. In the description of the drive circuit and the drive method of the liquid crystal display device according to the present embodiment, the same components as those in FIG.

  In FIG. 7, reference numeral 1 denotes an LCD panel. The LCD panel 1 is parasitic on the gate driver (GD1 to GDn) portion 10 for driving the gate lines G1 to Gn, the source lines S1 to Sm, and the source lines S1 to Sm. The source driver unit 60 drives the parasitic capacitors CC1 to CCm.

  The source driver unit 60 includes source drivers SD1 to SDm for driving source lines S1 to Sm and parasitic capacitances CC1 to CCm parasitic to the source lines S1 to Sm, and outputs of the source drivers SD1 to SDm from the source lines S1 to Sm. It is composed of switches SWC1 to SWCm and SWD1 to SWDm-1 for short-circuiting adjacent source lines via a separation resistor R2.

  In this way, the LCD panel 1, the gate driver unit 10 including the gate drivers GD1 to GDn for driving the gate lines G1 to Gn, and the switch SWC1 that enables the outputs of the source drivers SD1 to SDm to be connected to the source lines S1 to Sm. Is composed of a source driver unit 60 that can be connected to the adjacent source lines S1 to Sm via SWCm and SWD1 to SWDm-1, and the resistor R2 is turned on by switching on the source driver unit 60 at a predetermined timing. The charge accumulated in the source lines S1 to Sm is moved through the circuit to reduce the peak current during discharge and take measures against noise.

  Hereinafter, the operation of the liquid crystal display device configured as described above will be described.

  The driving circuit of the present liquid crystal display device is driven by the gate driver driving waveform shown in FIG. 2 and the source driver driving waveform shown in FIG.

  2 and 7, the gate line G1 is set to the L level by the gate driver GD1, the gate line G2 is set to the low level by the gate driver GD2, and the switches SWC1 to SWCm that are components of the source driver unit 30 are turned off. All the source lines are short-circuited by turning on the switches SWD1 to SWDm-1.

  At this time, if the charge is moved too quickly, the level of the gate line is affected by the parasitic capacitance between the lines at the intersection of the source line and the gate line, which may cause a malfunction. This phenomenon is likely to occur in a switch transistor far from the gate driver. In order to avoid this situation, in the present embodiment, the charge movement is controlled via the resistor R2, thereby controlling the charge movement and suppressing the peak current. In addition, by making this switch and resistor with a transistor, it can be easily built into the bag C.

  As described above, in the driving circuit and the driving method for the liquid crystal display device according to the fifth embodiment, the switch SWC1 that disconnects the outputs of the source drivers SD1 to SDm from the source lines S1 to Sm and shorts adjacent source lines. To SWCm and SWD1 to SWDm-1, and the charge transfer due to the short circuit is performed via the resistor R2, the current consumption can be reduced as in the second embodiment, and the source line and It is possible to prevent malfunction due to the line capacitance of the gate line.

  In the present embodiment, the resistor R2 is inserted in the second embodiment shown in FIG. 4 to prevent malfunction at the time of short-circuit. Similarly, the resistor R2 in the third embodiment shown in FIG. R2 may be inserted to prevent malfunction at the time of short circuit. This resistor can be made of a transistor together with a switch.

Sixth Embodiment FIG. 8 is a block diagram showing a configuration of a liquid crystal display device according to a sixth embodiment of the present invention. In the description of the driving circuit and the driving method of the liquid crystal display device according to the present embodiment, the same components as those in FIG.

  In FIG. 8, reference numeral 1 denotes an LCD panel. The LCD panel 1 is parasitic on the gate driver (GD1 to GDn) portion 10 for driving the gate lines G1 to Gn, the source lines S1 to Sm, and the source lines S1 to Sm. The source driver unit 70 drives the parasitic capacitors CC1 to CCm.

  The source driver unit 70 receives source drivers SD1 to SDm for driving source lines S1 to Sm and parasitic capacitances CC1 to CCm parasitic to the source lines S1 to Sm, and outputs of the source drivers SD1 to SDm from the source lines S1 to Sm. The switches SWA1 to SWAm and SWB1 to SWBm are separated from each other and short-circuit the source lines S1 to Sm to the half potential VGD / 2 of the gate driver output.

  In this way, the LCD panel 1, the gate driver unit 10 including the gate drivers GD1 to GDn for driving the gate lines G1 to Gn, and the outputs of the source drivers SD1 to SDm are gated through the switches SWA1 to SWAm and SWB1 to SWBm. Consists of a source driver unit 70 connected to a half potential VGD / 2 of the driver output. In the source driver unit 70, the source lines S1 to Sm and the VGD / 2 level are short-circuited at a predetermined timing, thereby reducing current consumption. And the time for charging / discharging the source lines S1 to Sm to a predetermined level is shortened.

  Hereinafter, the operation of the liquid crystal display device configured as described above will be described.

  In this embodiment, the potential to be short-circuited at the initial stage of writing to the liquid crystal capacitor is changed from the potential level Vcom of the common electrode to the half potential VSD / 2 of the source driver output for the following reason. is there.

  That is, as a problem of the TFT, there is a phenomenon that the holding voltage is lowered (ΔVGD) with respect to the gate voltage change due to the gate-drain parasitic capacitance CGD of the TFT. If this voltage drop ΔVGD remains as a DC voltage, it may cause burn-in, flicker, etc. Normally, the DC voltage is not applied to the liquid crystal by shifting the potential level Vcom of the common electrode from the video center by an amount equivalent to the voltage drop ΔVGD. To remove.

  Therefore, the most preferable potential for disconnecting the source drivers SD1 to SDm and shorting the source lines S1 to Sm before writing the next level is not the potential Vcom of the common electrode but the potential shifted from the Vcom by the voltage drop ΔVGD. . In this embodiment, a potential corresponding to this potential is obtained from the half potential VSD / 2 of the source driver output.

  The operation is the same as that of the first embodiment except that the source drivers SD1 to SDm are disconnected and shorted to the VSD / 2 level before writing the next level to the source lines S1 to Sm.

  As described above, in the liquid crystal display device driving circuit and the driving method thereof according to the sixth embodiment, the charge accumulated in all the source lines is charged to the vicinity of the VSD / 2 level by the charge transfer. Current consumption can be reduced compared to when the source driver charges the source line to a level opposite to the VSD / 2 level, and the source is transferred to a predetermined level by performing charge transfer with a resistance lower than the output impedance of the source driver. Time to set a line can be shortened.

  In particular, the charge transfer due to the short circuit is not the common electrode potential Vcom but the source driver output ½ potential VSD / 2 which is shifted from the Vcom by an amount corresponding to the voltage drop ΔVGD. The effect mentioned above can be achieved effectively.

  Here, any potential may be used as long as the potential is shifted from the common electrode potential Vcom by an amount corresponding to the voltage drop ΔVGD, but in this embodiment, a potential that can be easily obtained as a half potential of the source driver output. VSD / 2 is used.

  In this embodiment, the half potential VSD / 2 of the source driver output is used in place of the common electrode potential Vcom in the first embodiment shown in FIG. 1, but the fourth embodiment shown in FIG. In this embodiment, the effect may be further enhanced by using the potential VSD / 2.

Seventh Embodiment In the liquid crystal display device as shown in FIG. 18, the current consumption is reduced by changing the drive waveforms by the gate driver and the source driver to those that output the drive waveforms as shown in FIGS. Can be planned. The configuration in this embodiment can be applied to the configuration shown in each of the above embodiments or the conventional configuration shown in FIG.

  For example, if the present embodiment is applied to the configuration shown in FIG. 18 and the drive waveforms shown in FIGS. 9 and 10 are used, charging of the opposite polarity to Vcom is performed for each gate line. However, the current consumption is reduced by reducing the number of times of charging / discharging the parasitic capacitance of the source line by performing it every several lines.

  Hereinafter, the operation of the liquid crystal display device configured as described above will be described.

  9 is a waveform diagram showing drive waveforms of the gate driver section, FIG. 10 is a waveform chart showing drive waveforms of the source drivers SD1 to SDm of the source driver section, and FIG. 9 is the same as FIG.

  The driving circuit shown in FIG. 18 is driven by the gate driver driving waveform of FIG. 9 and the source driver driving waveform of FIG. In the present embodiment, as shown in the source driver drive waveform of FIG. 10, the charging level is inverted every three lines with respect to Vcom.

  First, in FIG. 18, an arbitrary source driver SDk-1 outputs one (higher than Vcom) level selected from predetermined 64 analog levels higher than Vcom, and sets the source line Sk-1 to a predetermined level. Charge. At the same time, the source driver SDk adjacent to SDk-1 outputs one level (lower than Vcom) selected from the predetermined 64 analog levels lower than Vcom, and charges the source line Sk to the predetermined level. Thus, the source drivers SD1 to SDm charge the source lines S1 to Sm so that the polarities of the adjacent source lines are reversed with reference to the Vcom level. At the same time, the gate line G1 becomes H level by the gate driver GD1.

  By this operation, the transistors TR11 to TR1m are turned on, and the output levels of the source drivers SD1 to SDm are charged to the liquid crystal capacitors CX11 to CX1m through the source lines S1 to Sm, respectively.

  Next, the gate driver GD1 sets the gate line G1 to the L level, and the gate driver GD2 sets the gate line G2 to the H level. At the same time, the source lines SD1 to Sm are charged with the liquid crystal capacitors CΧ21 to CΧ2m. Driven by SDm.

  At this time, as shown in FIG. 10, the level set for the source line is charged at a level higher than the Vcom level in the same manner as when the gate line G1 is at the low level. Similarly, when the gate driver GD3 becomes the soot level, the level higher than the Vcom level is charged. A level lower than the Vcom level is charged for the first time when the gate driver GD4 becomes H level. Similarly, when the gate drivers GD5 and GD6 are at the low level, they are charged at a level lower than the Vcom level.

  In this way, the number of times of charging / discharging the parasitic capacitances CC1 to CCm of the source line is reduced by inverting the charging level for every three lines with respect to Vcom. Other operations are the same as in the prior art.

  As described above, in the driving circuit and the driving method of the liquid crystal display device according to the seventh embodiment, the gate driver (GD1 to GDn) unit 10 outputs the write level output to the liquid crystal capacitor every three gate lines. Since the common electrode is inverted, the number of times of charging / discharging across the parasitic capacitance Vcom of the source line is reduced, so that current consumption can be reduced.

  In this embodiment, as shown in the source driver drive waveform of FIG. 10, the charging level is inverted every three lines with respect to Vcom. However, the present invention is not limited to every three lines.

  In the present embodiment, the example applied to the conventional example of FIG. 18 has been described, but it is needless to say that the present invention is not limited to this and can be combined with the above-described embodiments. If combined with the above-described embodiments, the effects of the present embodiment can be added to the effects of the above-described embodiments.

  According to each of the first to seventh embodiments described above, current consumption during charging / discharging of the parasitic capacitances CC1 to CCm parasitic to the source lines S1 to Sm can be reduced, and the source lines can be reduced to a predetermined level. The time for charging / discharging could be shortened.

  By the way, as described in the conventional example of FIG. 19, since each gate line G1 to Gn has parasitic capacitances CC1 to CCn, the gate drivers GD1 to GDn are designed to charge and discharge the parasitic capacitances CC1 to CCn. This has led to an increase in current consumption or power consumption accompanying an increase in the size of the gate driver and charging / discharging of the parasitic capacitances CC1 to CCn.

  Hereinafter, according to the eighth to thirteenth embodiments, methods for reducing current consumption during charging / discharging of the parasitic capacitances CC1 to CCn parasitic to the gate lines G1 to Gn will be described in detail.

Eighth Embodiment FIG. 11 is a block diagram showing a configuration of a liquid crystal display device according to an eighth embodiment of the present invention. In the description of the driving method of the liquid crystal display device according to the present embodiment, the same components as those in FIG.

  In FIG. 11, reference numeral 1 denotes an LCD panel. The LCD panel 1 has a source driver (SD1 to SDm) unit 100 for driving source lines S1 to Sm, a gate line G1 to Gn, and parasitic elements parasitic on the gate lines G1 to Gn. The gate driver unit 110 drives the capacitors CC1 to CCn.

  The LCD panel 1 is composed of switch transistors TR11 to TRnm, liquid crystal electrodes CX11 to CΧnm, and a common electrode (not shown) for applying a voltage level Vcom, and each pixel is arranged in a matrix. .

  As described above, the output of the LCD panel 1, the source driver unit 100 including the source drivers SD1 to SDm for driving the source lines S1 to Sm, and the gate drivers GD1 to GDn are gated through the switches SWA1 to SWΑn and SWB1 to SWBn. The gate driver unit 110 is connected to a half potential VGD / 2 of the driver output voltage amplitude. The gate driver unit 110 consumes the gate lines G1 to Gn by shorting the VGD / 2 level at a predetermined timing. The current is reduced.

  Hereinafter, a driving method of the liquid crystal display device configured as described above will be described.

  FIG. 12 is a waveform diagram showing drive waveforms of the gate drivers GD1 to GDn of the gate driver unit 110. The gate drive circuit of the present liquid crystal display device is driven with a gate driver drive waveform shown in FIG.

  First, in FIG. 11, the source drivers SD1 to SDm charge the source lines S1 to Sm to a predetermined analog level. At this time, the gate line Gk is changed from the L level to the H level by the gate driver GDk (k = 1,..., N) and the gate line Gk-1 is changed from the H level to the L level by the gate driver GDk-1. Immediately before being driven, the switches SWAk and SWAk-1 which are components of the gate driver unit 110 are turned off, and the switches SWBk and SWBk-1 are turned on, whereby the gate lines Gk and Gk-1 are turned on. Is short-circuited to the half potential VGD / 2 of the gate driver output voltage amplitude.

  Thereafter, the switches SWAk and SWAk-1 are turned on, the switches SWBk and SWBk-1 are turned off, the gate line Gk is set to the H level by the gate driver GDk, and the gate line Gk- 1 is driven to L level. By this operation, the transistors TRk1 to TRkm are turned on, the transistors TRk-1 to TRk-1m are turned off, and the output levels of the source drivers SD1 to SDm are respectively changed to the liquid crystal capacitances CΧk1 via the source lines S1 to Sm. Charged to ~ CXkm. Since the same operation is performed for the subsequent driving of the gate lines Gk + 1 to Gn, the description is omitted.

  As described above, the driving method of the liquid crystal display device according to the eighth embodiment is the LCD panel 1, the source driver unit 100 including the source drivers SD1 to SDm for driving the source lines S1 to Sm, and the gate driver GD1. To GDn are connected to a half potential VGD / 2 of the gate driver output voltage amplitude through switches SWA1 to SWAn and SWB1 to SWBn, and gate drivers GD1 to GDn are driven before driving the gate lines. Are disconnected by switches SWΑ1 to SWAn and SWB1 to SWBn and shorted to 1/2 potential VGD / 2 of the gate driver output voltage amplitude, that is, when the gate driver output is turned on or off, the gate line is set to VGD / 2 so that it is stored in each gate line. Was charged and discharged up to VGD / 2 level near the charge, for performing the charge transfer due to a short, it is possible to gate drivers reduce current consumption than when charging the gate lines of each Η or L level.

  That is, in the conventional example, the charges accumulated in the gate lines (particularly, the charges of the parasitic capacitors CC1 to CCn) are moved by the ability of the gated driver, and then the gate lines G1 to Gn are driven. The gate driver required a larger driving capability and accompanying current consumption. On the other hand, in the present driving method, before driving the gate lines Gk and Gk-1, the gate drivers GDk and GDk-1 are separated and shorted to the VGD / 2 level, so that the charges accumulated in each gate line (particularly, , Parasitic capacitances CC1 to CCn) are reduced first, and the gate lines Gk and Gk-1 are driven after the charge is reduced, so that the gate driver only needs to have an intrinsic driving capability to reduce current consumption. It becomes possible to do. In addition, the gate driver can be reduced in size and cost.

Ninth Embodiment FIG. 13 is a block diagram showing a configuration of a liquid crystal display device according to a ninth embodiment of the present invention. In the description of the driving method of the liquid crystal display device according to this embodiment, the same components as those in FIG.

  In FIG. 13, reference numeral 1 denotes an LCD panel. The LCD panel 1 has a gate driver section 120 for driving the gate lines G1 to Gn and parasitic capacitances CC1 to CCn parasitic to the gate lines G1 to Gn, and source lines S1 to Sm. And a source driver (SD1 to SDm) unit 100 for driving.

  The LCD panel 1 includes liquid crystal pixels each composed of switch transistors TR11 to TRnm, liquid crystal electrodes CX11 to CXnm, and a common electrode (not shown) for applying a voltage level Vcom, and the pixels are arranged in a matrix. .

  The gate driver unit 120 includes gate drivers GD1 to GDn for driving the parasitic capacitances CC1 to CCn parasitic to the gate lines G1 to Gn and the gate lines G1 to Gn, and outputs of the gate drivers GD1 to GDn from the gate lines G1 to Gn. The switches SWA1 to SWΑn and SWB1 to SWBn are separated and short-circuited to the common electrode potential Vcom. These switches can be easily built in the driver by transistors such as FETs.

  As described above, the output of the LCD panel 1, the source driver unit 100 including the source drivers SD1 to SDm for driving the source lines S1 to Sm, and the gate drivers GD1 to GDn is shared via the switches SWΑ1 to SWAn and SWB1 to SWBn. The gate driver unit 120 is connected to the electrode potential Vcom. In the gate driver unit 120, the gate lines G1 to Gn and the Vcom level are short-circuited at a predetermined timing, thereby reducing current consumption.

  Hereinafter, a driving method of the liquid crystal display device configured as described above will be described.

  The gate drive circuit of the present liquid crystal display device is driven with the gate driver drive waveform shown in FIG.

  In FIG. 13, source drivers SD1 to SDm charge source lines S1 to Sm to a predetermined analog level. At this time, the gate line Gk is changed from the L level to the H level by the gate driver GDk (k = 1,..., N) and the gate line Gk-1 is changed from the H level to the L level by the gate driver GDk-1. Immediately before being driven, the switches SWAk and SWAk-1 which are components of the gate driver unit 120 are turned off, and the switches SWBk and SWBk-1 are turned on, whereby the gate lines Gk and Gk-1 are turned on. Is short-circuited to the potential Vcom of the common electrode.

  Thereafter, the switches SWAk and SWAk-1 are turned on, the switches SWBk and SWBk-1 are turned off, the gate line Gk-1 is set to the H level by the gate driver GDk, and the gate line by the gate driver GDk-1 Gk-1 is driven to L level. By this operation, the transistors TRk1 to TRkm are turned on, and the transistors TRk-1 to TRk-1m are turned off, and the output levels of the source drivers SD1 to SDm are supplied to the liquid crystal capacitors CXk1 via the source lines S1 to Sm, respectively. Charged to ~ CXkm. Since the same operation is performed for the subsequent driving of the gate lines Gk + 1 to Gn, the description is omitted.

  As described above, the driving method of the liquid crystal display device according to the ninth embodiment is the LCD panel 1, the source driver unit 100 including the source drivers SD1 to SDm for driving the source lines S1 to Sm, and the gate driver GD. A gate driver unit 120 for connecting the output of GDn to the potential Vcom of the common electrode via the switches SWA1 to SWAn and SWB1 to SWBn, and the outputs of the gate drivers GD1 to GDn before switching the gate lines It is separated by SWAn and SWB1 to SWBn and shorted to the common electrode potential Vcom, that is, the gate line is shorted to Vcom at the moment of transient when the gate driver output is turned on or off. Short charge and discharge to near Vcom level To perform the charge transfer by can gate driver to reduce the current consumption than when charging the gate lines of each H or L level.

  As described above, in this driving method, before driving the gate lines Gk and Gk-1, the gate drivers GDk and GDk-1 are separated and short-circuited to the Vcom level, so that charges accumulated in each gate line (particularly, parasitic capacitances). The charge of CC1 to CCn is first extinguished and the gate lines Gk and Gk-1 are driven after the charge is extinguished. Similarly, current consumption can be reduced.

  In this embodiment, since the potential Vcom level of the common electrode is used as a potential for disconnecting and short-circuiting the gate drivers GDk and GDk-1 before driving the gate lines Gk and Gk-1, the existing Vcom level is used. There is an advantage that it can be used as it is and is easy to implement.

Tenth Embodiment FIG. 14 is a block diagram showing a configuration of a liquid crystal display device according to a tenth embodiment of the present invention. In the description of the driving method of the liquid crystal display device according to this embodiment, the same components as those in FIG.

  In FIG. 14, reference numeral 1 denotes an LCD panel. The LCD panel 1 has a gate driver section 130 for driving the gate lines G1 to Gn and parasitic capacitances CC1 to CCn parasitic to the gate lines G1 to Gn, and source lines S1 to Sm. And a source driver (SD1 to SDm) unit 100 for driving.

  The gate driver unit 130 includes gate drivers GD1 to GDn that drive parasitic capacitances CC1 to CCn parasitic to the gate lines G1 to Gn and the respective gate lines G1 to Gn, and outputs of the gate drivers GD1 to GDn from the gate lines G1 to Gn. It is composed of switches SWC1 to SWCn and SWD1 to SWDn-1 that separate and short-circuit adjacent gate lines. These switches can be easily built in the driver by transistors such as FETs.

  As described above, the output of the LCD panel 1, the source driver unit 100 including the source drivers SD1 to SDm for driving the source lines S1 to Sm, and the gate drivers GD1 to GDn are passed through the switches SWC1 to SWCn and SWD1 to SWDn-1. The gate driver unit 130 is connected to the adjacent gate driver output. In the gate driver unit 130, the switches SWC1 to SWCn and SWD1 to SWDn-1 are turned on or off at a predetermined timing, thereby reducing current consumption. is doing.

  Hereinafter, a driving method of the liquid crystal display device configured as described above will be described.

  The gate drive circuit of the present liquid crystal display device is driven with the gate driver drive waveform shown in FIG.

  In FIG. 14, source drivers SD1 to SDm charge source lines S1 to Sm to a predetermined analog level. At this time, the gate line Gk is changed from the L level to the H level by the gate driver GDk (k = 1,..., N) and the gate line Gk-1 is changed from the H level to the L level by the gate driver GDk-1. The gates Gk and Gk-1 are short-circuited by turning off the switches SWCk and SWCk-1 which are components of the gate driver unit 130 and turning on the switch SWDk-1 immediately before being driven to become Let

  Thereafter, the switches SWCk and SWCk-1 are turned on, the switch SWDk-1 is turned off, the gate line Gk is set to the H level by the gate driver GDk, and the gate line Gk-1 is turned on by the gate driver GDk-1. Drive to L level.

  By this operation, the transistors TRk1 to TRkm are turned on, and the transistors TRk-1 to TRk-1m are turned off, and the output levels of the source drivers SD1 to SDm are supplied to the liquid crystal capacitors CXk1 via the source lines S1 to Sm, respectively. Charged to ~ CXkm. Since the same operation is performed for the subsequent driving of the gate lines Gk + 1 to Gn, the description is omitted.

  As described above, the driving method of the liquid crystal display device according to the tenth embodiment is the LCD panel 1, the source driver unit 100 including the source drivers SD1 to SDm for driving the source lines S1 to Sm, and the gate driver GD1. To GDn switch outputs 130 are connected to each other through the switches SWC1 to SWCn and SWD1 to SWDn-1, and the gate drivers GD1 to GDn are output before the gate lines are driven. Disconnected by the switches SWC1 to SWCn and SWD1 to SWDn-1 to short-circuit adjacent gate lines, that is, the gate line in which the gate driver is turned on at the moment of transient when the gate driver output is turned on or off, and the next on operation The gate line connected to the gate driver Since the short circuit is performed, the charge and discharge of the charge accumulated in each gate line to the vicinity of the intermediate potential level between the gate drive on potential and the gate drive off potential is performed by the charge transfer due to the short circuit. Current consumption can be reduced as compared with the case where the gate line is charged to the soot or L level.

  As described above, in the present driving method, the charges accumulated in the gate lines are separated by disconnecting the gate drivers GDk and GDk-1 and shorting the gate lines Gk and Gk-1 before driving the gate lines Gk and Gk-1. (In particular, the charges of the parasitic capacitances CC1 to CCn) are first reduced, and the gate lines Gk and Gk-1 are driven after the charge is reduced. Can be reduced.

  In particular, in the present embodiment, VGD / 2 as in the eighth embodiment and the potential Vcom level of the common electrode do not need to be supplied to the gate driver unit as in the ninth embodiment, which is extremely easy. Implementation is possible.

Eleventh Embodiment FIG. 15 is a block diagram showing a configuration of a liquid crystal display device according to an eleventh embodiment of the present invention. In the description of the driving method of the liquid crystal display device according to this embodiment, the same components as those in FIG.

  In FIG. 15, reference numeral 1 denotes an LCD panel. The LCD panel 1 includes a gate driver section 140 for driving the gate lines G1 to Gn and parasitic capacitances CC1 to CCn parasitic to the gate lines G1 to Gn, and source lines S1 to Sm. And a source driver (SD1 to SDm) unit 100 for driving.

  The gate driver unit 140 includes gate drivers GD1 to GDn for driving the parasitic capacitances CC1 to CCn parasitic to the gate lines G1 to Gn and the respective gate lines G1 to Gn, and outputs of the gate drivers GD1 to GDn from the gate lines G1 to Gn. The switches SWA1 to SWAn and SWB1 to SWBn are separated from each other and short-circuited to the half potential VGD / 2 of the gate driver output voltage amplitude through the resistor R1. These switches and resistors can be easily built in the driver by transistors such as FETs.

  In this way, the LCD panel 1, the source driver section 100 including the source drivers SD1 to SDm for driving the source lines S1 to Sm, the outputs of the gate drivers GD1 to GDn are connected to the switches SWΑ1 to SWAn and SWB1 to SWBn and the resistor R1. Through the gate driver 140 connected to the half potential VGD / 2 of the gate driver output voltage amplitude. In the gate driver 140, the gate lines G1 to Gn and the VGD / 2 level are set to the resistance R1 at a predetermined timing. The current consumption is reduced by short-circuiting, and the peak current during discharge is further reduced to take measures against noise.

  Hereinafter, a driving method of the liquid crystal display device configured as described above will be described.

  The gate drive circuit of the present liquid crystal display device is driven with the gate driver drive waveform shown in FIG.

  In FIG. 15, source drivers SD1 to SDm charge source lines S1 to Sm to a predetermined analog level. At this time, the gate driver GDk (k = 1,..., N) simultaneously changes the gate line Gk from the L level to the low level, and the gate driver GDk-1 changes the gate line Gk-1 from the H level to the L level. Immediately before being driven, the switches SWAk and SWAk-1 which are components of the gate driver unit 140 are turned off, and the switches SWBk and SWBk-1 are turned on, whereby the gate lines Gk and Gk-1 are turned on. Is short-circuited to the half potential VGD / 2 of the gate driver output voltage amplitude through the resistor R1.

  Thereafter, the switches SWAk and SWAk-1 are turned on, the switches SWBk and SWBk-1 are turned off, the gate line Gk is set to the H level by the gate driver GDk, and the gate line Gk- 1 is driven to L level. By this operation, the transistors TRk1 to TRkm are turned on, the transistors TRk-11 to TRk-1m are turned off, and the output levels of the source drivers SD1 to SDm are respectively changed to the liquid crystal capacitances CΧk1 via the source lines S1 to Sm. Charged to ~ CXkm. Since the same operation is performed for the subsequent driving of the gate lines Gk + 1 to Gn, the description is omitted.

  As described above, in the driving circuit and the driving method for the liquid crystal display device according to the eleventh embodiment, the outputs of the gate drivers GD1 to GDn are separated by the switches SWA1 to SWΑn and SWB1 to SWBn before the gate lines are driven. Since the voltage is short-circuited to the half potential VGD / 2 of the gate driver output voltage amplitude through the resistor R1, the charge and discharge to the vicinity of the VGD / 2 level of the charge accumulated in each gate line is caused by the short circuit. Since it is performed by charge transfer, the current consumption can be reduced as compared with the case where the gate driver charges each gate line to the H or L level, and the peak current can be further reduced to take measures against noise.

  That is, when the gate lines G1 to Gn are short-circuited with the potential level Vcom of the common electrode, if the movement of charges is too fast, the level of the gate line is caused by the parasitic capacitance between the lines at the intersection of the source line and the gate line. It will be affected and cause malfunction. This phenomenon is likely to occur in a switch transistor far from the gate driver. In order to avoid this situation, in the present embodiment, the charge movement is controlled through the resistor R1, thereby controlling the charge movement and suppressing the peak current. Therefore, in addition to the effect of the eighth embodiment, it is possible to reduce the peak current and prevent malfunction due to noise.

Twelfth Embodiment FIG. 16 is a block diagram showing a configuration of a liquid crystal display device according to a twelfth embodiment of the present invention. In the description of the driving method of the liquid crystal display device according to this embodiment, the same components as those in FIG.

  In FIG. 16, reference numeral 1 denotes an LCD panel. The LCD panel 1 has a gate driver section 150 for driving the gate lines G1 to Gn and parasitic capacitances CC1 to CCn parasitic to the gate lines G1 to Gn, and source lines S1 to Sm. And a source driver (SD1 to SDm) unit 100 for driving.

  The gate driver unit 150 includes gate drivers GD1 to GDn that drive parasitic capacitances CC1 to CCn parasitic to the gate lines G1 to Gn and the respective gate lines G1 to Gn, and outputs of the gate drivers GD1 to GDn from the gate lines G1 to Gn. The switches SW か ら 1 to SWΑn and SWB1 to SWBn are separated and short-circuited to the potential Vcom of the common electrode via the resistor R1. These switches and resistors can be easily built in the driver by transistors such as FETs.

  In this way, the LCD panel 1, the source driver unit 100 including the source drivers SD1 to SDm for driving the source lines S1 to Sm, the outputs of the gate drivers GD1 to GDn are connected to the switches SWΑ1 to SWΑn and SWB1 to SWBn and the resistor R1. The gate driver unit 150 is connected to the potential Vcom of the common electrode through the gate driver unit 150. In the gate driver unit 150, the gate lines G1 to Gn and the Vcom level are short-circuited through the resistor R1 at a predetermined timing. , And further reduce noise by reducing the peak current during discharge.

  Hereinafter, a driving method of the liquid crystal display device configured as described above will be described.

  The gate drive circuit of the present liquid crystal display device is driven with the gate driver drive waveform shown in FIG.

  In FIG. 16, source drivers SD1 to SDm charge source lines S1 to Sm to a predetermined analog level. At this time, the gate line Gk is changed from the L level to the H level by the gate driver GDk (k = 1,..., N) and the gate line Gk is changed from the H level to the L level by the gate driver GDk-1. Immediately before being driven, the switches SWAk and SWAk-1 which are constituent elements of the gate driver unit 150 are turned off, and the switches SWBk and SWBk-1 are turned on to thereby make the gate lines Gk and Gk-1 resistive. Shorted to the potential Vcom of the common electrode via R1.

  Thereafter, the switches SWAk and SWAk-1 are turned on, the switches SWBk and SWBk-1 are turned off, the gate line Gk is set to the H level by the gate driver GDk, and the gate line Gk- 1 is driven to L level.

  By this operation, the transistors TRk1 to TRkm are turned on, the transistors TRk-1 to TRk-1m are turned off, and the output levels of the source drivers SD1 to SDm are respectively changed to the liquid crystal capacitances CΧk1 to S1 to Sm through the source lines S1 to Sm. Charged to CXkm. Since the same operation is performed for the subsequent driving of the gate lines Gk + 1 to Gn, the description is omitted.

  As described above, in the liquid crystal display device driving circuit and the driving method thereof according to the twelfth embodiment, the outputs of the gate drivers GD1 to GDn are separated by the switches SWA1 to SWΑn and SWB1 to SWBn before the gate lines are driven. Since the voltage Vcom of the common electrode is short-circuited through the resistor R1, the charge accumulated in each gate line is charged and discharged to the vicinity of the Vcom level by the charge transfer due to the short circuit. Current consumption can be reduced as compared with the case where the gate line is charged to the H or L level, and the peak current can be reduced for the same reason as in the case of the eleventh embodiment described above, and noise countermeasures are taken. be able to.

  Therefore, in addition to the effects of the ninth embodiment, it is possible to further reduce the peak current and prevent malfunction due to noise.

Thirteenth Embodiment FIG. 17 is a block diagram showing a configuration of a liquid crystal display device according to a thirteenth embodiment of the present invention. In the description of the driving method of the liquid crystal display device according to this embodiment, the same components as those in FIG.

  In FIG. 17, reference numeral 1 denotes an LCD panel. The LCD panel 1 includes a gate driver unit 160 for driving the gate lines G1 to Gn and parasitic capacitances CC1 to CCn parasitic to the gate lines G1 to Gn, and source lines S1 to Sm. And a source driver (SD1 to SDm) unit 100 for driving.

  The gate driver unit 160 includes gate drivers GD1 to GDn that drive parasitic capacitances CC1 to CCn parasitic to the gate lines G1 to Gn and the gate lines G1 to Gn, and outputs of the gate drivers GD1 to GDn from the gate lines G1 to Gn. The switches SWC1 to SWCn and SWD1 to SWDn-1 are separated from each other and short-circuited between the adjacent gate lines via the resistor R2. These switches and resistors can be easily built in the driver by transistors such as FETs.

  In this way, the LCD panel 1, the source driver unit 100 including the source drivers SD1 to SDm for driving the source lines S1 to Sm, and the outputs of the gate drivers GD1 to GDn are connected to the switches SWC1 to SWCn and SWD1 to SWDn-1. The gate driver unit 160 is formed by connecting adjacent gate lines via R2. In the gate driver unit 160, adjacent gate lines are short-circuited via a resistor R2 at a predetermined timing, thereby reducing current consumption. Reduce the peak current during discharge and take measures against noise.

  Hereinafter, a driving method of the liquid crystal display device configured as described above will be described.

  The gate drive circuit of the present liquid crystal display device is driven with the gate driver drive waveform shown in FIG.

  In FIG. 17, source drivers SD1 to SDm charge source lines S1 to Sm to a predetermined analog level. At this time, the gate line Gk is changed from L level to H level by the gate driver GDk (k = 1,..., N) and the gate line Gk-1 is changed from low level to L level by the gate driver GDk-1. Immediately before being driven, the switches SWCk and SWCk-1 which are constituent elements of the gate driver unit 160 are turned off, and the switch SWDk-1 is turned on, thereby causing the gate lines Gk and Gk-1 to become resistors. Short through R2.

  Thereafter, the switches SWCk and SWCk-1 are turned on, the switch SWDk is turned off, the gate line Gk is set to the H level by the gate driver GDk, and the gate line Gk-1 is set to the L level by the gate driver GDk-1. Drive to become.

  By this operation, the transistors TRk1 to TRkm are turned on, the transistors TRk-11 to TRk-1m are turned off, and the output levels of the source drivers SD1 to SDm are respectively set to the liquid crystal capacitors CXk1 via the source lines S1 to Sm. Charged to ~ CXkm. Since the same operation is performed for the subsequent driving of the gate lines Gk + 1 to Gn, the description is omitted.

  As described above, the driving circuit and the driving method for the liquid crystal display device according to the thirteenth embodiment include the LCD panel 1 and the source driver unit 100 including the source drivers SD1 to SDm for driving the source lines S1 to Sm. The gate drivers GD1 to GDn are provided with a gate driver unit 160 in which adjacent gate lines are connected to each other via switches RWC1 to SWCn and SWD1 to SWDn-1 via a resistor R2, and the gate drivers GD1 to GD1 The output of GDn is cut off by switches SWC1 to SWCn and SWD1 to SWDn-1, and the adjacent gate lines are short-circuited via the resistor R2, so that the gate drive of the charge accumulated in each gate line is turned on. Charging / discharging up to the middle potential level between the potential and gate drive off potential due to short circuit To perform the load movement, it can also reduce current consumption than if the gate driver charges the gate lines of each H or L level, it is possible to perform noise suppression by reducing the peak current.

  Therefore, in addition to the effect of the tenth embodiment, it is possible to further reduce the peak current and prevent malfunction due to noise.

  If the driving circuit and the driving method of the liquid crystal display device having such excellent features are applied to drivers of various liquid crystal display panels, the liquid crystal display device using the liquid crystal display device has lower current consumption and higher quality. Display can be performed.

  The liquid crystal display device driving circuit and the driving method thereof according to each of the above embodiments can be applied to, for example, a liquid crystal television, but the present invention is not limited to this, and the liquid crystal display unit arranged in a matrix is driven. Of course, the device may be used for other devices, for example, a liquid crystal display device such as a liquid crystal projector.

  In the above embodiments, the waveforms of FIGS. 2, 3, 9, 10, and 12 are shown as examples of driving. However, the driving waveform may be any waveform and driving method. Needless to say.

  Furthermore, it goes without saying that the types and number of switching elements, resistors, driver circuits, etc. constituting the liquid crystal display device are not limited to the above-described embodiments. For example, a TFT liquid crystal panel is used as the active matrix panel, but it may be applied to a thin film diode. Moreover, although the TFT element is used as the switching element, it can also be applied to nonlinear elements such as MIM and diode.

It is a block diagram which shows the structure of the drive circuit of the liquid crystal display device which concerns on 1st Embodiment to which this invention is applied, and its drive method. It is a wave form diagram which shows the drive waveform of the drive circuit of the said liquid crystal display device, and the gate driver part of the drive method. It is a wave form diagram which shows the drive waveform of source driver SD1-SDm of the drive circuit of the said liquid crystal display device, and the source driver part of the drive method. It is a block diagram which shows the structure of the drive circuit of the liquid crystal display device which concerns on 2nd Embodiment to which this invention is applied, and its drive method. It is a block diagram which shows the structure of the drive circuit of the liquid crystal display device which concerns on 3rd Embodiment to which this invention is applied, and its drive method. It is a block diagram which shows the structure of the drive circuit of the liquid crystal display device which concerns on 4th Embodiment to which this invention is applied, and its drive method. It is a block diagram which shows the structure of the drive circuit of the liquid crystal display device which concerns on 5th Embodiment to which this invention is applied, and its drive method. It is a block diagram which shows the structure of the drive circuit of the liquid crystal display device which concerns on 6th Embodiment to which this invention is applied, and its drive method. It is a wave form diagram which shows the drive waveform of the gate driver part of the drive circuit of the liquid crystal display device which concerns on 7th Embodiment to which this invention is applied, and its drive method. It is a wave form diagram which shows the drive waveform of source driver SD1-SDm of the drive circuit of the said liquid crystal display device, and the source driver part of the drive method. It is a block diagram which shows the structure of the drive circuit of the liquid crystal display device which concerns on 8th Embodiment to which this invention is applied, and its drive method. It is a wave form diagram which shows the drive waveform of the drive circuit of the said liquid crystal display device, and the gate driver part of the drive method. It is a block diagram which shows the structure of the drive circuit of the liquid crystal display device which concerns on 9th Embodiment to which this invention is applied, and its drive method. It is a block diagram which shows the structure of the drive circuit of the liquid crystal display device which concerns on 10th Embodiment to which this invention is applied, and its drive method. It is a block diagram which shows the structure of the drive circuit of the liquid crystal display device which concerns on 11th Embodiment to which this invention is applied, and its drive method. It is a block diagram which shows the structure of the drive circuit of the liquid crystal display device which concerns on 12th Embodiment to which this invention is applied, and its drive method. It is a block diagram which shows the structure of the drive circuit of the liquid crystal display device which concerns on 13th Embodiment to which this invention is applied, and its drive method. It is a block diagram which shows the structure of the conventional liquid crystal display device. It is a block diagram which shows the structure of the conventional liquid crystal display device. It is a wave form diagram which shows the drive waveform of the gate driver part of the conventional liquid crystal display device. It is a wave form diagram which shows the drive waveform of source driver SD1-SDm of the source driver part of the conventional liquid crystal display device.

Explanation of symbols

1 LCD panel, 10, 110, 120, 130, 140, 150, 160 Gate driver part, 20, 30, 40, 50, 60, 70, 100 Source driver part, G1 to Gn gate line, S1 to Sm source line, CC1 to CCm, CC1 to CCn parasitic capacitance, SD1 to SDm source driver, SWA1 to SWAm, SWB1 to SWBm, SWC1 to SWCm, SWD1 to SWDm, SWA1 to SWAn, SWB1 to SWBn, SWC1 to SWCn, SWD1 to SWDn switch, Vcom Common electrode potential, VSD / 2 source driver output 1/2 potential, VGD / 2 gate driver output 1/2 potential, R1, R2 resistance

Claims (5)

A source driver for applying a voltage to the source line;
A first switch for electrically connecting the source line and the source driver in a first period;
An electrode to which a predetermined potential is applied;
A source line driver circuit comprising: a second switch that electrically connects the source line and the electrode in a second period different from the first period.   2. The source line driving circuit according to claim 1, wherein the first and second switches are constituted by transistors.   The source line driving circuit according to claim 1, wherein a resistor is provided between the electrode and the second switch.   The source line driving circuit according to claim 3, wherein the resistor includes a transistor.   2. The source line driving circuit according to claim 1, wherein the predetermined voltage is the same as a half potential of the output potential of the source driver.

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