JP2006059957A - Structure of semiconductor package and method of manufacturing semiconductor package - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure of semiconductor package along with its manufacturing method, which is excellent in productivity for further reduction in thickness and miniaturization of a product with higher functions. <P>SOLUTION: A first resin layer 9 in which a conductor layer is laminated to provide adhesive characteristics, and thermoplasticity is heated. A protruded bump 3 formed at the terminal of a semiconductor device 2 is embedded in the first resin layer 9. The conductor layer is jointed to the bump 3, and the conductor layer is pattered to form a first circuit conductor 10a. Jointing particles 11 having conductivity are arranged at a prescribed position of the first circuit conductor 10a corresponding to the bump 3, and the first circuit conductor 10a is jointed to the jointing particles 11. A second resin layer 12 having adhesion characteristics and thermoplasticity in which another conductor layer is laminated is heated. The jointing particles 11 are embedded in the second resin layer 12, and another conductor layer of the second resin layer 12 is jointed to the jointing particles 11. Another conductor layer of the second resin layer 12 is pattered to form a second circuit conductor 10b. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a structure of a semiconductor package and a method for manufacturing the semiconductor package. In particular, the present invention relates to a rearrangement of a plurality of semiconductor chip electrode portions and a package in a wafer state called CSP (Chip Scale Package). The present invention relates to a wafer level semiconductor package structure and a semiconductor package manufacturing method.

  As electronic devices become smaller, thinner, and more advanced, the space or area within the device that is allowed for mounting is becoming smaller, and the conventional two-dimensional high-density mounting technology supports it. Is becoming difficult. For this reason, various methods for increasing the number of wiring layers or miniaturizing wiring circuits have been proposed for the purpose of increasing the wiring density (see, for example, Patent Document 1).

  Here, FIG. 9 shows an example of a substrate forming method that enables multi-layered and high-density mounting, and the outline thereof will be described. FIG. 9 is a cross-sectional view showing the structure of a conventional multilayer substrate. In FIG. 9, a bonding particle 103 made of a conductor such as metal is disposed on a first circuit pattern 102 of a conductive paste formed on a resin film 101, and a heat-softening first resin layer 104 is formed so as to cover it. The surface of one end surface of the bonding particle 103 penetrates and exposes the heat-softening resin layer, and the surface of the heat-softening first resin layer 104 where one end of the bonding particle 103 is exposed. By repeating a series of steps in which the second circuit pattern 106 is formed again with a conductive paste on the top, the circuit board is formed in multiple layers.

  Also, as a new mounting form to further increase the mounting density, a component-embedded board that attracts attention by securing a new mounting area and space by embedding components in the board and attracting attention has been attracting attention. Yes. For example, a circuit board is provided with a resin insulating substrate portion and a wiring pattern portion formed on the resin insulating substrate portion, and the wiring pattern portion corresponds to an electrode pad of a built-in component. Then, bumps are formed, and a circuit board is laminated on the built-in component and thermocompression bonded, thereby electrically connecting the bump and the electrode pad formed of the conductor, and bonding between the built-in component and the circuit board. The structure which performs is proposed (for example, refer patent document 2).

  Furthermore, in addition to electronic components assembled from passive elements, semiconductor devices such as ICs and LSIs are used as built-in components. However, semiconductor devices are increasingly integrated, highly functional, and miniaturized. In many cases, the substrate is built in a multilayered substrate. Conventionally, a semiconductor device is assembled by performing die and wire bonding, resin sealing, etc. on a pellet unit obtained by cutting and separating a semiconductor element from a wafer into chips, and electrically connecting a terminal portion of the semiconductor element and a lead frame. In general, the wire bonding method is used, but in recent years, the use of flip chip connection using bumps, which are protruding terminal portions of the chip, is superior in terms of high-speed signal processing compared to the wire bonding method. There are also many things.

  For flip chip connection, recently, a bare chip mounting method in which an unpackaged chip is mounted on a printed circuit board as it is, or after performing wiring, external terminal portion formation, resin sealing, bump formation at the wafer level, A manufacturing method in which a CSP is formed by cutting and separating into semiconductor devices has been proposed (see, for example, Patent Document 3).

Here, an example of CSP type flip chip connection will be briefly described with reference to FIG. FIG. 10 is a cross-sectional view showing the structure of a CSP type semiconductor device. In FIG. 10, individual CSP type semiconductor devices 200 obtained by cutting and separating chips from a wafer are laminated on an insulating adhesive layer 290 provided on the surface of the semiconductor chip 210 on the terminal portion forming side. Thus, the wiring (portion) 240 is formed on the provided insulating layer 220. The wiring 240 formed on the insulating layer 220 and the terminal 215 of the semiconductor chip 210 are connected via an insulating adhesive layer 290 provided on the terminal 215 of the semiconductor chip 210 and a via portion 270 penetrating the insulating layer 220. Electrically connected. Further, the external terminal formation region of the wiring 240 is opened, the wiring 240 and the via portion 270 are covered with the solder resist 250, and the bumps 260 are two-dimensionally arranged as external terminals in the external terminal formation region of the wiring 240. The via part 270 is joined to substantially one surface along the wiring 240 to form one via part, and the CSP type semiconductor device 200 is configured.
Japanese Patent No. 3414653 (5th page, Fig. 1) Japanese Patent Laid-Open No. 2001-53413 (pages 6-8, FIG. 5) Japanese Patent Laid-Open No. 2002-231855 (5th page, FIG. 3)

  However, in the above-described conventional electronic component mounting structure, metal particles are arranged on a conductive circuit pattern formed on a resin film, embedded in a heat-softening resin layer, and further bonded with exposed metal particles. Although the proposed example of forming a conductive circuit pattern on the surface of a layer can certainly form a multilayer substrate by a relatively simple process of printing a conductive paste, disposing metal particles, and hot pressing. Development of a specific method essential for mass production, such as a method of arranging metal particles at an accurate position and a method of reliably connecting the metal particles and the conductive circuit pattern, remains as a problem. Furthermore, development of a method for applying this mounting structure to a semiconductor package has been awaited.

  On the other hand, in the example of a component-embedded board that enables a three-dimensional mounting by securing a new mounting area and space by embedding the component in the board, which is shown as a new mounting form for further increasing the mounting density. Form bumps and conductors by forming bumps corresponding to the electrode pads of the built-in parts on the wiring pattern part formed on the resin insulating substrate, and laminating the circuit board on the built-in parts and thermocompression bonding. However, due to the thermal history of the thermocompression bonding process or the like, thermal distortion occurs in the terminal portions of the electrode pads, bumps, and the like, leaving problems in connection and bonding.

  Also, in the CSP type flip chip connection of the semiconductor device, it is necessary to position and bond the semiconductor device chip and the circuit board individually, and there is a limit to the individual processing dimensions and assembly accuracy, Not only may there be problems with higher functionality, miniaturization, and miniaturization that will require further improvements in the future, but vias and bumps will be used to connect the wiring section and terminal section. Problems remain in connection and bonding reliability.

  The present invention has been made to solve the above-described problems. By using the semiconductor package structure of the present invention for multi-layer mounting, the mounting density of electronic components is improved and through holes are used. The reliability of connection and bonding between terminal parts such as bumps and leads of electronic components and circuit conductors on the board is extremely high, and quality improvement can be easily realized. High inter-layer connection and stacking can be used, the degree of freedom in device configuration and structural design is high, unitization of highly functional electronic parts is easy, productivity is high, and the product is further reduced in thickness and size. An object of the present invention is to provide a semiconductor device package structure and a semiconductor package manufacturing method capable of increasing functionality.

  In order to solve the above problems, a structure of a semiconductor package of the present invention includes a semiconductor element, a first resin layer, conductive bonding particles, and a second resin layer, and the semiconductor element has a terminal portion. The first resin layer has adhesiveness and thermoplasticity, a conductor layer is laminated on one surface, and the second resin layer has adhesiveness and thermoplasticity. Then, another conductor layer is laminated on one surface, bumps are embedded in the first resin layer softened by heating, the first circuit conductor is formed by bonding the conductor layer and patterning the conductor layer. The bonding particles are arranged and bonded at predetermined positions, and the bonding particles are embedded in the second resin layer softened by heating and bonded to another conductor layer, and the second conductor layer is patterned to form the second resin layer. Circuit conductor is formed, and the bump and the second circuit conductor are connected to form a multilayer structure. To have. The semiconductor device includes a semiconductor element, a first resin layer, conductive bonding particles, and a second resin layer, and the semiconductor element has a protruding bump formed on the terminal portion, The resin layer has adhesiveness and thermoplasticity, the second resin layer has adhesiveness and thermoplasticity, a conductor layer is laminated on one side, and the tip of the bump is completely embedded so that the thickness exceeds the tip. The first resin layer is laminated and a via is formed by exposing the tip of the bump at a position corresponding to the bump on the first resin layer, and the via is filled with a conductive resin so as to join the bump. The first circuit conductor is formed of a conductive resin on the surface of the first resin layer, the bumps and the first circuit conductor are connected, and the bonding particles are arranged and bonded at predetermined positions of the first circuit conductor. The bonding particles are embedded in the second resin layer softened by heating and bonded to the conductor layer, One, the second circuit conductor is formed by patterning the conductive layer may have a multi-layered structure by connecting the bumps and the second circuit conductor. The semiconductor device includes a semiconductor element, a first resin layer, conductive bonding particles, and a second resin layer, and the semiconductor element has a protruding bump formed on the terminal portion, The resin layer has adhesiveness and thermoplasticity, and the second resin layer has adhesiveness and thermoplasticity, and a conductor layer is laminated on one side, and the tip of the bump is exposed or the tip of the bump is A first resin layer is formed by being laminated so as to protrude, and a first circuit conductor is formed of a conductive resin on a surface of the first resin layer, and a bump exposed on the surface of the first resin layer; The first circuit conductor is connected, the bonding particles are arranged and bonded at predetermined positions of the first circuit conductor, the bonding particles are embedded in the second resin layer heated and softened, and bonded to the conductor layer. And patterning the conductor layer to form a second circuit conductor, and the bump and the second circuit conductor It may have a multi-layered structure are connected. Further, a second resin having adhesiveness and thermoplasticity in which conductive particles are disposed at predetermined positions of the first circuit conductor, the first circuit conductor and the bonding particles are bonded, and the conductor layers are laminated. The layer is heated, the bonding particles are embedded in the second resin layer, the conductor layer of the second resin layer and the bonding particles are bonded, and the conductor layer of the second resin layer is patterned to form the second circuit In addition to the structure in which the conductor is repeatedly formed to be multilayered, the entire semiconductor element is embedded in a first resin layer having a larger area than the semiconductor element, and the second resin layer is the same as the first resin layer You may have the structure made into the magnitude | size.

  With these configurations, the electronic circuit is formed in a stacking manner with a plurality of heat-softening and adhesive resin layers in which conductive metal is laminated on a semiconductor element. In addition, high density and high functionality can be implemented simultaneously by increasing the number of layers and increasing the density. In addition, since the semiconductor element is integrated with the resin layer and the circuit conductor, the circuit formation surface of the semiconductor element can be protected and the mechanical strength can be secured, so that the reliability and productivity of the package structure of the semiconductor device can be improved. Can be achieved.

  Further, the structure of the semiconductor package of the present invention includes a semiconductor element, a first resin layer, and a second resin layer, and the semiconductor element has a protruding bump formed in the terminal portion, The resin layer and the second resin layer have adhesiveness and thermoplasticity, and the bumps on the first resin layer are formed by laminating the first resin layer so that the tip of the bump is completely embedded and exceeds the tip. The first via is formed by exposing the tip of the bump at a corresponding position, and the first via is filled with a conductive resin so as to be joined to the bump, and the surface of the first resin layer is filled with the conductive resin. A first circuit conductor is formed, the bump and the first circuit conductor are connected, a second resin layer is formed on the first resin layer with a predetermined thickness, and the surface of the second resin layer A second via reaching the first circuit conductor is formed at a predetermined position on the first via and connected to the first circuit conductor In this way, the second via is filled with the conductive resin, and the second circuit conductor is formed on the second resin layer with the conductive resin, and the bump and the second circuit conductor are connected to form a multilayer. It has a configuration. The semiconductor device includes a semiconductor element, a first resin layer, conductive bonding particles, and a second resin layer, and the semiconductor element has a protruding bump formed on the terminal portion, The resin layer has adhesiveness and thermoplasticity, and the second resin layer has adhesiveness and thermoplasticity, and a conductor layer is laminated on one side, and the tip of the bump is exposed or the tip of the bump is A first resin layer is formed by being laminated so as to protrude, and a first circuit conductor is formed of a conductive resin on a surface of the first resin layer, and a bump exposed on the surface of the first resin layer; A first circuit conductor is connected, a second resin layer is formed with a predetermined thickness on the first resin layer, and the first circuit conductor is formed at a predetermined position on the surface of the second resin layer. Is formed, and the via is filled with a conductive resin so as to connect to the first circuit conductor, and the second resin layer is formed. To the second circuit conductor by a conductive resin is formed, it may have a multi-layered structure by connecting the bumps and the second circuit conductor.

  With these configurations, circuit conductors can be formed by exposing the bump ends, covering the entire resin surface with a metal film using a dry plating method or a wet plating method, and then etching, in addition to using a conductive resin. Various methods can be used, such as forming them, and there are many options for production process formation, and an optimum method can be selected and used. Moreover, the material of the resin layer to be used can be obtained over a wide selection range, and it is possible to select a material that is advantageous for cost reduction suitable for performance and function. In addition, by reducing the formation range of the recesses provided in the resin on the bumps and forming a partition wall between adjacent recesses, it is possible to advantageously prevent short circuits between circuit conductors in a fine circuit, and to improve productivity and quality. It becomes easy to improve.

  In addition, the structure of the semiconductor package of the present invention is such that the semiconductor element is in the form of a chip consisting of a piece or a diced wafer, and at least one semiconductor element is disposed on a resin base film having adhesiveness. It is also possible to have a configuration in which a plurality of semiconductor elements having different thicknesses are installed on a base film.

  With these configurations, the semiconductor element is integrated with the resin or the circuit conductor, and the circuit formation surface of the semiconductor element can be protected and the mechanical strength can be secured. Therefore, the reliability and productivity of the semiconductor device package can be improved. Improvements can be made.

  In order to solve the above-described problems, a method for manufacturing a semiconductor package according to the present invention includes a surface side on which a protruding bump is formed on a terminal portion of a semiconductor element, a side of a first resin layer on which a conductor layer is laminated, The first resin layer, the step of placing the conductor layer and the bump, and the step of embedding the bump in the first resin layer, bonding the conductor layer and the bump, and the first resin layer. Forming a first circuit conductor by patterning the conductor layer, and disposing a bonding particle having conductivity at a predetermined position of the first circuit conductor to bond the first circuit conductor and the bonding particle. And a step of arranging and installing the second resin layer on which the other conductor layer is laminated on the upper side where the bonding particles are installed, and the second resin layer is heated and softened and pressurized, The bonding particles are buried in the resin layer 2 and another conductor layer and the bonding particles are bonded. And that step, and a step of forming another second circuit conductors by patterning the conductive layer of the second resin layer. And a step of forming a first resin layer on the surface of the semiconductor element on which the bump-like bumps are formed so that the tip of the bump is completely embedded to a thickness exceeding the tip, and the first resin Forming a first via in which a tip of the bump is exposed by drilling at a predetermined position corresponding to the bump on the surface of the layer, and filling the first via with a conductive resin and bonding the bump to the bump; Forming a first circuit conductor with a conductive resin on the surface of the first resin layer and connecting the bump and the first circuit conductor; and a first resin on which the first circuit conductor is formed Forming a second resin layer with a predetermined thickness on the layer, and forming a second via reaching the first circuit conductor by drilling at a predetermined position on the surface of the second resin layer Filling the second via with a conductive resin and bonding the first circuit conductor to the process And extent, by the conductive resin to the surface of the second resin layer to form a second circuit conductor may comprise a step of connecting the bumps and the second circuit conductor. Further, a step of filling the first via with a conductive resin and bonding the bump to the bump, and forming a first circuit conductor with a conductive resin on the surface of the first resin layer, the bump and the first circuit conductor Or a step of filling the second via with a conductive resin and bonding it to the first circuit conductor, and a second resin layer on the surface of the second resin layer by the conductive resin. The step of forming the circuit conductor and connecting the bump and the second circuit conductor may be performed simultaneously.

  By these methods, the semiconductor element is integrated with the resin layer and the circuit conductor, the circuit forming surface of the semiconductor element can be protected and the mechanical strength can be secured, the resin of the resin substrate has adhesiveness, By embedding the entire semiconductor element in the resin, the semiconductor element is integrated with the resin substrate and the circuit conductor, so that the circuit forming surface of the semiconductor element can be protected and the mechanical strength can be secured. As well as improving the reliability, productivity can be improved. In addition to using a conductive resin, the circuit conductor can be formed by various methods such as exposing the bump end, then covering the entire resin surface with a metal film by a dry plating method or a wet plating method, and etching. The most suitable method can be selected from these methods. There are many choices in the manufacturing process, such as not only the circuit conductor material but also the resin material that can be selected according to the forming method, and the optimal material and process that are suitable for performance and function, and that are advantageous for cost reduction. This makes it possible to easily improve productivity, improve quality, reduce costs, and the like.

  The structure of the semiconductor package of the present invention can be a multilayer circuit by forming a circuit conductor connected to a semiconductor element on the semiconductor element, and further laminating the circuit conductor via a resin.

  In addition, the semiconductor element can be formed as a small and fine semiconductor package by fixing and integrating a plurality of semiconductor elements on a base film. Furthermore, since the semiconductor element is joined and integrated with the resin, the strength is increased, damage during handling is reduced, and quality and productivity can be easily improved.

  Embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
Hereinafter, the structure of the semiconductor package and the manufacturing method thereof according to the first embodiment of the present invention will be described with reference to FIGS. 1, 2, and 3. FIG. FIG. 1 is a cross-sectional view showing the structure of a semiconductor package according to the first embodiment of the present invention, FIG. 2 is a cross-sectional view showing another structure of the semiconductor package according to the first embodiment of the present invention, and FIG. 12 is a flowchart illustrating an example of a process for manufacturing a semiconductor package according to Form 1.

  In FIG. 1, a semiconductor package 41 has a bump 3 formed on a circuit forming surface of a semiconductor element (hereinafter also referred to as a semiconductor device) 2, and a first resin layer 9 having adhesiveness and heat softening properties. And a first resin of a first electric conductor metal-attached resin layer (hereinafter also referred to as a conductor metal-attached resin layer) 13 formed of an electric conductor metal (not shown, hereinafter also referred to as a conductor metal) serving as a conductor layer. The bump 3 is embedded in the layer 9, and the first circuit conductor 10a formed by patterning the conductive metal and the bump 3 are joined so as to ensure electrical conduction. The first circuit conductor 10a is patterned by removing an unnecessary portion of the conductor metal that becomes the conductor layer by an etching method or a processing method using a laser or the like.

  On the first circuit conductor 10a, the bonding particles 11 are placed and mounted at predetermined positions. The bonding particles 11 are made of any metal simple substance of gold, silver, copper, tin, palladium, nickel, platinum and aluminum, an alloy mainly composed of any of these metals, or resin particles, and these metals, It is formed by resin plating with an alloy.

  The bonding particles 11 are formed from a first circuit conductor 10 a formed on the surface of the first resin layer 9 and a conductor metal (not shown) which is another conductor layer from the second resin layer 12. The second circuit conductor 10b formed by patterning the conductor metal of the second resin layer 18 with a metal conductor has a function of electrically connecting up and down with the second resin layer 12 in between. Yes. The second resin layer 12 is preferably made of the same material as that of the first resin layer 9, but can be used after examination even if it is made of a different material if the characteristics are approximate.

  The attached bonding particle 11 is embedded in the second resin layer 12 and is connected to the second circuit conductor 10b formed on the second resin layer 12, and is also electrically connected to the semiconductor element 2. Thus, the semiconductor package 41 is configured. By using the first resin layer 9 and the first circuit conductor 10a, the second resin layer 12 and the second circuit conductor 10b, and the bonding particles 11, the multilayer circuit is repeatedly formed to form a multilayer circuit having a large number of layers. It becomes possible to do. Moreover, it is also possible to attach an electronic component 53 separately to the second circuit conductor 10b formed on the surface of the second resin layer 12.

  Note that the structure of the semiconductor package according to the first embodiment of the present invention described above is not limited to the structure shown in FIG. Other semiconductor package structures as shown in FIG. 2 are possible.

  For example, as in the semiconductor package 43 shown in FIG. 2A, a first resin layer 9a larger than the chip size of the semiconductor element 2 is prepared, and the surface opposite to the bump 3 formation surface of the semiconductor element 2 is exposed. A structure in which the entire chip of the semiconductor element 2 is embedded in the first resin layer 9a, or an exposed surface of the semiconductor element 2 after the entire chip of the semiconductor element 2 is embedded as in the semiconductor package 44 shown in FIG. Can be covered with a third resin layer 15 having the same size as the first resin layer 9a. The third resin layer 15 is preferably made of the same material as that of the first resin layer 9, but any material having similar characteristics can be used after consideration. Which configuration is used can be arbitrarily selected according to the purpose of use of the structure of the semiconductor package.

  Further, as in the semiconductor package 45 shown in FIG. 2C, a configuration in which individual electronic components such as a resistor (resistor) and a capacitor (capacitor) are incorporated as necessary can be adopted. For example, when the resistor 16 is built in, the built-in resistor 16 can be formed by a method of printing and applying a resistance material between the first circuit conductors 10a after the first circuit conductor 10a is formed. In addition to printing resistance by such printing, formation by a method of bonding using a bonding material with film-like resistance or chip resistance is also possible. For the built-in capacitor 17, the first circuit conductor 10a on the first resin layer 9a and the second circuit conductor 10b on the second resin layer 12 are formed with a predetermined area, respectively. The two resin layers 12 can be formed to face each other. Since the capacitance of the capacitor is determined by the area of each circuit conductor to be faced and the dielectric constant of the second resin layer 12, design consideration is required in advance. In the case of a built-in capacitor, it is naturally possible to form it by a method such as bonding to a film or chip capacitor using a bonding material. FIG. 2C shows an example of a configuration in which a resistor and a capacitor are built in, but a coil (inductor) can also be built in.

  Further, as in the semiconductor package 46 shown in FIG. 2D, after the entire chip of the semiconductor element 2 is embedded in the first resin layer 9a larger than the chip size, the exposed surface of the semiconductor element 2 is covered with the first resin layer 9a. And a third circuit conductor 10c is formed on the surface of the third resin layer 15 opposite to the circuit formation surface of the semiconductor element 2, and the first resin layer 9a is formed. A semiconductor package structure in which circuit conductors are connected to each other with a semiconductor element 2 interposed between through-holes 19 penetrating the second resin layer 12 and the third resin layer 15 at the same position can be configured. . In addition, although the example which incorporates an individual electronic component was shown in FIG.2 (d), the structure which does not incorporate an electronic component is also possible.

  Next, the procedure for manufacturing the semiconductor package according to the first embodiment of the present invention will be described with reference to the flowchart of the steps illustrated in FIG. In FIG. 3, a stepwise component mounting structure composed of an electronic component, a resin layer, a through hole, a conductive resin and the like in each step is shown on the right side in a sectional view.

  First, the surface side on which the protruding bumps 3 of the semiconductor element 2 are formed and the first resin layer 9 side of the first resin layer with metal 13 are placed facing each other (step S1). The first conductive metal-attached resin layer 13 is formed by attaching a conductive metal 14 serving as a conductive layer to a first resin layer 9 having heat softness and adhesiveness, and the conductive metal 14 is generally made of copper foil. However, there is no particular limitation as long as electrical conduction is possible. Further, the bumps 3 formed on the circuit surface of the semiconductor element 2 preferably have the same height. However, after forming the bumps 3, a method of aligning the height by pressing with a flat plate, In the step S2, it is also possible to deform the bumps 3 with the applied pressure at the time of joining to the conductor metal 14 and use them with the same height. The material used for the first resin layer 9 may be a resin that is softened by heating and then completely cured through a semi-cured state, such as an epoxy resin in a thermosetting resin.

  Next, the 1st resin layer 9 is softened by heating the 1st resin layer 13 with a metal with a heating-pressing machine (not shown) at predetermined temperature. When the first resin layer 9 is softened, the bumps 3 of the semiconductor element 2 are embedded in the first resin layer 9, and the bumps 3 and the conductor metal 14 are in contact with each other until electrical conduction is ensured. Pressure (step S2). Pressurization can be performed using a known method. Moreover, since the softening temperature and the applied pressure of the first resin layer 9 vary depending on the material used for the first resin layer 9, it is desirable that the first resin layer 9 be confirmed after being experimentally confirmed. By confirming the continuity between the bump 3 and the conductor metal 14 using a measuring instrument, after ensuring electrical continuity, the first resin layer 9 is cured by cooling in a state of being pressurized in the direction of the arrow.

  Subsequently, when the curing of the first resin layer 9 is completed, the conductive metal 14 is patterned by removing unnecessary portions of the conductive metal 14 by an etching method or a processing method using a laser or the like, and the first metal layer on the semiconductor element 2 is patterned. A first circuit conductor 10a connected to the semiconductor element 2 is formed on the surface of the resin layer 9 (step S3). The first circuit conductor 10a is formed by performing patterning in the state of only the first conductor metal-attached resin layer 13 before embedding the bumps 3 in the first resin layer 9, and then forming the first circuit conductor 10a. However, when the fine first circuit conductor 10a is used, the area of the portion to be bonded to the bump 3 is small, and the position may be shifted during pressurization, resulting in poor connection. It is necessary to carry out the process after fully examining the conditions necessary for the process. In addition, after the first circuit conductor 10a is formed, when the resistor 16 is formed between the first circuit conductors 10a and incorporated as in the semiconductor package 45 shown in FIG. Is formed. The resistor 16 may be formed by a printing resistance by printing, a method of bonding using a bonding material with a film-like resistance or a chip resistance, and the like. Although not shown, even when a coil (inductor) is incorporated, the formation can be performed in step S3.

  Next, the bonding particles 11 are placed at predetermined positions on the surface of the first circuit conductor 10a and bonded (step S4). The joining method can be performed by a well-known method such as ultrasonic welding, welding, soldering, or conductive resin coating. The bonding particles 11 are made of any metal simple substance of gold, silver, copper, tin, aluminum, Ni, palladium, etc., an alloy mainly composed of any of these metals, or resin particles. In addition, a resin-plated surface using a chemical containing an alloy is used. The shape of the bonding particle 11 is generally often used as a sphere, a hemisphere, or a columnar body, but is not limited to these shapes, and can be used after being formed into an arbitrary shape.

  When the installation / joining of the joining particles 11 is finished at a predetermined position on the surface of the first circuit conductor 10a in step S4, the second conductive metal-attached resin layer 18 is disposed from the upper side where the joining particles 11 are placed (step S5). ). At this time, the surface side on which the bonding particles 11 are installed and the second resin layer 12 side of the second resin layer 18 with a conductive metal are arranged to face each other.

  Thereafter, the second conductive metal-attached resin layer 18 is heated and softened at a predetermined temperature using a heating and pressurizing machine (not shown), and then pressurized in the direction indicated by the arrow, so that the bonded particles 11 are formed. Embedded in the softened second resin layer 12, pressurization is further advanced, and the bonded particles 11 and the conductive metal 14 serving as another conductive layer are brought into contact with each other and bonded, and the formed first conductive metal-added resin The first circuit conductor 10a on the first resin layer 9 of the layer 13 and the conductor metal 14 on the second resin layer 12 of the second resin layer 18 with conductive metal are joined and integrated, and are electrically conductive. Can be secured (step S6).

  The second resin layer 12 constituting the second conductive metal-attached resin layer 18 is preferably made of the same material as that of the first resin layer 9, but if a different material has very close characteristics, Can be used. However, the second resin layer 12 has adhesiveness, and it may be a material having a low temperature curing type with a softening temperature in the range of 80 to 200 ° C. and a characteristic that the linear expansion coefficient is equal to or very close to that of the second resin layer 12. desirable.

  In step S6, the bonding particles 11 are embedded in the second resin layer 12 softened by pressurization, and bonded to the conductor metal 14 which is another conductor layer to ensure electrical conduction, and then cooled in this state. Thus, the second resin layer 12 is cured, and the conductive metal 14 on the second resin layer 18 with a conductive metal is patterned by removing unnecessary portions of the conductive metal 14 by an etching method or a processing method using a laser or the like. Then, by forming the second circuit conductor 10b (step S7), the manufacturing process of the semiconductor package 41 having the multilayer circuit is completed.

  In addition, after forming the second circuit conductor 10b, when the capacitor (capacitor) 17 is formed and incorporated as in the semiconductor package 45 shown in FIG. 2C, the first on the first resin layer 9 is formed. The internal circuit capacitor 10a and the second circuit conductor 10b on the second resin layer 12 are formed to have a predetermined area, and face each other with the second resin layer 12 in between. 17 is formed. The capacitance of the capacitor is determined by the area of each circuit conductor facing each other and the dielectric constant of the second resin layer 12. In the case of a built-in capacitor, it can be formed by a method of bonding a film or a chip capacitor using a bonding material.

  In the manufacturing process of the semiconductor package according to the first embodiment of the present invention, after step S5, multilayering is performed using the second conductive metal-attached resin layer 18 in which the conductive metal 14 is laminated on the second resin layer 12. Although the process has been described, the manufacturing process of the semiconductor package in the first embodiment of the present invention is not limited to this. For example, it replaces with the resin layer 18 with a 2nd conductor metal, and uses only the 2nd resin layer 12 with which the conductor metal is not laminated | stacked, and it is so that the joining particle 11 is exposed to the surface above the 2nd resin layer 12. Then, the second circuit conductor 10b is formed on the surface of the second resin layer 12 by using a paste-like conductive resin by printing or the like, and the bonding particles 11 and the second circuit conductor are formed. A method of joining 10b is also conceivable. The method of forming the second circuit conductor 10b can be formed by using transfer or the like in addition to the above-described coating formation by printing or the like.

  In the description of the above process, the circuit formation is performed on the circuit formation surface side of the semiconductor element 2, but the second of the circuit formation surface of the semiconductor element 2 as in the semiconductor package 46 shown in FIG. Similarly, the third resin layer 15 and the third circuit conductor 10c are formed on the surface opposite to the circuit conductor 10b, and the second circuit conductor 10b and the third circuit conductor 10c are sandwiched between the semiconductor elements 2. Are connected by the through hole 19 to form a multi-layered semiconductor package 46. In this case, it is desirable to use the same resin material as the first resin layer 9 a and the second resin layer 12 for the third resin layer 15. As the third circuit conductor 10c formed on the third resin layer 15, a third conductive metal-attached resin layer (not shown) in which conductive metals are laminated may be used, or conductive resin may be printed or transferred. May be formed. A conductive resin is filled in a through hole 19 that penetrates the first resin layer 9a, the second resin layer 12, and the third resin layer at the same position to connect the circuit conductors, thereby achieving electrical conduction. it can.

  As described above, the structure of the semiconductor package according to the first embodiment of the present invention is not only a package structure that can be processed with the same size as the chip size of the semiconductor element, but also multi-layered using a through hole, Since it is easy to increase the density and achieve high definition and high functionality at the same time, it is suitable for downsizing and high integration of devices to be used. Further, since a certain degree of thickness can be secured in the first resin layer and the second resin layer in which the bumps and the bonding particles are embedded when multilayering, the influence of distortion caused by thermal expansion or the like when receiving a thermal history Therefore, defects in the junction with the circuit conductor can be reduced, and a highly reliable semiconductor device package structure can be realized.

(Embodiment 2)
Subsequently, the structure of the semiconductor package and the manufacturing method thereof according to the second embodiment of the present invention will be described with reference to FIGS. 4 is a sectional view showing the structure of the semiconductor package according to the second embodiment of the present invention, FIG. 5 is a sectional view showing another structure of the semiconductor package according to the second embodiment of the present invention, and FIG. 12 is a flowchart illustrating an example of a process for manufacturing a semiconductor package according to Form 2. 4 to 6, the same components as those in FIGS. 1 to 3 are denoted by the same reference numerals.

  In the structure of the semiconductor package according to the first embodiment of the present invention described above, the resin layer with the conductor metal obtained by laminating the conductor metal on the first resin layer is used, and the bump formed on the terminal portion of the semiconductor element is embedded in the resin layer. The conductive bonding particles disposed on the conductive metal on the first resin layer are embedded in the second resin layer, and the circuit conductor formed on the second resin layer and the bonding particles are bonded to form a multilayer. In contrast to the structure of the semiconductor package according to the second embodiment of the present invention, only the first resin layer on which no conductor metal is laminated is used, and the first resin layer and the second resin are used. The difference is that a multilayer structure is formed by forming through holes or vias in the layers and electrically bonding them with bumps provided in the terminal portions of the semiconductor element.

  In FIG. 4, the semiconductor package 42 has bumps 3 formed on the circuit formation surface of the semiconductor element 2, and the bumps 3 are embedded in the first resin layer 9 having adhesiveness and heat softening properties. The first resin layer 9 can be formed using a coating method such as printing of a material on a paste or a method using a sheet-like material. The resin material used for forming the first resin layer 9 can be obtained with a wider selection range than the resin layer forming material obtained by laminating a conductor metal in the structure of the semiconductor package of the first embodiment of the present invention. It is possible to select a material that is advantageous for cost reduction suitable for performance and function. On the top of the bump 3 of the second resin layer 9, a recess 22 is formed as a via that exposes a part of the bump 3 by partially removing the resin layer by etching, laser processing, mechanical processing, or the like. Yes.

  The recess 22 serving as a via is filled with a conductive resin 20 and a first circuit conductor 21 a using the same conductive resin 20 is formed on the surface of the first resin layer 9. Further, by reducing the formation range of the recesses 22 serving as vias provided in the resin on the bumps 3 and forming a partition wall between the adjacent recesses 22, it is advantageous to prevent a short circuit between circuit conductors in the fine circuit. It is easy to improve productivity and quality. Further, a second resin layer 12 is formed on the first resin layer 9, and the second resin layer 12 is etched, laser-processed, or corresponding to the position of the first circuit conductor 21a. A hollow portion 23 serving as a through hole or a via is formed by mechanical processing or the like. The second resin layer 12 is preferably made of the same material as that of the first resin layer 9, but can be used after consideration even if it is made of a different material if the characteristics are approximate.

  Then, the cavity 23 corresponding to the via is filled with the conductive resin 20 and the second circuit using the same conductive resin 20 on the surface of the second resin layer 12 opposite to the semiconductor element 2. A conductor 21b is formed and connected to the bump 3 of the semiconductor element 2 to form a semiconductor package 42 having a multilayer structure. The first resin layer 9 and the first circuit conductor 21a, the second resin layer 12 and the second circuit conductor 21b, and the conductivity filled in the recess 22 and the cavity 23 corresponding to the via formed in each resin layer. A multilayer circuit having a large number of layers can be formed by repeatedly laminating with the conductive resin 20. It is also possible to attach an electronic component (not shown) separately to the second circuit conductor 10b formed on the surface of the second resin layer 12.

  Note that the structure of the semiconductor package according to the second embodiment of the present invention described above is not limited to the structure shown in FIG. Other semiconductor package structures as shown in FIG. 5 are possible.

  For example, as in a semiconductor package 47 shown in FIG. 5A, a cavity 23 serving as a via is formed in the second resin layer 12 for electrical connection between the first circuit conductor 21a and the second circuit conductor 21b. Instead of filling the conductive resin 20, a method using the bonding particles described in the structure of the semiconductor package of the first embodiment is also possible.

  5A, after forming the first circuit conductor 21a with the conductive resin 20 on the first resin layer 9, the bonding particles 11 are placed at predetermined positions of the first circuit conductor 21a. The second resin layer 12 is disposed on the surface, and the bonding particles 11 are embedded in the second resin layer 12 using a known method such as heat and pressure, and the bonding particles 11 are formed on the surface of the second resin layer 12. After exposing a part, the 2nd circuit conductor 21b is formed in the surface of the 2nd resin layer 12 using the conductive resin 20, and the joining particle 11 and the 2nd circuit conductor 21b are electrically The semiconductor package 47 having a multi-layer structure is configured to be electrically connected to each other.

  Further, as in the semiconductor package 48 shown in FIG. 5B, after the entire chip of the semiconductor element 2 is embedded in the first resin layer 9a larger than the chip size, the exposed surface of the semiconductor element 2 is made the first resin layer 9a. The third resin layer 15 is covered with a third resin layer 15 having the same size as that of the semiconductor element 2, and a third circuit conductor 21c is formed on the surface of the third resin layer 15 opposite to the circuit formation surface of the semiconductor element 2, and the first resin layer 9a is formed. A semiconductor package structure in which circuit conductors are connected to each other with a semiconductor element 2 interposed between through-holes 19 penetrating the second resin layer 12 and the third resin layer 15 at the same position can be configured. . The third resin layer 15 is preferably made of the same material as that of the first resin layer 9a, but any material having similar characteristics can be used after consideration. Which configuration is used can be arbitrarily selected according to the purpose of use of the structure of the semiconductor package. In the configuration shown in FIG. 5B, conductive bonding is used instead of filling the cavity 23 serving as a via formed in the second resin layer 12 with the conductive resin 20 as in FIG. 5A. Of course, it is possible to adopt a configuration in which particles are embedded.

  Further, FIG. 5B shows an example in which individual electronic components are incorporated, but a configuration in which electronic components are not incorporated is also possible. As a method of incorporating individual electronic components, the same method as described in the structure of the semiconductor package in the first embodiment can be used. For example, when the resistor 16 is built in, the built-in resistor 16 can be formed by a method of printing and applying a resistance material between the first circuit conductors 21a after the first circuit conductors 21a are formed. In addition to printing resistance by such printing, formation by a method of bonding a film-like resistance or a chip resistance using a bonding material is also possible. The built-in capacitor 17 includes a first circuit conductor 21a on the first resin layer 9a and a second circuit conductor 21b on the second resin layer 12 each having a predetermined area. The two resin layers 12 can be formed to face each other. Since the capacitance of the capacitor is determined by the area of each circuit conductor to be faced and the dielectric constant of the second resin layer 12, design consideration is required in advance. In the case of a built-in capacitor, it is naturally possible to form it by a method of bonding using a bonding material with a film or a chip capacitor. FIG. 5B shows an example of a configuration in which a resistor and a capacitor are built in, but a coil (inductor) can also be built in.

  In the semiconductor package according to the second embodiment of the present invention described above, the tips of the bumps 3 formed on the terminal portions of the semiconductor element 2 are completely embedded, and the first resin layer 12 is formed. The first resin layer 9 is formed so that the surface has a thickness exceeding the tip of the bump 3. In addition to such a configuration, in the semiconductor package according to the second embodiment of the present invention, is the tip of the protruding bump 3 formed on the terminal portion of the semiconductor element 2 exposed on the surface of the first resin layer 9? Alternatively, a configuration in which the first resin layer 9 is formed by being embedded so that the tip of the bump 3 protrudes is also possible. In the case of this configuration, it is not necessary to form the recess 22 serving as a via in the first resin layer 9 and fill the conductive resin 20, but the tip of the bump 3 protruding on the surface of the first resin layer 9. To be exposed on the surface of the first resin layer 9. After this, the first circuit conductor 21a is formed by the conductive resin 20 on the surface of the first resin layer 9, and the bump 3 and the first circuit conductor 21a exposed on the surface of the first resin layer 9 are formed. Will be connected. Further, the tip of the bump 3 protruding on the first resin layer 9 is pressed and compressed by being sandwiched by a pressing jig, cut by a jig such as scissors, nippers, and cutters, or a jig such as a file. It can be deleted by methods such as cutting, chemically dissolving by etching, and deleting by using a laser or torch. Moreover, since the thickness of the 1st resin layer 12 can be made thin in the semiconductor package in Embodiment 2 of this invention of this structure, the whole semiconductor package can be made thin.

  Next, the procedure for manufacturing the structure of the semiconductor package according to the second embodiment of the present invention will be described with reference to the flowchart of the steps illustrated in FIG. In FIG. 6, a stepwise semiconductor package structure including a semiconductor element, a resin layer, a conductor circuit, a cavity corresponding to a via, a bump, and the like in each step is shown on the right side in a cross-sectional view.

  First, the semiconductor element 2 having the bump 3 formed thereon is disposed on the pad on the circuit formation surface, and the first resin layer 9 is formed so as to bury the bump 3 (step S11). The bumps 3 are formed on the pads on the circuit formation surface of the semiconductor element 2 using a conductive resin. At this time, it is not particularly necessary to adjust the bumps 3 to have the same height. Moreover, the resin material used for formation of the 1st resin layer 9 will not be specifically limited if it is a resin material which has adhesiveness. The formation of the first resin layer 9 includes a method of forming a paste-like or cream-like resin material by coating, printing, or the like, or a method of forming by pasting a sheet-like resin material. Can be used. When the first resin layer 9 is formed by application, printing, or the like, since it is formed using a paste-like or cream-like resin material whose viscosity is adjusted, the material is either thermosetting or thermosoftening. Resin material may be used. However, in the case where the resin material is formed in a sheet form and pasted, it is necessary to embed the bumps 3 in the first resin layer 9 and to use a thermosoftening resin material. In consideration of the influence on the semiconductor element 2, it is desirable that the thermal softening temperature is appropriately selected and used from a low-temperature curable resin material that softens in a temperature range of about 80 to 200 ° C. Moreover, when using a sheet-like thermosetting resin as the 1st resin layer 9, if necessary, the epoxy resin which has the characteristic which will be in the semi-hardened state called the B stage hardened after once softening at the time of heat curing is needed. It can also be used. Any other resin material can be used as long as it is a resin having the same semi-cured property without being limited to the epoxy resin.

  The surface of the formed first resin layer 9 needs to be formed smoothly for the formation of the first circuit conductor 21a in a subsequent process, and a mechanical method such as polishing or grinding is used as necessary. In some cases, when the first resin layer 9 is formed using a heat softening resin material, the first resin layer 9 is softened by heating and then smoothed by pressurization using a jig having a smooth surface. Is available. In addition, in consideration of work in the subsequent process, the thickness dimension s from the bump 3 embedded in the formed first resin layer 9 to the surface of the first resin layer 9 can be determined in consideration of workability. It is desirable to set as small as possible.

  Next, a part of the resin material on the bump 3 embedded in the first resin layer 9 is removed to form a multilayer structure by connecting to the bump 3 of the semiconductor element 2 to form an electronic circuit. A recess 22 to be a via is formed, and a part of the bump 3 is exposed (step S12). The recessed portion 22 forming portion of the first resin layer 9 exposing the bump 3 may be the end surface of the bump 3 or a portion extending from the end to the side surface, but the area to be removed on the first resin layer 9 can be reduced. As a result, a higher-definition electronic circuit pattern can be formed. The selective removal of the resin material of the first resin layer 9 for forming the recess 22 that becomes the first via exposing the bump 3 is performed by a laser processing method using a YAG laser, an excimer laser or the like, or etching the resin material. It can be carried out by selecting from various options such as chemical processing method, mechanical processing method using grinding or sand blasting.

  When the exposure of part of the bump 3 embedded in the first resin layer 9 is completed in step S12, the first circuit conductor 21a electrically connected to the exposed bump 3 is formed using the conductive resin 20. (Step S13). The first circuit conductor 21a is formed by connecting the bumps 3 to the recesses 22 serving as the first vias by the step of filling the conductive resin 20 and then joining the filled conductive resin 20 with the same. A method of performing the process of forming the first circuit conductor 21a on the surface of the first resin layer 9 with the conductive resin 20 in two steps, filling the recess 22 with the conductive resin 20, and the first A method of simultaneously forming the first circuit conductor 21a on the surface of the resin layer 9 in one step is conceivable. Which method is selected is arbitrary, and is determined in consideration of characteristics such as the thickness dimension s in the first resin layer 9, the depth and diameter of the concave portion 22 serving as the first via, and the viscosity of the conductive resin 20. To do. However, when the depth of the recess 22 is shallow, a one-step method is easy, which is advantageous in reducing the number of steps.

  In the description of the above-described process, a method of filling the recess 22 serving as the first via with the conductive resin 20 and forming the first circuit conductor 21a on the first resin layer 9 with the same conductive resin 20 is used. In addition to this method, after exposing the bump 3 end, the entire resin surface is covered with a dry plating method or a metal film that can be formed by a wet plating method. Various different methods, such as a method of forming a film by patterning or a method of forming a circuit conductor only on a necessary part by masking, can be considered, but an optimal method may be selected according to the actual manufacturing process. .

  Subsequently, the second resin layer 12 is formed so as to cover the first circuit conductor 21a formed of the conductive resin 20 in Step S13 (Step S14). The resin material used to form the second resin layer 12 is preferably the same material as the resin material on which the first resin layer 9 is formed, but a resin material of a different material can also be used. When using a different material, it is desirable that the material has a very close characteristic value, and it should be used after thorough examination.

  For the formation of the second resin layer 12, the same method as the method for forming the first resin layer 9 in Step S11 can be used. Detailed description is omitted to avoid duplication.

  In step S14, after forming the second resin layer 12, at a predetermined position of the second resin layer 12 and a position where it can be connected to the first circuit conductor 21a formed on the first resin layer 9. A cavity 23 serving as a second via is formed to expose the first circuit conductor 21 a formed of the conductive resin 20 covered with the second resin layer 12. The formation of the cavity 23 is performed by removing the second resin layer 12, but the same method as the method in which the recess 22 serving as a via is formed in the first resin layer 9 in step S12 can be used. Detailed description is omitted to avoid duplication.

  In addition, when forming the 2nd resin layer 12 by the method of sticking the sheet-like resin material in Step S13, a hole is beforehand made in the predetermined part of the 2nd resin layer 12 as hollow part 23, By installing the second resin layer 12 by heating and pressurizing and bonding the second via layer, the second via layer is installed at a position corresponding to the first circuit conductor 21a formed of the conductive resin 20 on the first resin layer 9. It is also possible to form a hollow portion 23. After forming the second resin layer 12 on the first resin layer 9, when forming the cavity 23 in the second resin layer 12, the thickness of the second resin layer 12 is set as thin as possible. This facilitates the work of forming the cavity 23.

  In step S15, after the first circuit conductor 21a on the first resin layer 9 is exposed by the cavity 23 formed in the second resin layer 12, the cavity 23 serving as a through hole or a via hole is electrically conductive. The resin 20 is filled to make electrical connection with the first circuit conductor 21a, and the second circuit conductor 21b is formed on the second resin layer 12 using the same conductive resin 20 ( Step S16), the manufacturing process of the semiconductor package 42 integrated with the semiconductor element 2 and multilayered is completed. Similarly to the case of forming the first circuit conductor 21a on the first resin layer 9 in step S13, the filling of the conductive resin 20 into the cavity 23 serving as the second via also in step S16, The formation of the second circuit conductor 21b on the surface of the resin layer 12 in two steps or simultaneously in one step is optional, and the depth and diameter of the recess 22 serving as the first via, the conductive resin However, when the thickness dimension of the second resin layer 12 in the cavity 23 forming part is small, the work of one process is easy, the man-hours can be easily reduced, and the production can be reduced. This is advantageous for improving productivity and reducing manufacturing costs.

  Thereafter, by repeating the processes from step S14 to step S16, a multi-layered semiconductor package having a larger number of electronic circuit layers can be formed.

  As in the case of the semiconductor package 47 shown in FIG. 5A, the bonding particles 11 are used for electrical joining instead of filling the cavity 23 with the conductive resin 20 to obtain electrical joining and multilayering. In the case of manufacturing the structure to be taken, first, the first resin layer 9 is formed so as to expose one end of the bump 3 in step S11 in FIG. 6, and then the first resin layer is formed in step S13 shown in FIG. After the first circuit conductor 21a made of the conductive resin 20 is formed on the resin layer 9, the step of installing and bonding the bonding particles 11 at a predetermined position of the first circuit conductor 21a is performed. In the subsequent steps, one end of the bonding particle 11 is embedded so as to be exposed on the surface of the second resin layer 12, and the bonding particle 11 is electrically connected to the second resin layer 12 by the conductive resin 20. The second circuit conductor 21b is formed so as to be conductive to the semiconductor package 47, and the semiconductor package 47 having a multilayer circuit configuration can be manufactured.

  In the above description of the process, the circuit is formed on the bump 3 formation surface side of the semiconductor element 2, but the opposite side to the bump 3 formation surface of the semiconductor element 2 as in the semiconductor package 48 shown in FIG. Similarly, a third circuit conductor 21c using the third resin layer 15 and the conductive resin 20 is formed on this surface, and the second circuit conductor 21b and the third circuit conductor 21c are sandwiched between the semiconductor elements 2. Are filled with a conductive resin 20 in a through hole 19 that penetrates the first resin layer 9a, the second resin layer 12, and the third resin layer 15 at the same position to connect the circuit conductors to each other. As a result, a multi-layered semiconductor package 48 can be formed. In this case, it is desirable to use the same resin material as the first resin layer 9 a and the second resin layer 12 for the third resin layer 15.

  Further, the semiconductor package 48 shown in FIG. 5B shows a configuration in which a resistor 16 and a capacitor (capacitor) 17 are formed, but a resistor (resistor) or a coil (inductor, FIG. 5B) In step S13 in FIG. 6, after forming the first circuit conductor 21a, a paste-like resistance material can be formed between the first circuit conductors 10a by a printing method or the like to be incorporated. . A film-like resistor, a chip resistor, a method of joining a chip-like inductor with a joining material, and the like are also possible. When the capacitor 17 is formed and incorporated, the first circuit conductor 10a on the first resin layer 9a and the second circuit layer 12 on the second resin layer 12 are formed after the second circuit conductor 10b is formed. Each of the circuit conductors 10b is formed to have a predetermined area, and facing each other with the second resin layer 12 interposed therebetween, thereby forming the built-in capacitor 17. The capacitance of the capacitor is determined by the area of each circuit conductor facing each other and the dielectric constant of the second resin layer 12. In the case of a built-in capacitor, it can be formed by a method of bonding a film or a chip capacitor with a bonding material.

  As described above, the structure of the semiconductor package according to the second embodiment of the present invention is not only a package structure that can be processed with the same size as the chip size of the semiconductor element, but also a multilayer structure using through holes. Since it is easy to achieve high density and high definition and high functionality at the same time, it is suitable for downsizing and high integration of devices to be used. In addition, a resin layer made of a material having characteristics close to those of the first resin layer and the second resin layer is formed, and the through holes and vias corresponding to the vias are filled in the cavity and the cavity. Since the conductive resin to be used is a low-temperature curing type, it is possible to obtain a package structure of a semiconductor device with extremely high reliability of bonding and connection with terminal portions such as bumps formed on the semiconductor element.

(Embodiment 3)
Subsequently, the structure of the semiconductor package according to the third embodiment of the present invention will be described with reference to FIGS. The semiconductor package according to the third embodiment of the present invention uses a plurality of semiconductor elements, and bumps formed on the terminal portions of the respective semiconductor elements are embedded in a resin layer to form a single package. It is the structure which aimed at. FIG. 7 is a cross-sectional view showing the structure of a semiconductor package in which bumps formed on terminal portions of a plurality of semiconductor elements having the same shape are embedded in a resin layer, and FIG. 8 is a terminal portion of semiconductor elements having a plurality of different shapes. It is sectional drawing which shows the structure of the semiconductor package which embed | buried and formed the bump formed in the resin layer. FIGS. 7 and 8 show examples of two semiconductor elements. However, in the case of two or more semiconductor elements, explanation can be made by applying the respective configurations in the same manner as in the case of two semiconductor elements, so that duplication is avoided. Therefore, explanation is omitted.

  In the semiconductor package 49 shown in FIG. 7A, two semiconductor elements 2a and 2b having the same shape and having a thickness dimension t in which the bump 3 is formed on the circuit forming surface side are opposite to the surface on which the bump 3 is formed. It is installed and fixed at a predetermined position on the base film 24 so as to be in contact with the surface. In the case of a package structure including a plurality of semiconductor elements 2 a and 2 b, it is common to install and fix at a predetermined position using a base film 24.

  The base film 24 may be made of a material that has adhesiveness and does not cause deformation, breakage, or abnormal expansion / contraction due to heat treatment that requires heating to about 200 ° C. in the manufacturing process of the semiconductor package. desirable. In particular, the expansion and contraction can be expected to reduce the influence of expansion and contraction due to the heat history by confirming by conducting an experiment such as heat treatment with only the material to be used in advance. As the material of the base film 24, an epoxy resin or a polyimide resin is usually used in many cases. The fixing method of the semiconductor elements 2a and 2b and the base film 24 differs depending on whether the base film 24 is left as a part of the semiconductor package 49 after the semiconductor package 49 is completed or removed. A known method such as using an adhesive or a pressure-sensitive adhesive can be used. By fixing the two semiconductor elements 2a and 2b to the base film 24, it is possible to form an integrated form as one semiconductor package 49, and it is possible to handle the same or close to one semiconductor element. Become.

  The configuration of the semiconductor package according to the third embodiment of the present invention shown in FIG. 7A is similar to the configuration of the semiconductor package according to the first embodiment of the present invention described with reference to FIG. The first resin layer 9 having a heat softening property and the first resin layer 13 with a conductive metal formed of a conductive metal are heated and pressurized to embed the bumps 3 in the first resin layer 9. It connects with the 1st circuit conductor 10a on the resin layer 9, and the joining particle 11 is installed and joined to the predetermined position on the 1st circuit conductor 10a after that. Here, in the formation of the bumps 3 of the individual semiconductor elements 2a and 2b, when it is difficult to adjust the height of the bumps 3 to a fixed height, the bumps 3 are fixed after the semiconductor elements 2a and 2b are fixed on the base film 24. A flat plate (not shown) is installed on the side and the base film 24 side, sandwiched and pressed, whereby the bump 3 can be compressed and deformed to adjust the bump height to the same. Also, until the bumps 3 are embedded in the first resin layer 9 of the first conductive metal-attached resin layer 13 and all the bumps 3 are contacted and connected by the pressure applied when connecting to the first circuit conductor 10a. It is possible to compress and deform the bump 3 by applying pressure.

  Further, a second resin layer 18 with a metal conductor is formed by patterning a conductor metal on the second resin layer 12 from above the bonding particles 11 to form the second circuit conductor 10b. The bonding particles 11 are embedded in the second resin layer 12 by heating and pressurizing, and are connected to the second circuit conductor 10b on the second resin layer 12 so that the two semiconductor elements 2a and 2b are connected. A semiconductor package 49 having a multilayer circuit structure is formed.

  The same two semiconductor elements 2a and 2b are fixedly integrated with the base film 24, and formed into a multilayer structure by the first conductor metal-attached resin layer 13, the second conductor metal-attached resin layer 18, and the bonding particles 11. A high-functional and high-density semiconductor package 49 that can be formed of the single semiconductor element 2 described in detail in the semiconductor package manufacturing method according to the first embodiment of the present invention shown in FIG. Since the manufacturing process can be applied almost as it is, the description of the manufacturing method is omitted to avoid duplication.

  In the configuration of the semiconductor package according to the third embodiment of the present invention shown in FIG. 7B, as shown in FIG. 7A, the semiconductor package 50 is connected to the terminal portions of a plurality of semiconductor elements having the same shape. The place where the formed bump is embedded in the resin layer is the same. The difference is that instead of using a multi-layered configuration with a resin layer with a conductive metal in which a circuit conductor is laminated with a conductive metal on a resin layer having adhesiveness and heat-softening properties and a bonding particle, a multi-layered configuration is used. In the same manner as in the configuration of the semiconductor package according to the second embodiment of the present invention described with reference to FIG. 4, a resin layer having adhesiveness and heat softening is provided with recesses and cavities serving as through holes or vias, and a conductive resin. Is filled in the concave and hollow portions to form a multilayer structure. The configuration of the semiconductor package in Embodiment 3 of the present invention shown in FIG. 7B is almost the same as the configuration of the semiconductor package in Embodiment 2 of the present invention described with reference to FIG. In order to avoid duplication, description of the configuration is omitted here.

  A plurality of semiconductor elements 2a and 2b are fixedly integrated with the base film 24, and a recess 22 and a cavity 23 corresponding to vias formed in the first resin layer 9 and the second resin layer 12, respectively. The high-performance, high-functionality, and high-density semiconductor package 50 having a multilayer structure by filling the conductive resin 20 into the semiconductor resin is described in detail in the semiconductor package manufacturing method according to the second embodiment of the present invention shown in FIG. Since the manufacturing process of the semiconductor package 42 formed of the single semiconductor element 2 described above can be easily manufactured by almost adapting it as it is, description of the manufacturing method is omitted here to avoid duplication.

  Note that the bumps 3 formed on the semiconductor elements 2a and 2b in the method using the conductive resin 20 are connected by the conductive resin 20 in the recesses 22, so that the bumps 3 can be used without adjusting the bump height. Is possible.

  In the semiconductor package 51 shown in FIG. 8A, the bump 3a, 3b is formed on the circuit forming surface side, the semiconductor element 31 having the thickness dimension x, and the other semiconductor element 32 having the thickness dimension t are bumps 3a. 3b is installed and fixed at a predetermined position on the base film 24 so as to be in contact with the surface opposite to the surface on which 3b is formed. In this case, the package structure includes two semiconductor elements 31 and 32 having different thickness dimensions, but is installed and fixed at a predetermined position using the base film 24 and integrated as one semiconductor package 51. It is possible to handle the same or nearly the same as one semiconductor element. Since the base film 24 can be made of the same material as that used for the installation and fixing of the same plurality of semiconductor elements shown in FIG. 7, the description regarding the base film 24 is omitted here to avoid duplication.

  The configuration of the semiconductor package according to the third embodiment of the present invention shown in FIG. 8A is similar to the configuration of the semiconductor package according to the first embodiment of the present invention described with reference to FIG. The first resin layer 9 having heat softening property and the first resin layer 13 with conductive metal formed by the conductive metal are heated and pressurized to embed the bumps 3a and 3b in the first resin layer 9, and It connects with the 1st circuit conductor 10a on the 1 resin layer 9, and the joining particle 11 is installed and joined to the predetermined position on the 1st circuit conductor 10a after that. Here, the bump 3a formed on the circuit surface of the semiconductor element 31 having the thickness dimension x and the bump 3b on the circuit surface of the semiconductor element 32 having the thickness dimension t are adjusted by adjusting the bump height at the time of bump formation. The total dimension h of the thickness dimension of the semiconductor element and the bump height is the same. When the bump 3b formed on the semiconductor element 32 has a normal bump height, the bump 3a formed on the semiconductor element 31 having a thickness dimension smaller than that of the semiconductor element 32 is formed to have a height dimension larger than that of the bump 3b. h is aligned with the total size of the semiconductor element 32.

  Thus, by making the total dimension h of two different semiconductor elements 31 and 32 the same, the first resin layer 9 with the conductive metal formed by the first resin layer 9 and the conductive metal is heated and pressurized. Then, the bumps 3a and 3b of the two different semiconductor elements 31 and 32, which are installed and fixed on the base film 24, are integrated in the first resin layer 9, and the first circuit conductor 10a. When joining with the conductor metal of the resin layer 13 with the first conductor metal formed as described above, all of the bumps can be easily joined.

  In addition, in the formation of the bumps 3a and 3b of the individual semiconductor elements 31 and 32, when it is difficult to adjust the total dimension h, the two semiconductor elements 31 and 32 are respectively placed on the base film 24 at predetermined positions. After fixing, a flat plate (not shown) is installed on each of the bumps 3a and 3b and the base film 24, sandwiched and pressed, and the bumps 3a and 3b are compressed and deformed to adjust the total dimension h. .

  Further, the bumps 3a and 3b of the two different semiconductor elements 31 and 32 are embedded in the first resin layer 9 of the resin layer 13 with the first conductor metal, and the pressure applied when connecting to the conductor metal is increased. It is also possible to pressurize until all the bumps 3a and 3b are in contact connection with the conductor metal, and compress the bump 3a and the bump 3b.

  The bump 3a and the bump 3b are embedded in the first resin layer 9 of the resin layer 13 with the first conductor metal and connected to the conductor metal, and then the conductor metal is removed by etching or laser processing. Then, the first circuit conductor 10a is patterned and formed, and then the bonding particles 11 are installed and bonded at predetermined positions on the first circuit conductor 10a.

  Further, a second resin layer 18 with a conductive metal is formed on the second resin layer 12 from above the bonding particles 11, and the second resin layer 12 is heated and pressurized so that the bonding particles 11 are second. After being embedded in the resin layer 12 and connected to the conductor metal on the resin layer 18 with the second conductor metal, unnecessary portions are removed by etching, laser processing, or the like, and the second resin layer 12 is removed. By patterning the second circuit conductor 10b thereon, a semiconductor package 51 having a multilayer circuit structure having two different semiconductor elements 31 and 32 is formed.

  Two different semiconductor elements 31 and 32 are fixed to and integrated with the base film 24, and the first conductor metal-attached resin layer 13 having the first resin layer 9 and the second conductor metal having the second resin layer 12. A high-density, high-function, high-performance semiconductor package 51 in which a plurality of semiconductor elements 31 and 32 having different thicknesses are integrally formed by using a resin layer 18 and bonding particles 11 to form a multilayer structure. The manufacturing process of the semiconductor package 41 formed of the single semiconductor element 2 described in detail in the manufacturing method of the semiconductor package in the first embodiment of the present invention shown in FIG. Since this is possible, the description of the manufacturing method is omitted to avoid duplication.

  In the configuration of the semiconductor package according to the third embodiment of the present invention shown in FIG. 8B, as shown in FIG. 8A, the semiconductor package 52 includes a semiconductor element 32 having a thickness dimension t, and a thickness dimension. The same is true in that the bumps 3a and 3b formed in the respective terminal portions of a plurality of differently shaped semiconductor elements 31 of the semiconductor element 31 having x are embedded in the resin layer. The difference is that instead of using a multi-layered configuration with a resin layer with a conductive metal in which a circuit conductor is laminated with a conductive metal on a resin layer having adhesiveness and heat-softening properties and a bonding particle, a multi-layered configuration is used. As in the configuration of the semiconductor package according to the second embodiment of the present invention described with reference to FIG. 4, through holes or vias are formed in the first resin layer 9 and the second resin layer 12 having adhesiveness and thermal softening property. The concave portions 22 and the hollow portions 23 are provided, and the conductive resin 20 is used to fill the concave portions 22 and the hollow portions 23 to form a multilayer structure. In addition, since a plurality of semiconductor elements having different thicknesses are used in forming the bumps, the bump height needs to be adjusted as described in the configuration of FIG. Let me explain.

  The bump height is adjusted by changing the heights of the bumps 3a and 3b formed on the semiconductor elements 31 and 32 having different thicknesses so as to be equal to the total dimension h, and the bumps 3a and 3b of the semiconductor elements 31 and 32. A method of forming bumps with a constant height dimension is considered.

  Since the method of aligning the total dimension h can be performed in accordance with the method described in the configuration of FIG. 8A, here, the bump height is constant regardless of the thickness dimension of the semiconductor element. Will be described. When bumps having a constant height are used as shown in FIG. 8B, the difference in thickness (t−x) between the semiconductor element 31 and the semiconductor element 32 is the same as that of the two semiconductor elements 31 and 32. It appears as a dimensional difference in the height direction including the bumps 3a and 3b. This dimensional difference is the depth from the surface of the first resin layer 9 to the ends of the bumps 3a and 3b when the recess 22 exposing the upper ends of the bumps 3a and 3b is formed in the first resin layer 9. It is necessary to change the filling amount of the conductive resin 20 according to the amount of the difference.

  In consideration of the above, first, the bumps 3a and 3b having a certain height are embedded in the semiconductor elements 31 and 32 which are installed and fixed at predetermined positions on the base film 24 and have different thicknesses. Thus, the first resin layer 9 is formed. Next, the second resin layer 9 on the bumps 3 a and 3 b buried in the first resin layer 9 is removed, and the upper end portion of the bump 3 is exposed to form the recess 22. The recess 22 is formed as a difference in depth from the surface of the first resin layer 9 to the upper ends of the bumps 3a and 3b with the semiconductor elements 31 and 32, but the depth of the recess 22 The difference in thickness is eliminated by filling the conductive resin 20 up to the surface of the first resin layer 9. The first circuit conductor 21a is formed on the surface of the first resin layer 9 using the conductive resin 20 so as to connect to the filled conductive resin 20, thereby connecting to the conductive resin 20 in the recess 22 The semiconductor elements 31 and 32 can be electrically connected. Therefore, in the method described above, since the bumps 3a and 3b formed on the plurality of semiconductor elements 31 and 32 are connected by the conductive resin 20 in the recess 22, it is particularly necessary to adjust the bump height. do not do.

  Then, a second resin layer 12 having a cavity 23 serving as a second via is further provided on the first circuit conductor 21 a formed on the first resin layer 9, and the cavity 23 is electrically conductive. The electronic circuit is configured by filling the resin 20 and forming the second circuit conductor 21b on the surface of the second resin layer 12 to form a multilayer structure, so that a plurality of semiconductor elements 31 and 32 having different thicknesses are formed. The semiconductor package 52 comprised by these can be formed.

  Instead of connecting the first circuit conductor 21a and the second circuit conductor 21b with the conductive resin 20 filled in the hollow portion 23 and sandwiching the second resin layer 12, the structure shown in FIG. Thus, a configuration in which the bonding particles 11 are used for connection is also possible.

  Further, the semiconductor element 31 and the semiconductor element 32 having different thickness dimensions are fixed on the base film 24 and integrated, and the recess 22 and the cavity formed in the first resin layer 9 and the second resin layer 12, respectively. A high-performance, high-functionality, high-density semiconductor package 52 having a multilayer structure by filling the conductive resin 20 into the semiconductor package 23 in the semiconductor package manufacturing method according to the second embodiment of the present invention shown in FIG. Since the manufacturing process of the semiconductor package 42 formed by the single semiconductor element 2 described in detail can be easily applied by adapting almost as it is, description of the manufacturing method is omitted here to avoid duplication.

  The structure of the semiconductor package according to the third embodiment of the present invention is a structure in which a plurality of semiconductor elements are arranged and fixed on a base film and formed into multiple layers. FIG. 7 and FIG. Although only the example using an element is shown, it cannot be overemphasized that it is applicable to the case of two or more semiconductor elements.

  As described above, the structure of the semiconductor package according to the third embodiment of the present invention is that a plurality of semiconductor elements can be installed and fixed using a base film to form a multi-layer structure. Easy to unitize. In addition, by providing adhesiveness to the base film and embedding the entire semiconductor element in the resin layer, the semiconductor element is integrated with the resin layer and the circuit conductor, thereby protecting the circuit formation surface of the semiconductor element and mechanical strength. As a result, the reliability and productivity of the semiconductor package can be improved. Further, since the same configuration as described in the structure of the semiconductor package in the first and second embodiments is used, it relates to the bonding between the bump formed on each semiconductor element and the circuit conductor at the time of multilayering. Problems can be reduced and a high-quality semiconductor package structure can be realized.

  The structure of the semiconductor package according to the present invention is a structure in which a semiconductor element and a circuit board are integrally formed by a method of forming a circuit board in a semiconductor element, and the semiconductor device is reduced in size, reliability, function, and performance. This makes it possible to improve the performance, function, and reliability of each device by applying it to OA equipment, home appliances, and the like, and it is extremely useful for improving productivity at the time of manufacturing.

Sectional drawing which shows the structure of the semiconductor package in Embodiment 1 of this invention Sectional drawing which shows the other structure of the semiconductor package in Embodiment 1 of this invention The flowchart which shows an example of the process for manufacturing the semiconductor package in Embodiment 1 of this invention Sectional drawing which shows the structure of the semiconductor package in Embodiment 2 of this invention Sectional drawing which shows the other structure of the semiconductor package in Embodiment 2 of this invention A flow chart which shows an example of a process for manufacturing a semiconductor package in Embodiment 2 of the present invention. Sectional drawing which shows the structure of the semiconductor package which embed | buried and formed the bump formed in the terminal part of the several semiconductor element of the same shape in Embodiment 3 of this invention in the resin layer Sectional drawing which shows the structure of the semiconductor package which embed | buried and formed in the resin layer the bump formed in the terminal part of the several semiconductor element of different shape in Embodiment 3 of this invention Sectional view showing the structure of a conventional multilayer substrate Sectional drawing which shows the structure of a CSP type semiconductor device

Explanation of symbols

2, 2a, 2b, 31, 32 Semiconductor element 3, 3a, 3b, 260 Bump 9, 9a, 104 First resin layer 10a, 21a First circuit conductor 10b, 21b Second circuit conductor 10c, 21c Third Circuit conductor 11, 103 bonding particle 12 second resin layer 13 resin layer with first conductor metal 14 (electrical) conductor metal 15 third resin layer 16 resistance (resistor)
17 Capacitor
18 Second resin layer with metal conductor 19 Through hole 20 Conductive resin 22 Recess 23 Cavity 24 Base film 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52 Semiconductor package 53 Electronic component 101 Resin film 102 First circuit pattern 106 Second circuit pattern 200 Semiconductor device 210 Semiconductor chip 215 Terminal 220 Insulating layer 240 Wiring 250 Solder resist 270 Via part 290 Insulating adhesive layer

Claims (21)

A semiconductor element, a first resin layer, conductive bonding particles, and a second resin layer,
The semiconductor element has a protruding bump formed on a terminal portion, the first resin layer has adhesiveness and thermoplasticity, a conductor layer is laminated on one surface, and the second resin layer Has adhesiveness and thermoplasticity and another conductor layer is laminated on one side,
The bumps are embedded in the first resin layer softened by heating and bonded to the conductor layer, and the bonding particles are arranged at predetermined positions of the first circuit conductor formed by patterning the conductor layer. The bonding particles are embedded in the second resin layer that is bonded and softened by heating, and bonded to another conductor layer, and the second conductor layer is patterned to form a second circuit conductor. A structure of a semiconductor package, wherein the bump and the second circuit conductor are connected to be multi-layered. A semiconductor element, a first resin layer, conductive bonding particles, and a second resin layer,
The semiconductor element has a protruding bump formed on a terminal portion, the first resin layer has adhesiveness and thermoplasticity, and the second resin layer has adhesiveness and thermoplasticity. A conductor layer is laminated on one side,
The tip of the bump is completely embedded and the first resin layer is laminated to a thickness exceeding the tip, and the tip of the bump is exposed at a position corresponding to the bump on the first resin layer. A via is formed, and the via is filled with a conductive resin so as to be bonded to the bump, and a first circuit conductor is formed on the surface of the first resin layer with the conductive resin, and the bump and the bump The first circuit conductor is connected, the bonding particles are arranged and bonded at predetermined positions of the first circuit conductor, the bonding particles are embedded in the second resin layer heated and softened, and A semiconductor package which is bonded to a conductor layer, is patterned to form a second circuit conductor, and the bumps and the second circuit conductor are connected to form a multilayer. Structure. Comprising a semiconductor element, a first resin layer and a second resin layer;
The semiconductor element has a protruding bump formed on a terminal portion, and the first resin layer and the second resin layer have adhesiveness and thermoplasticity,
The tip of the bump is completely embedded and the first resin layer is laminated to a thickness exceeding the tip, and the tip of the bump is exposed at a position corresponding to the bump on the first resin layer. The first via is formed, the first via is filled with a conductive resin so as to be joined to the bump, and the first circuit conductor is formed on the surface of the first resin layer by the conductive resin. The bump and the first circuit conductor are connected to each other, a second resin layer is formed on the first resin layer with a predetermined thickness, and a predetermined surface on the surface of the second resin layer is formed. A second via reaching the first circuit conductor is formed at the position, and the second via is filled with a conductive resin so as to be connected to the first circuit conductor, and the second resin A second circuit conductor is formed on the layer by the conductive resin, and the bump Structure of the semiconductor package, characterized in that said second circuit conductor is multi-layered and connected. A semiconductor element, a first resin layer, conductive bonding particles, and a second resin layer,
The semiconductor element has a protruding bump formed on a terminal portion, the first resin layer has adhesiveness and thermoplasticity, and the second resin layer has adhesiveness and thermoplasticity. A conductor layer is laminated on one side,
The tip of the bump is exposed or embedded so that the tip of the bump protrudes, and the first resin layer is laminated and formed on the surface of the first resin layer by a conductive resin. The bumps exposed on the surface of the first resin layer formed with circuit conductors are connected to the first circuit conductors, and the bonding particles are arranged and bonded at predetermined positions of the first circuit conductors. The bonding particles are embedded in the second resin layer softened by heating and bonded to the conductor layer, and a second circuit conductor is formed by patterning the conductor layer, and the bump and the first 2. A structure of a semiconductor package, wherein the circuit conductors are connected to each other to be multilayered. A semiconductor element, a first resin layer, conductive bonding particles, and a second resin layer,
The semiconductor element has a protruding bump formed on a terminal portion, the first resin layer has adhesiveness and thermoplasticity, and the second resin layer has adhesiveness and thermoplasticity. A conductor layer is laminated on one side,
The tip of the bump is exposed or embedded so that the tip of the bump protrudes, and the first resin layer is laminated and formed on the surface of the first resin layer by a conductive resin. The bumps exposed on the surface of the first resin layer formed with circuit conductors are connected to the first circuit conductor, and the second resin layer is formed on the first resin layer with a predetermined thickness. Is formed, and a via reaching the first circuit conductor is formed at a predetermined position on the surface of the second resin layer, and the via is filled with a conductive resin so as to connect to the first circuit conductor. In addition, a second circuit conductor is formed of the conductive resin on the second resin layer, and the bump and the second circuit conductor are connected to be multilayered. Semiconductor package structure. The entire semiconductor element is embedded in the first resin layer having an area larger than that of the semiconductor element, and the second resin layer has the same size as the first resin layer. The structure of the semiconductor package of any one of Claims 1-5. The bonding particles having conductivity are arranged at predetermined positions of the first circuit conductor, and the first circuit conductor and the bonding particles are bonded,
The second resin layer having adhesiveness and thermoplasticity obtained by laminating the conductor layer is heated, the bonding particles are embedded in the second resin layer, and the conductor layer of the second resin layer and the The bonding particles are bonded,
5. The multi-layered structure according to claim 1, wherein the conductive layer of the second resin layer is patterned to repeat the formation of the second circuit conductor. The structure of the semiconductor package as described in the item. 7. The structure of a semiconductor package according to claim 6, wherein the exposed surface of the semiconductor element is further covered and buried with a third resin layer having the same size as the first resin layer. The semiconductor element is embedded in the first resin layer larger than the semiconductor element, the exposed surface of the semiconductor element is covered with the third resin layer having the same size as the first resin layer, and the third resin layer is covered with the third resin layer. A third circuit conductor is formed on the surface of the resin layer opposite to the circuit formation surface of the semiconductor element, and penetrates the first resin layer, the second resin layer, and the third resin layer at the same position. 9. The structure of a semiconductor package according to claim 8, wherein circuit conductors are connected to each other with a through-hole formed therebetween to connect the circuit conductors to form a multilayer. 10. The structure of a semiconductor package according to claim 1, wherein the semiconductor element is in the form of a chip made of an individual piece or a diced wafer. 11. The structure of a semiconductor package according to any one of claims 1 to 10, wherein at least one of the semiconductor elements is installed on a resin base film having adhesiveness. The semiconductor package structure according to claim 11, wherein a plurality of the semiconductor elements having different thicknesses are disposed on the base film. 13. The semiconductor package structure according to claim 1, wherein individual electronic components including a coil, a resistor, and a capacitor are built in the second resin layer. The bonding particles formed by processing a metal simple substance or an alloy, or by resin plating using a chemical containing a metal simple substance or an alloy on resin particles are used. The structure of a semiconductor package according to any one of claims 4 and 6 to 13. The metal material used for forming the bonding particles is a single metal of gold, silver, copper, tin, palladium, nickel, platinum, or aluminum, or an alloy mainly composed of any of the metals. The structure of a semiconductor package according to claim 14. As the material for forming the first resin layer and the second resin layer, a material obtained by printing or laminating a heat-softening resin or a material obtained by heating and pressure laminating a resin member in a sheet state is used. The structure of a semiconductor package according to claim 1, wherein: The material for forming the third resin layer is a material obtained by printing or laminating a heat-softening resin, or a material obtained by heating and pressure laminating a resin member in a sheet state. Semiconductor package structure. A step of arranging and placing the surface side on which the bump-shaped bumps are formed on the terminal portion of the semiconductor element and the side of the first resin layer on which the conductor layer is laminated, facing each other;
Heating and softening the first resin layer, pressurizing, embedding the bump in the first resin layer, and bonding the conductor layer and the bump;
Patterning the conductor layer of the first resin layer to form a first circuit conductor;
Disposing conductive bonding particles at predetermined positions of the first circuit conductor to bond the first circuit conductor and the bonding particles;
On the upper side where the bonding particles are installed, the step of placing and arranging the second resin layer on which another conductor layer is laminated,
Heat-softening and pressurizing the second resin layer, burying the bonding particles in the second resin layer, and bonding the other conductor layer and the bonding particles;
And a step of patterning another conductor layer of the second resin layer to form a second circuit conductor. A step of forming the first resin layer to a thickness exceeding the tip, with the tip of the bump being completely embedded on the surface on which the bump-like bump is formed on the terminal portion of the semiconductor element;
Forming a first via that exposes the tip of the bump by drilling at a predetermined position corresponding to the bump on the surface of the first resin layer;
Filling the first via with a conductive resin and bonding to the bump;
Forming a first circuit conductor with the conductive resin on the surface of the first resin layer, and connecting the bump and the first circuit conductor;
Forming a second resin layer with a predetermined thickness on the first resin layer on which the first circuit conductor is formed;
Forming a second via reaching the first circuit conductor by drilling at a predetermined position on the surface of the second resin layer;
Filling the second via with a conductive resin and bonding to the first circuit conductor;
Forming a second circuit conductor with the conductive resin on the surface of the second resin layer, and connecting the bump and the second circuit conductor. Manufacturing method. Filling the first via with the conductive resin and bonding the bump to the bump; forming the first circuit conductor on the surface of the first resin layer with the conductive resin; 20. The method of manufacturing a semiconductor package according to claim 19, wherein the step of connecting the first circuit conductor and the first circuit conductor is performed simultaneously. Filling the second via with the conductive resin and bonding to the first circuit conductor; and forming the second circuit conductor on the surface of the second resin layer with the conductive resin. 20. The method of manufacturing a semiconductor package according to claim 19, wherein the step of connecting the bump and the second circuit conductor is simultaneously performed.

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