JP2006049840A - Variable capacitance capacitor, circuit module and communication device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a variable resonance circuit which exhibits a low degree of waveform distortion or intermodulation distortion, a high electric power resistance and a low loss. <P>SOLUTION: Several variable capacitors C1-C4 each using a thin-film dielectric layer whose dielectric constant varies with applied voltage are connected in series between an input terminal I and an output terminal O of high-frequency signal. First bias lines B11, B12 and B13 on the high potential side of applied voltage and second bias lines B21 and B22 on the low potential side are alternately connected to both ends of the several variable capacitors and between the capacitors. In this way, the rate of capacitance change of a variable capacitance capacitor by bias signal can be maximally used and the resonance frequency can be changed in a wide range of frequencies. In addition, the variable capacitance capacitor exhibits a low degree of waveform distortion or intermodulation distortion in a high-frequency electronic component, a high electric power resistance and a low loss even at a high-frequency. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a variable capacitor having a dielectric layer whose dielectric constant changes depending on an applied voltage and capable of changing a resonance frequency when the capacitance changes, and a circuit module and a communication device using the same. In particular, the present invention relates to a variable capacitor excellent in characteristics such as power durability, low distortion, and low loss, and a circuit module and a communication device using the same.

  Conventionally, a thin film capacitor in which the dielectric constant of a dielectric layer changes according to an applied voltage has been proposed (see, for example, Patent Document 1).

  The thin film capacitor proposed in Patent Document 1 includes a lower electrode layer 202, a thin film dielectric layer 203, an upper electrode layer 204, and a lower electrode layer 202 on a support substrate 201, as shown in a sectional view in FIG. Is a thin film capacitor 200 formed by sequentially depositing and depositing. Specifically, a conductor layer to be the lower electrode layer 202 is deposited on substantially the entire surface of the support substrate 201, and then patterned into an electrode shape to form the lower electrode layer 202 having a predetermined shape. Next, a thin film dielectric layer 203 is formed on the lower electrode layer 202. The thin film dielectric layer 203 is formed by placing a mask at a predetermined position and forming it by a thin film forming method, or forming it by a spin coating method and then patterning it into a predetermined shape. Note that the thin film dielectric layer 203 is heat-cured as necessary. Next, after forming a conductor layer to be the upper electrode layer 204 on substantially the entire surface of the thin film dielectric layer 203, the upper electrode layer 204 having a predetermined shape is formed by patterning the electrode shape of the upper electrode layer 204. The thin film capacitor 200 was formed. Here, in the thin film dielectric layer 203, a facing region that is actually sandwiched between the lower electrode layer 202 and the upper electrode layer 204 is a capacitance generation region.

According to such a thin film capacitor 200, a predetermined direct current bias voltage (bias signal) is applied to the thin film dielectric layer 203, and the dielectric constant of the thin film dielectric layer 203 is controlled to a desired value, so that the capacitance characteristic is obtained. As a result, it functions as a variable capacitor.
Japanese Patent Laid-Open No. 11-260667

  However, when this thin film capacitor 200 is used, for example, as shown in the equivalent circuit diagrams in FIGS. 11A and 11B, the bias signal is an external circuit formed on the wiring board on which the thin film capacitor 200 is mounted. (Bias supply circuit) G was supplied.

  Here, in FIG. 11A, a choke coil 205 as an inductance component is arranged between a connection point A between the thin film capacitor 200 and the bias supply circuit G and the bias terminal V.

  In FIG. 11B, a strip line 206 having a λ / 4 line length with respect to the wavelength λ of the high-frequency signal operated by the thin film capacitor 200 is formed in the bias supply circuit G. One end of the strip line 206 on the bias terminal V side is grounded, and a DC limiting capacitance element 208 is formed between one end of the strip line 206 on the bias terminal V side and the ground portion.

  As described above, when the thin film capacitor 200 is used, in addition to the thin film capacitor 200, a bias supply circuit G corresponding to the structure and characteristics of the thin film capacitor 200 must be prepared on the wiring board. For this reason, it is necessary to design the bias supply circuit G corresponding to the thin film capacitor 200 mounted on the wiring board, and there is a problem that adjustment is very complicated. Furthermore, since the thin film capacitor 200 and the bias supply circuit G are configured separately, there is a problem that the size of the thin film capacitor 200 and the bias supply circuit G increase as a whole.

  In addition, when the thin film capacitor 200 as described above is used as a high frequency electronic component, a DC bias voltage for changing the capacitance and a high frequency signal voltage (high frequency voltage) are simultaneously applied to the thin film capacitor 200. become. However, when the high-frequency voltage is high, the capacitance of the thin film capacitor 200 is also changed by the high-frequency voltage, so that waveform distortion, intermodulation distortion, and the like occur in the high-frequency electronic component. In order to reduce the waveform distortion, intermodulation distortion, etc., it is necessary to reduce the capacitance change due to the high-frequency voltage by reducing the high-frequency electric field strength. For this purpose, it is effective to increase the thickness of the thin film dielectric layer 203. However, when the thickness of the thin film dielectric layer 203 is increased, the DC electric field strength is also reduced, so that there is a problem that the capacity change rate due to the DC bias voltage is also reduced.

  In addition, since a current easily flows through the capacitor in the high frequency region, there is a problem in terms of power resistance that the capacitor generates heat due to the loss resistance of the capacitor and is destroyed when the capacitor is used in the high frequency region. It is effective to increase the thickness of the thin film dielectric layer 203 and reduce the amount of heat generated per unit volume in order to cope with such problems with power durability. As described above, the thin film dielectric layer 203 is effective. If the thickness is increased, the DC electric field strength is also reduced, so that the rate of change in capacity due to the DC bias voltage is also lowered.

  The present invention has been devised in view of the above-described problems in the prior art, and the object thereof is to eliminate the need for forming an independent external bias supply circuit for the variable capacitor and to facilitate handling. The object is to provide a variable capacitor.

  Another object of the present invention is to provide a variable capacitor that suppresses capacitance change due to a high-frequency signal, has low intermodulation distortion, has excellent power resistance, and can greatly change capacitance by a DC bias. It is in.

  Still another object of the present invention is to provide a circuit module and a communication device using the above-described variable capacitor.

  In the variable capacitor of the present invention, 1) a plurality of variable capacitance elements using a thin film dielectric layer whose dielectric constant is changed by an applied voltage between an input terminal and an output terminal of a high-frequency signal are connected in series; The first bias line on the high potential side and the second bias line on the low potential side of the applied voltage are alternately connected to both ends of the plurality of variable capacitance elements and between the elements. .

  The variable capacitance capacitor of the present invention is 2) In the configuration of 1) above, among the plurality of variable capacitance elements, the capacitance value of the variable capacitance element group A in which the first bias line is connected to the input terminal side. And a total value of capacitance values of the variable capacitance element group B in which the first bias line is connected to the output terminal side are substantially equal to each other.

  The variable capacitor of the present invention is characterized in that 3) in the configuration of 2), the variable capacitor is an even number.

  In the variable capacitor according to the present invention, 4) in the configuration of 3), the variable capacitance element of the variable capacitance element group A and the variable capacitance element of the variable capacitance element group B are substantially equal in capacitance value. It is characterized by being a pair.

  In addition, the variable capacitor of the present invention is characterized in that, in 5) the configuration of 3), the capacitance values of the plurality of variable capacitors are substantially equal.

  The variable capacitor according to the present invention is characterized in that 6) in the configuration of 2), the variable capacitor is an odd number.

  The variable capacitor of the present invention is 7) In the configuration of any one of 1) to 4) or 6), the variable capacitor connected to the input terminal and the variable capacitor connected to the output terminal. The element has a capacitance value larger than that of the other variable capacitance elements.

  The circuit module of the present invention is characterized in that the variable capacitor of the present invention having any one of the constitutions 1) to 7) is used as a capacitor constituting a resonance circuit.

  The communication apparatus of the present invention is characterized in that the circuit module of the present invention is used as a filter means.

  According to the variable capacitor of the present invention (with the configuration in which the bias terminals V1 and V2 are connected as shown in FIG. 1), 1) the dielectric constant changes depending on the applied voltage between the input terminal and the output terminal of the high-frequency signal. A plurality of variable capacitance elements using thin film dielectric layers are connected in series, and a first bias line on the high potential side and a second bias line on the low potential side of the applied voltage are connected to both ends of the plurality of variable capacitance elements and Since each element is connected alternately, an independent bias supply circuit mounted on an external wiring board like a conventional variable capacitor can be eliminated, and a variable capacitor is mounted. The circuit board can be miniaturized and handled easily.

  In the variable capacitor of the present invention, a plurality of variable capacitors are connected in series, and the first bias line on the high potential side and the second bias line on the low potential side of the applied voltage include the plurality of variable capacitors. Are alternately connected between the two ends and each element, so that an applied voltage supplied via the first bias line, that is, a DC bias voltage (bias signal) is independently applied to each variable capacitance element, and thereafter By passing through the second bias line, the variable capacitance elements are connected in parallel in terms of DC. For this reason, a desired DC bias voltage can be applied to each variable capacitance element, so that the capacity change rate of each variable capacitance element due to the DC bias voltage can be utilized to the maximum, and the capacitance can be greatly changed. Is possible. The variable capacitor according to the present invention includes a plurality of variable capacitors, but each variable capacitor is connected in parallel to the bias signal path, so that a bias power supply for supplying a DC bias voltage is provided. Can be combined into two (one when one is grounded), and the configuration of the circuit board on which the variable capacitor is mounted is simplified.

In the variable capacitor according to the present invention, since a plurality of variable capacitors are connected in series in high frequency, the high frequency voltage applied to the variable capacitors is divided into each variable capacitor, so that each variable capacitor The high-frequency voltage applied to the capacitive element is divided and reduced, which makes it possible to reduce the capacitance fluctuation caused by the high-frequency signal of the variable capacitor, and to greatly suppress waveform distortion and intermodulation distortion in high-frequency electronic components. can do. Furthermore, since a plurality of variable capacitance elements are connected in series in terms of high frequency, there is the same effect as increasing the thickness of the dielectric layer of the capacitance elements in terms of high frequency. The calorific value per volume can be reduced, and the power resistance can be improved. Here, the waveform distortion means that a harmonic signal is generated by energy conversion to a frequency different from that of the input signal because the capacitance of the variable capacitor changes depending on the voltage of the input signal (high frequency signal), and the waveform distortion occurs in the output signal. That means. Intermodulation distortion means that when an input signal is two input signals having different frequencies, the output signal is a sum term of the two input signals, a square term of the sum, and a cube term of the sum. , Expressed by an expression that adds the fourth or higher term of the sum, and in the second or higher term of the sum, the two input signals are mixed (multiplied), and intermodulation distortion (harmonic of the product term) Occurs. Specifically, two input signals (X = A cos ω ₁ t + B cos ω ₂ t) (A and B are constants) are converted into a variable capacitance capacitor (y = α ₁ X + α ₂ X ² + α ₃ X ³ +... ) (Α ₁ , α ₂ , α ₃ are constants), the output signal is y = α ₁ (Acosω ₁ t + Bcosω ₂ t) + α ₂ (Acosω ₁ t + Bcosω ₂ t) ² + α ₃ (Acosω ₁ t + Bcosω ₂ t ) ³ ..., and, when deploying it, square terms _{2ABcosω 1 t · cosω 2 t =} cos (ω 1 ± ω 2) t, 3 cube of section _{^{3A 2 Bcos 2 ω 1 t ·}} cosω 2 It includes an intermodulation distortion represented by t = cos (2ω ₁ ± ω ₂ ) t, 3AB ² cosω ₁ t · cos ² ω ₂ t = cos (2ω ₂ ± ω ₁ ) t.

  As described above, according to the variable capacitor of the present invention, since a plurality of variable capacitors are connected in series in terms of high frequency, capacitance variation due to a high frequency signal is suppressed, and when used as high frequency electronic components, The modulation distortion is small and the power durability is excellent.

  According to the variable capacitor of the present invention, 2) in the configuration of 1), the capacitance value of the variable capacitor group A in which the first bias line is connected to the input terminal side among the plurality of variable capacitors. And the total value of the capacitance values of the variable capacitance element group B having the first bias line connected to the output terminal side are substantially equal to each other. In addition, since DC bias voltages having different polarities are applied between the variable capacitance element group A and the variable capacitance element group B, the capacitance fluctuations caused by the high-frequency voltage between the variable capacitance element group A and the variable capacitance element group B are offset. As a result, the fluctuation of the capacitance value due to the high-frequency signal of the entire variable capacitor can be further reduced. It can be without.

  Further, according to the variable capacitor of the present invention, 3) in the configuration of 2) above, since the variable capacitance elements are even numbers, the direction of the DC bias voltage applied to each variable capacitance element varies alternately, but is variable. Because the number of capacitive elements is an even number, the effect of the difference in the direction of the DC bias voltage between adjacent variable capacitive elements is offset to eliminate the polarity with respect to the bias signal. As a result, when mounting as a variable capacitive capacitor It is easy to handle without paying attention to the polarity.

  According to the variable capacitor of the present invention, 4) in the configuration of 3) above, the variable capacitance elements of the variable capacitance element group A and the variable capacitance elements of the variable capacitance element group B have a pair of capacitance values that are substantially equal. Therefore, even if the capacitance of each variable capacitive element varies due to the high-frequency voltage, the variable capacitive element group A and the variable capacitive element group B are applied with DC bias voltages having different polarities. Capacitance fluctuations are canceled out between the variable quantity elements that are pairs of substantially the same capacitance values of the element group A and the variable capacitance element group B. Therefore, the fluctuation of the capacitance value due to the high-frequency signal of the entire variable capacitor is reduced. As a result, when used as a high-frequency electronic component, waveform distortion and intermodulation distortion with respect to a high-frequency signal can be reduced.

  Further, according to the variable capacitor of the present invention, 5) In the configuration of 3) above, the capacitance values of the plurality of variable capacitors are substantially equal. Since any variable capacitance element of the capacitance element group B forms a pair having substantially the same capacitance value, the variable capacitance element group A and the variable capacitance element even if the capacitance of each variable capacitance element varies due to a high-frequency voltage. Since a DC bias voltage having a polarity different from that of the group B is applied, the capacitance variation is canceled between the variable capacitance elements which are pairs of substantially the same capacitance values of the variable capacitance element group A and the variable capacitance element group B. As a result, the fluctuation of the capacitance value due to the high-frequency signal of the entire variable capacitor can be further reduced. It is possible to reduce the distortion. In addition, since a plurality of the same variable capacitance elements need only be formed, the manufacturing becomes easier as compared with the case where the design of each variable capacitance element is different.

  According to the variable capacitor of the present invention, 6) in the configuration of 2), since the variable capacitance element is an odd number, the input terminal and the output terminal which are signal terminals for supplying a high-frequency signal, A bias capacitor for supplying a bias signal to which the first and second bias lines are connected can be made common, and as a result, an easily handled variable capacitor that can increase the degree of freedom in mounting, pattern design, etc. Can do.

  According to the variable capacitor of the present invention, 7) in the configuration of any one of 1) to 4) or 6), the variable capacitor connected to the input terminal and the variable capacitor connected to the output terminal are The stray capacitance generated between the input capacitor and the variable capacitor connected to the input terminal and between the output capacitor and the variable capacitor connected to the output terminal because the capacitance value is larger than other variable capacitors. Since the capacitance value of the variable capacitance element connected to the input terminal and the variable capacitance element connected to the output terminal is larger than the value, the variable capacitance element connected to the input terminal and the variable capacitance element connected to the output terminal The influence of the stray capacitance value on the capacitance value is small. The capacitance value of the variable capacitor is the reciprocal of the sum of the reciprocal of the capacitance value of each variable capacitance element because the variable capacitance elements are connected in series. Therefore, the variable capacitance element connected to the input terminal and the output The capacitance value of the variable capacitance element connected to the terminal contributes less to the capacitance value of the variable capacitance capacitor than the capacitance values of the other variable capacitance elements. As a result, the influence of the stray capacitance can be suppressed, and the variation in the capacitance value of the variable capacitor is small.

  Further, according to the circuit module of the present invention, the variable capacitance capacitor of the present invention having any one of the above configurations 1) to 7) is used as a capacitor constituting the resonance circuit. Since a large and desired capacity can be obtained with high accuracy, a desired resonance frequency can be obtained with high accuracy over a wide frequency range. In addition, since the capacitor constituting the resonance circuit is excellent in power durability, the reliability is high.

  Further, according to the communication device of the present invention, since the circuit module of the present invention is used as the filter means, a desired resonance frequency can be accurately set over a wide frequency range. And a desired filter function can be obtained with high accuracy.

  Hereinafter, a variable capacitor, a circuit module, and a communication device of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is an equivalent circuit diagram showing an example of an embodiment of a variable capacitor of the present invention having four variable capacitors.

  In the equivalent circuit diagram shown in FIG. 1, symbols C1, C2, C3, and C4 are all variable capacitance elements, and B11, B12, and B13 are first bias lines including at least one of a resistance component and an inductor component (in FIG. And B21 and B22 are second bias lines including at least one of the resistance component and the inductor component (in the figure, the resistance components R21 and R22 are shown). In FIG. 1, the first bias terminal V1 is set to a higher potential than the second bias terminal V2 (the first bias terminal V1 may be a positive potential and the second bias terminal V2 may be a negative potential), and the variable capacitance element C1 , C3 is a variable capacitance element group A in which the first bias line is connected to the input terminal I side, and the variable capacitance elements C2 and C4 are variable capacitance element groups in which the first bias line is connected to the output terminal O side. B.

  In the variable capacitor Ct having such a configuration, a high frequency signal is passed between the input terminal I and the output terminal O of the variable capacitor Ct via the variable capacitors C1, C2, C3, and C4 connected in series. Will flow. At this time, the resistance components R11, R12, R13 and R21, R22 of the first bias lines B11, B12, B13 and the second bias lines B21, B22 are the frequency regions of the high frequency signals of the variable capacitance elements C1, C2, C3, C4. It is a large impedance component with respect to the impedance at, and does not adversely affect the impedance in the high frequency band.

  A bias signal for controlling the capacitance component of the variable capacitance element C1 is supplied from the first bias terminal V1 to the variable capacitance element C1 via the inductance L1 and the first bias line B11, and the second bias line B21 and the inductance L2 are supplied. To the second bias terminal V2. The variable capacitance element C1 has a predetermined dielectric constant according to the DC bias voltage applied to the variable capacitance element C1, and as a result, a desired capacitance component is obtained. The variable capacitance elements C2, C3, and C4 are also connected in parallel with each other through the first bias lines B12 and B13 and the second bias lines B21 and B22. A bias signal is applied, and a predetermined capacitance component can be obtained.

  As a result, the DC bias voltage for controlling the capacitances of the variable capacitance elements C1, C2, C3, and C4 to a desired value can be stably supplied to the variable capacitance elements C1, C2, C3, and C4 separately. In addition, the dielectric constants of the variable capacitance elements C1, C2, C3, and C4 can be changed as desired by applying a bias signal, so that the variable capacitance capacitor Ct can easily control the capacitance component.

  In the high frequency signal input to the variable capacitance elements C1, C2, C3, C4, the resistance components R11, R12, R13 and R21, R22 are impedance components that are large relative to the impedance in the frequency region of the high frequency signal. Therefore, there is no leakage through the first bias lines B11, B12, B13 and the second bias lines B21, B22. As a result, the bias signal is stably applied independently to the variable capacitance elements C1, C2, C3, and C4. As a result, each variable capacitance element C1, C2, C3, and C4 by the bias signal is applied. The capacity change rate can be used to the maximum.

  That is, in the variable capacitor Ct, the variable capacitors C1, C2, C3, and C4 can be regarded as variable capacitors connected in series in terms of high frequency.

  Therefore, the high-frequency voltage applied to the series-connected variable capacitance elements C1, C2, C3, and C4 is divided into the variable capacitance elements C1, C2, C3, and C4. The high frequency voltage applied to C2, C3 and C4 will decrease. From this, the capacitance variation with respect to the high frequency signal can be suppressed to be small, and waveform distortion, intermodulation distortion, and the like can be suppressed in the high frequency electronic component using the variable capacitor.

Further, by connecting the variable capacitance elements C1, C2, C3, and C4 in series, there is the same effect as increasing the thickness of the dielectric layer of the capacitance element in terms of high frequency, and the unit by the loss resistance of the variable capacitance capacitor. The calorific value per volume can be reduced, and the power resistance of the variable capacitor Ct can be improved. Here, the heat generation due to the loss resistance of the variable capacitor is defined as ESR as the loss resistance component of the variable capacitor, I as the current flowing through the variable capacitor (V as the voltage applied to the capacitor), and P as the power consumption. = I ² · ESR (P = V ² / ESR) occurs, and the variable capacitor generates heat.

  Further, since bias signals can be supplied from the first and second bias terminals V1 and V2 through the first bias lines B11, B12, B13 and the second bias lines B21, B22, external wiring is provided in the conventional variable capacitor. An independent bias supply circuit mounted on the substrate is not required, and the circuit substrate on which the variable capacitor Ct is mounted can be reduced in size and handled easily.

  Further, the first bias lines B11, B12, B13 on the high potential side of the applied voltage, that is, the first bias terminal V1, and the second bias lines B21, B22 on the low potential side, that is, the second bias terminal V2 side, Since the variable capacitance elements C1, C2, C3, and C4 are alternately connected to both ends and between the elements, the bias lines on the second bias terminal V2 side of the variable capacitance elements C1 and C2, the variable capacitance elements C2 and C3 The bias line on the first bias terminal V1 side and the bias line on the second bias terminal V2 side of the variable capacitance elements C3 and C4 can be shared. As a result, the number of bias lines can be reduced, and the configuration of the bias lines can be simplified.

  In the equivalent circuit diagram shown in FIG. 1, the second bias terminal V2 may be grounded. In this case, the inductance L2 is not necessary.

  Here, it is preferable that the total value of the capacitance values of the variable capacitance element group A and the total value of the capacitance values of the variable capacitance element group B are substantially equal. Hereinafter, the reason will be described with reference to FIGS.

  FIG. 2 shows the applied voltage dependence of the capacitance change rate of the variable capacitance elements C1, C2, C3 and C4. In FIG. 2, the horizontal axis represents the applied voltage (unit: V), and the vertical axis represents the capacity change rate (unit:%). Here, white circles indicate a state in which a DC bias voltage is applied, and black circles indicate a state in which a high frequency voltage is applied superimposed on the DC bias voltage while the DC bias voltage is applied.

  FIGS. 3A and 3B are conceptual diagrams showing a connection configuration of the variable capacitance elements C1, C2, C3, and C4 in the variable capacitance capacitor Ct shown in FIG. The variable capacitance elements C1 and C3 constituting A are collectively shown, and the variable capacitance elements C2 and C4 constituting the variable capacitance element group B are collectively shown.

  In FIG. 3A, in the state where the DC bias voltage is applied, the total value of the capacitance values of the variable capacitance element group A is C, and the total value of the capacitance values of the variable capacitance element group B is the variable capacitance element group. The total capacity value of A is x times the total value C, that is, xxC.

  FIG. 3B shows the total capacitance value of the variable capacitance element group A and the total capacitance value of the variable capacitance element group B when a high frequency voltage is applied in a state where a DC bias voltage is applied. ing.

  As shown in FIG. 2, when a high frequency voltage is applied to the variable capacitance elements C1, C2, C3, and C4 with a DC bias voltage applied, the DC bias voltage is When the potential is positive, the bias voltage actually applied to the variable capacitance elements C1, C2, C3, and C4 is increased by the application of the high frequency voltage, and as a result, the capacitance value is reduced as compared with the state where only the DC bias voltage is applied. . On the contrary, when the DC bias voltage is a negative potential, the DC bias voltage actually applied to the variable capacitance elements C1, C2, C3, and C4 is reduced by applying the high frequency voltage, and as a result, only the DC bias voltage is applied as the capacitance value. Increased compared to the state that has been. Thus, even if the absolute values of the DC bias voltages are equal, the capacitances of the variable capacitance elements C1, C2, C3, and C4 are different if their polarities are different. 2 shows the applied voltage dependence of the capacitance change rate of the variable capacitance elements C1, C2, C3, C4. Therefore, the capacitance change amount of the variable capacitance elements C1, C2, C3, C4 is the variable capacitance. It depends on the individual capacitances of the elements C1, C2, C3 and C4.

  Here, in the variable capacitor Ct, the first bias lines B11 and B12 having a high potential are connected to the input terminal I side of the variable capacitor group A, and the variable capacitor group B has a first bias having a high potential. Since the lines B12 and B13 are connected to the output terminal O side, the first bias terminal V1 has a positive potential and the second bias terminal V2 has a negative potential. A positive DC bias voltage is applied to the capacitive element group A, and a negative DC bias voltage is applied to the variable capacitive element group B. For this reason, in the variable capacitance element group A, the bias voltage increases, and the total capacitance value decreases from C to C−ΔC. On the other hand, in the variable capacitance element group B, the bias voltage decreases, and the total capacitance value increases from x × C to x × (C + ΔC). Conversely, when the phase of the high-frequency signal is a negative potential, the total value of the capacitance values of the variable capacitance element group A is C + ΔC, and the total value of the capacitance values of the variable capacitance element group B is x × (C−ΔC).

    Here, ΔC represents a capacitance change amount of the variable capacitance element group A due to the high frequency signal with reference to the total value C of the capacitance values of the variable capacitance element group A. As shown in FIG. 2, the applied voltage dependence of the capacitance change rate of the variable capacitance elements C1 to C4 is not a linear function relationship between the positive and negative applied voltages. Therefore, strictly speaking, the absolute value of the capacitance change amount ΔC due to the high-frequency voltage is not equal when the DC bias voltage is a positive voltage and when the DC bias voltage is a negative voltage, but can be regarded as being substantially expressed by a linear function. It was supposed to be. FIG. 12 shows the variable capacitance elements C1, C2, C3, and C4 when a high frequency voltage of 1 MHz to 3 GHz is applied to the variable capacitance elements C1, C2, C3, and C4 with a DC bias voltage applied. It is the graph (diagram) which showed the frequency dependence of the capacity | capacitance change with the specific numerical value (measured value). FIG. 13 is a graph (diagram) showing the applied voltage dependence of the capacitance change of the variable capacitance elements C1, C2, C3, C4 at the high frequency voltage of 2 GHz in FIG. is there.

Here, the total value C of the capacitance values of the variable capacitance element group A when the DC bias voltage is applied is 2.5 pF, and the capacitance change ΔC of the variable capacitance element group A due to the high frequency signal is represented by the variable capacitance element group A when the DC bias voltage is applied. The total capacitance value C of the variable capacitance element group A and the total capacitance value xx of the variable capacitance element group B when a DC bias voltage is applied is 0.625 pF, which is 25% of the total capacitance value C of The combined capacitance value of C, that is, the capacitance value C _T when the DC bias voltage is applied to the variable capacitor Ct, the capacitance value of the variable capacitor Ct when a high frequency signal is applied superimposed on the DC bias voltage, capacitance value when the phase is negative potential of the capacitance value C _{T +} and a high-frequency signal when the phase is positive potential C _T -, a variable capacitor due to the added high-frequency signal is superimposed on the DC bias voltage ratio _{C T +} / _C T of the change in the capacitance value of _t, C T - the result / _{C T} was calculated in Table 1.

As can be seen from Table 1, when x = 1.0, that is, when the capacitance values of the variable capacitive element group A and the variable capacitive element group B are equal, the variable when the high frequency signal is applied superimposed on the DC bias voltage. The capacitance value C _T + and C _T − of the capacitance capacitor Ct are equal. However, as x increases, that is, as the difference in capacitance value between the variable capacitance element group A and the variable capacitance element group B increases, the difference between the capacitance values C _T + and C _T − due to the difference in phase of the high-frequency signal. When x = 1.6, the difference in change rate with respect to the capacitance value C of the variable capacitor Ct is a difference of 10%. As described above, when the variable capacitance element group A and the variable capacitance element group B have different capacitance values, the variable capacitance capacitor Ct behaves as a capacitor having a different capacitance with respect to the phase of the high frequency signal. In this case, waveform distortion intermodulation distortion is generated for a high-frequency signal. Accordingly, by setting the total value of the capacitance values of the variable capacitance element group A and the total value of the capacitance values of the variable capacitance element group B to be substantially the same, waveform distortion and intermodulation distortion can be suppressed in the high frequency electronic component. it can.

  Further, since the number of variable capacitance elements is an even number (here, four), the application of the bias signal does not change even if a high frequency signal is applied from either of the signal terminals I and O as shown in FIG. In other words, although the direction of the DC bias voltage applied to each variable capacitance element is alternately different, since the number of variable capacitance elements is an even number, the influence of the difference in the direction of the DC bias voltage between adjacent variable capacitance elements can be offset. As a result, the polarity with respect to the bias signal does not occur, and as a result, it is not necessary to pay attention to the polarity when mounting as a variable capacitor and the handling becomes easy.

  Further, when the variable capacitive elements C1 and C3 of the variable capacitive element group A and the variable capacitive elements C2 and C4 of the variable capacitive element group B form a pair having substantially the same capacitance value, for example, the variable capacitive element group The capacitance value of the variable capacitor C1 of A is 4 pF, the capacitance of the variable capacitor C3 is 2 pF, the capacitance of the variable capacitor C2 of the variable capacitor group B is 2 pF, and the capacitance of the variable capacitor C4 is 4 pF. Thus, the same number of variable capacitance elements having the same capacitance value are included in each variable capacitance element group. In such a variable capacitor Ct, even if the capacitance of each variable capacitor varies with respect to the high frequency voltage applied superimposed on the DC bias voltage, the variable capacitor group A and the variable capacitor group B are Since DC bias voltages having different polarities are applied, the variable capacitance element group A and variable capacitance element group B can be varied by canceling capacitance fluctuations between the variable amount elements that are paired with substantially equal capacitance values. The variation of the capacitance value due to the high frequency signal of the entire capacitor Ct being superimposed on the bias voltage can be further reduced, and as a result, the waveform distortion and intermodulation distortion with respect to the high frequency signal can be reduced in the high frequency electronic component. it can.

  Further, when the capacitance values of the variable capacitance elements C1, C2, C3, and C4 are substantially equal, for example, when all the capacitance values are 2.6 pF, the absolute value of the capacitance change amount in all the variable capacitance elements. Are substantially equal to each other, so that the capacitance variation between the arbitrary variable capacitance elements of the variable capacitance element group A and the arbitrary variable capacitance elements of the variable capacitance element group B cancels each other. It is possible to further reduce the fluctuation of the capacitance value due to being superimposed on the bias voltage, and as a result, it is possible to reduce waveform distortion and intermodulation distortion with respect to the high frequency signal in the high frequency electronic component.

  4 (a) and 4 (b), which are equivalent circuit diagrams, have the same configuration as the variable capacitor Ct shown in FIG. 1, and an odd number of variable capacitors (five in this figure). It is good. In this figure, the same parts as those in FIG. 1 are denoted by the same reference numerals, and redundant description thereof will be omitted.

  In FIG. 4, first bias lines B11, B12, B13 and second bias lines B21, B22, B23 are provided in order to apply a DC bias voltage to the individual variable capacitance elements C1 to C5. In such a variable capacitor Ct ′, the signal terminals I and O and the first and second bias terminals V1 and V2 can be separated as shown in FIG. 4A, as shown in FIG. 4B. In addition, the first bias voltage V1 can be used in common with the input terminal I, and the second bias voltage V2 can be used in common with the output terminal O, and can be handled in the same manner as a general capacitor. As a result, it is possible to increase the degree of freedom in mounting, pattern design, etc., and to make the variable capacitor Ct ′ easy to handle.

  In the variable capacitors Ct and Ct ′, the variable capacitance element C1 connected to the input terminal I and the variable capacitance element C4 or C5 connected to the output terminal O have larger capacitance values than other variable capacitance elements. Is preferred. This is because, compared with the stray capacitance value generated between the input terminal I and the variable capacitance element C1 connected to the input terminal I and between the output terminal O and the variable capacitance element C4 or C5 connected to the output terminal O, the input By increasing the capacitance value of the variable capacitor C1 connected to the terminal I and the variable capacitor C4 or C5 connected to the output terminal O, the influence of stray capacitance can be suppressed, and the variable capacitors Ct, Ct The variation in the capacitance value of 'is small.

  Next, an example of a method for producing the variable capacitor Ct of the present invention will be described.

  FIG. 5 is a transparent plan view showing an example of a variable capacitor Ct having four variable capacitors C1 to C4 with respect to the variable capacitor Ct of the present invention. FIG. 6 is a plan view of the variable capacitor Ct shown in FIG. It is AA 'line sectional drawing.

  5 and 6, 1 is a support substrate, 2 is a lower electrode layer, 31, 32 and 33 are conductor lines, 4 is a thin film dielectric layer, 5 is an upper electrode layer, 61, 62, 63, 64 and 65 are Thin film resistors, 7 is an insulating layer, 8 is a lead electrode layer, 9 is a protective layer, 10 is a solder diffusion preventing layer, and 111, 112 and 113, 114 are solder terminal portions. The solder diffusion preventing layer 10 and the solder terminal portions 111 and 112 constitute a first signal terminal (input terminal) I and a second signal terminal (output terminal) O, respectively. The solder diffusion preventing layer 10 and the solder terminal portions 114 and 113 constitute a first bias terminal V1 and a second bias terminal V2, respectively.

  The support substrate 1 is a ceramic substrate such as alumina ceramic, a single crystal substrate such as sapphire, or the like. On the support substrate 1, a lower electrode layer 2, a thin film dielectric layer 4 and an upper electrode layer 5 are sequentially formed on almost the entire surface of the support substrate 1. After the formation of these layers, the upper electrode layer 5, the thin film dielectric layer 4 and the lower electrode layer 2 are sequentially etched into a predetermined shape.

  When forming the lower electrode layer 2, the thin film dielectric layer 4, and the upper electrode layer 5, between the lower electrode layer 2 and the thin film dielectric layer 4 and between the thin film dielectric layer 4 and the upper electrode layer 5. In addition, it is desirable to minimize the contamination of impurities such as particles that can cause the characteristics of the variable capacitor to deteriorate. Therefore, it is desirable that the lower electrode layer 2, the thin film dielectric layer 4 and the upper electrode layer 5 are continuously formed by the same film forming apparatus without opening the film forming chamber to the atmosphere. For this reason, sputtering is suitable as a specific film forming method.

  The lower electrode layer 2 needs to have a high melting point so that it can withstand the high temperature because high temperature sputtering is required for forming the thin film dielectric layer 4. Specifically, it is made of a metal material such as Pt or Pd. This lower electrode layer 2 is also formed by high temperature sputtering. Furthermore, the lower electrode layer 2 is flattened by being heated to 700 to 900 ° C. which is the sputtering temperature of the thin film dielectric layer 4 after being formed by high-temperature sputtering, and kept for a certain time until the sputtering of the thin film dielectric layer 4 is started. Become a layer.

  The thickness of the lower electrode layer 2 is determined in consideration of the resistance component from the variable capacitance element C1 to the variable capacitance element C2, the resistance component from the variable capacitance element C3 to the variable capacitance element C4, and the continuity of the lower electrode layer 2. The thicker one is desirable, but when considering the adhesiveness with the support substrate 1, the relatively thinner one is desirable, and both are determined. Specifically, it is 0.1 μm to 10 μm. If the thickness of the lower electrode layer 2 is less than 0.1 μm, the resistance of the lower electrode layer 2 itself increases and the continuity of the lower electrode layer 2 may not be ensured. On the other hand, if the thickness is greater than 10 μm, the internal stress increases, and the adhesion to the support substrate 1 may be reduced, or the support substrate 1 may be warped.

The thin film dielectric layer 4 is preferably a high dielectric constant dielectric layer made of a perovskite oxide crystal containing at least Ba, Sr, and Ti. For example, at least Ba, Sr, as the perovskite type oxide crystal containing Ti, barium strontium titanate _{((Ba x Sr 1-x} ) TiO 3), Mn in barium strontium titanate, Mg, La, W, and the like Some are doped. The thin film dielectric layer 4 is formed on the surface (upper surface) of the lower electrode layer 2. For example, using a dielectric material from which a perovskite oxide crystal can be obtained as a target, film formation by sputtering is performed until a desired thickness is obtained. At this time, by performing high-temperature sputtering at a high substrate temperature, for example, 800 ° C., a low-loss thin-film dielectric layer 4 having a high dielectric constant and a large capacitance change rate can be obtained without performing heat treatment after sputtering. it can.

  As the material of the upper electrode layer 5, Au having a low resistivity is desirable in order to reduce the resistance of this layer. However, in order to improve the adhesion with the thin film dielectric layer 4, it is preferable to use Pt or the like as the adhesion layer. desirable. The thickness of the upper electrode layer 5 is 0.1 μm to 10 μm. The lower limit of the thickness is set in consideration of the resistance and continuity of the upper electrode layer 5 itself, similarly to the lower electrode layer 2. Further, the upper limit of the thickness is set in consideration of the adhesion with the thin film dielectric layer 4.

  After film formation as described above, the upper electrode layer 5, the thin film dielectric layer 4 and the lower electrode layer 2 are sequentially etched into a predetermined shape. Etching is performed by wet etching or dry etching after uniformly applying a resist on the entire surface by spin coating or the like, patterning the resist into a predetermined shape by photolithography. Since the capacitance values of the variable capacitance elements C1 to C4 are determined by the area of the upper electrode layer 5, it is desirable to use dry etching with higher accuracy in the etching of the upper electrode layer 5.

  The dry etching can be performed using, for example, an electron cyclotron resonance apparatus (ECR apparatus) and argon plasma as an etchant.

  The thin film dielectric layer 4 may be etched by either wet etching or dry etching.

  The lower electrode layer 2 may be etched by either wet etching or dry etching. However, when the lower electrode layer 2 is thick, dry etching is performed in the same manner as the upper electrode layer 5 from the viewpoint of patterning accuracy. It is desirable to carry out by etching.

  In the etching of the upper electrode layer 5, the thin film dielectric layer 4 and the lower electrode layer 2 as described above, the lower surface of the thin film dielectric layer 4 is smaller than the upper surface of the lower electrode layer 2, and the lower surface of the upper electrode layer 5 is a thin film dielectric. Etching is performed to be smaller than the upper surface of the body layer 4. As a result, the thin-film dielectric layer 4 is not present at the outer edge portion of the lower electrode layer 2 where the electric field tends to concentrate, so that the leakage current characteristics are improved.

  In this way, variable capacitance elements C1 to C4 can be obtained.

  Here, in order to electrically connect between the first signal terminal I and the variable capacitance element C1 and between the variable capacitance element C4 and the second signal terminal O, the first and second signals on the support substrate 1 are used. It is desirable to form a conductive layer made of a conductive material at a position where the terminals I and O are formed. This conductive layer may be formed by forming a new film after forming the variable capacitors C1 to C4. However, when the lower electrode layer 2 is patterned, patterning is performed so that these conductive layers are also formed at the same time. By performing, the same material and the same process as the lower electrode layer 2 may be used.

  The first bias lines B11, B12, and B13 are composed of conductor lines 32 and 33 and thin film resistors 61, 62, and 63, and the connection from the first bias terminal V1 to the first signal terminal I and the variable capacitance element C1. Between the connection points of the variable capacitance element C2 and the variable capacitance element C3, that is, between the upper electrode layer 5 of the variable capacitance element C2 and the extraction electrode layer 8 connecting the upper electrode layer 5 of the variable capacitance element C3. Between the variable capacitance element C4 and the second signal terminal O, and is connected to an external circuit via the first bias terminal V1.

  The second bias lines B21 and B22 are composed of the conductor line 31 and the thin film resistors 64 and 65, and between the connection point between the variable capacitance element C2 and the variable capacitance element C3 from the second bias terminal V2, that is, the variable capacitance. Between the lower electrode layer 2 shared by the element C2 and the variable capacitive element C3 and between the connection points of the variable capacitive element C3 and the variable capacitive element C4, that is, the lower part shared by the variable capacitive element C2 and the variable capacitive element C3. They are respectively provided between the electrode layers 2 and connected to an external circuit via a second bias terminal V2.

  By providing the first and second bias lines B11, B12, B13 and B21, B22 having such a configuration, the variable capacitance elements C1 to C4 have the first and second bias lines B11, B12, B13 and B21, B22. Are connected in parallel.

  The conductor lines 31, 32, and 33 can be formed by forming a new film after the lower electrode layer 2, the thin film dielectric layer 4 and the upper electrode layer 5 are formed. In this case, it is desirable to use a lift-off method in order to protect the already formed lower electrode layer 2, thin film dielectric layer 4 and upper electrode layer 5. The conductor lines 31 to 33 can also be formed by patterning so that the conductor lines 31 to 33 are formed at the same time when the lower electrode layer 2 is patterned.

  As a material for the conductor lines 31 to 33, in order to suppress variation in resistance values of the first and second bias lines B11, B12, B13, B21, and B22, Au having a low resistance is desirable. , 62, 63, 64, 65 are sufficiently high, and may be formed using the same material and the same process as the lower electrode layer 2 using Pt or the like.

  Here, in order to facilitate the formation of the first and second bias terminals V1 and V2 at the positions where the first and second bias terminals V1 and V2 are formed on the support substrate 1, the conductor line 31 and the conductor line 32 are respectively formed. It is desirable to form an electrically connected conductive layer made of a conductive material. The conductive layer may be formed by forming a film after forming the variable capacitors C1 to C4. However, when the conductor lines 31 to 33 are formed, the first and second conductor lines 31, 32 are formed. By forming the shape of the bias terminals V1 and V2 in accordance with the shapes of the first and second bias terminals V1 and V2, and performing patterning so that these conductive layers are also formed at the same time. The conductor lines 31 to 33 may be formed using the same material and the same process.

  Note that the first and second bias terminals V1 and V2 are arranged symmetrically with respect to the center of the variable capacitor Ct of the present invention, so that the variable capacitor Ct can be moved up and down in the plan view shown in FIG. Even if it is reversed, since it can be mounted on a wiring board, handling becomes easy.

  Next, the material of the thin film resistors 61 to 65 constituting the first and second bias lines B11, B12, B13, B21, B22 contains tantalum (Ta) and has a specific resistance of 1 mΩ · cm or more. Some are desirable. Specific resistance ρ obtained from R = ρ · l / (w · t) (R: resistance of thin film resistor, l: length of thin film resistor, w: width of thin film resistor, t: film thickness of thin film resistor) is 1 mΩ. When the thickness is smaller than cm, it is necessary to reduce the film thickness t, and disconnection is likely to occur. In addition, the thin film resistors 61 to 65 need to increase the aspect ratio (length 1 / width w) to increase the length, but if the aspect ratio is too large, the element shape of the variable capacitor increases. It is possible to prevent the aspect ratio from becoming too large by setting the specific resistance to 1 mΩ · cm or more. On the other hand, if the specific resistance becomes too large, the temperature characteristics and reproducibility of the thin film resistors 61 to 65 are likely to deteriorate, and therefore the upper limit of the specific resistance is determined in consideration of both characteristics. For example, when the resistance value of the bias line is 10 kΩ, the specific resistance is 1 mΩ · cm or more, and when the film thickness is 50 nm, the aspect ratio is 50 or less, which can be realized without increasing the element shape of the variable capacitor. Aspect ratio. Specific examples of the thin film resistors 61 to 65 include tantalum nitride (TaN), TaSiN, and Ta—Si—O. For example, in the case of tantalum nitride, thin film resistors 61 to 65 having a desired composition ratio and resistivity can be formed by a reactive sputtering method in which sputtering is performed by adding Ta to the atmosphere using Ta as a target. it can.

  By appropriately selecting the sputtering conditions, thin film resistors 61 to 65 having a film thickness of 40 nm or more and a specific resistance of 1 mΩ · cm or more can be formed. Furthermore, after the sputtering is completed, a resist is applied and processed into a predetermined shape, and then patterning can be easily performed by performing an etching process such as reactive ion etching (RIE) using this as a mask.

  The resistance values of the first and second bias lines B11, B12, B13, B21, and B22 are such that the impedances of the first and second bias lines B11, B12, B13, B21, and B22 are variable capacitance elements C1 in the frequency range to be used. It is set to be larger than the impedance of .about.C4. Since the resistance values of the conductor lines 31 to 33 are very small compared to the resistance values of the thin film resistors 61 to 65, the resistance values of the first and second bias lines B11, B12, B13, B21 and B22 are the thin film resistors 61. It is almost equal to the resistance value of ~ 65. Accordingly, the resistance values of the thin film resistors 61 to 65 are set to be larger than the impedances of the variable capacitance elements C1 to C4 in the frequency region to be used. For example, when the variable capacitor Ct is used at a frequency of 1 GHz and the capacitances of the variable capacitors C1 to C4 are set to 5 pF, the impedance is not adversely affected from 1/10 (100 MHz) of this frequency. The thin film resistors 61 to 65 are variable so that the signal component in the frequency domain leaks to the first and second bias lines B11, B12, B13, B21, and B22 and does not affect the impedances of the variable capacitance elements C1 to C4. If the resistance value of the capacitive elements C1 to C4 is set to a resistance value of 10 times or more of the impedance at 100 MHz, the required resistance value of the first and second bias lines B11, B12, B13, B21, B22 is about 3.2 kΩ. That's it. If the specific resistance of the thin film resistors 61 to 65 in the variable capacitor is 1 mΩ · cm or more and the resistance value of the first and second bias lines B11, B12, B13, B21, B22 is 10 kΩ, the thin film resistors Since the aspect ratio (length / width) of 61 to 65 can be 50 or less when the film thickness is 50 nm, the thin film resistors 61 to 65 have an aspect ratio that can be realized without increasing the element shape.

  The first and second bias lines B11, B12, B13, B21, and B22 including these thin film resistors 61 to 65 are directly formed on the support substrate 1. This eliminates the need for an insulating layer for securing insulation from the lower electrode layer 2, the upper electrode layer 4, and the extraction electrode layer 8, which is necessary when forming on the variable capacitance elements C <b> 1 to C <b> 4. It becomes possible to reduce the number of layers constituting C1 to C4. Furthermore, by using the high-resistance thin film resistors 61 to 65, the variable capacitor Ct can be manufactured without increasing the shape.

  Next, the insulating layer 7 is necessary for ensuring insulation between the lead electrode layer 8 and the lower electrode layer 2 formed thereon. Further, since the insulating layer 7 covers the first and second bias lines B11, B12, B13, B21, and B22, the thin film resistors 61 to 65 can be prevented from being oxidized. The resistance values of the bias lines B11, B12, B13, B21, and B22 can be made constant over time, thereby improving the reliability. The material of the insulating layer 7 is preferably made of at least one of silicon nitride and silicon oxide in order to improve moisture resistance. These films are preferably formed by a chemical vapor deposition (CVD) method or the like in consideration of coverage.

  The insulating layer 7 can be processed into a desired shape by a dry etching method using a normal resist. The insulating layer 7 is provided with a through hole reaching the conductor line 33 in order to ensure the connection between the thin film resistors 61 to 65 and the lead electrode layer 8. In addition, it is preferable that only the upper electrode layer 4 and the solder terminal portions 111, 112, 113, and 114 are exposed from the insulating layer 7 from the viewpoint of improving moisture resistance.

  Next, the lead electrode layer 8 is provided between the upper electrode layer 5 of the first variable capacitance element C1 and the first signal terminal I, that is, the conductive layer of the first signal terminal I forming portion, and between the variable capacitance element C2 and the variable capacitance. The insulating layer 7 penetrates between the upper electrode layer 5 of the element C3 and between the upper electrode layer 5 of the variable capacitor C4 and the second signal terminal O, that is, the conductive layer of the second signal terminal O forming portion. Each is connected through a hole. By forming the lead electrode layer 8 in this way, the variable capacitance elements C1 to C4 are connected in series from the first signal terminal I to the second signal terminal O in order. Further, the lead electrode layer 8 extending over the variable capacitance elements C2 and C3 is connected to the conductor line 33 through the through hole of the insulating layer 7. As the material of the extraction electrode layer 8, it is desirable to use a low resistance metal such as Au or Cu. In consideration of adhesion between the lead electrode layer 8 and the insulating layer 7, an adhesion layer such as Ti or Ni may be used.

  When the extraction electrode layer 8 is formed, a layer made of a material constituting the extraction electrode layer 8 is formed at the positions where the first and second signal terminals I and O and the first and second bias terminals V1 and V2 are formed. Preferably formed. This is because mounting is facilitated by aligning the heights of the positions where the first and second signal terminals I and O and the first and second bias terminals V1 and V2 are formed.

  Next, the protective layer 9 is formed so that the solder terminal portions 111, 112, 113, and 114 are exposed and covered entirely. The protective layer 9 is used to mechanically protect the constituent members of the variable capacitor Ct including the variable capacitor C1 and to protect it from contamination by chemicals and the like. However, when the protective layer 9 is formed, the solder terminal portions 111, 112, 113, 114 are exposed. As a material of the protective layer 9, a material having high heat resistance and excellent coverage with respect to a step is preferable. Specifically, polyimide resin, BCB (benzocyclobutene) resin, or the like is used. These are formed by applying a resin material and then curing at a predetermined temperature.

  The solder diffusion preventing layer 10 is formed by the solder of the solder terminal portions 111, 112, 113, 114 when the solder terminal portions 111, 112, 113, 114 are reflowed or mounted. Formed in order to prevent diffusion into. As a material of the solder diffusion preventing layer 10, Ni is suitable. In addition, in order to improve solder wettability, Au, Cu, etc. having high solder wettability may be formed on the surface of the solder diffusion preventing layer 10 to about 0.1 μm.

  Finally, solder terminal portions 111, 112, 113, 114 are formed on the solder diffusion preventing layer 10. This is formed to facilitate mounting of the variable capacitor on the external wiring board. These solder terminal portions 111, 112, 113, 114 are generally formed by reflowing after solder paste is printed on the solder terminal portions 111, 112, 113, 114 using a predetermined mask.

  According to the above-described variable capacitor Ct, the first and second bias lines B11, B12, B13, B21, B22 or a part thereof contain tantalum nitride and have a specific resistance of 1 mΩ · cm or more. By using 61 to 65, the aspect ratio of the thin film resistors 61 to 65 is reduced, and the size of the variable capacitor Ct is reduced. Furthermore, by forming the first and second bias lines B11, B12, B13, B21, and B22 directly on the support substrate 1, the number of layers constituting each element such as the variable capacitance element C1 is reduced. . Further, since the formation process of each conductor layer, dielectric layer, etc. constituting each element can be made common, it can be formed very easily despite the relatively complicated structure.

  Next, a manufacturing method of the variable capacitor Ct ′ of the present invention will be described.

  7 is a transparent plan view showing an example of the variable capacitor Ct ′ of the present invention having five variable capacitors C1 to C5, and FIG. 8 is an AA ′ diagram of the variable capacitor Ct ′ shown in FIG. It is line sectional drawing. In these drawings, the same parts as those in FIGS. 5 and 6 are denoted by the same reference numerals, and redundant description thereof will be omitted.

  7 and 8, C5 is a variable capacitance element, and is formed between the variable capacitance element C4 and the second signal terminal O in the same material and in the same process as the variable capacitance elements C1 to C4.

  34 is a conductor line, 66 is a thin film resistor, the first bias line B13 constituting the bias supply circuit is composed of the conductor line 34 and the thin film resistor 63, and the second bias line B23 is the conductor line 31. And a thin film resistor 66.

  The first bias line B13 and the second bias line B23 are formed of the same material and in the same process as the first bias lines B11 and B12 and the second bias lines B21 and B22.

  The insulating layer 7 is provided with through holes reaching the conductor lines 33 and 34 in order to ensure the connection between the thin film resistor 61 and the lead electrode layer 8.

  In order to directly connect the variable capacitance elements C1 to C5 from the first signal terminal I to the second signal terminal O, for example, the lead electrode layer 8 is connected to the first signal terminal I and the upper electrode layer 4 of the variable capacitance element C1. Are electrically connected to each other by sharing the lower electrode layer 2 between the variable capacitance elements C1 and C2, and the upper electrode layer 4 of the variable capacitance elements C2 and C3 is connected via the lead electrode layer 8 In the same manner, the lower electrode layer 2 is shared between the variable capacitor elements C3 and C4, and the upper electrode layer 4 of the variable capacitor elements C4 and C5 is connected to the lower electrode layer via the lead electrode layer 8. The electrode layer 2 may be shared and the variable capacitance element C5 and the second signal terminal O may be electrically connected to each other.

  According to the variable capacitor Ct ′ described above, the bias terminal that supplies a bias signal to which the input terminal I and the output terminal O, which are signal terminals for supplying a high-frequency signal, and the first and second bias lines are connected. V1 and V2 can be made common, and as a result, the degree of freedom of mounting and pattern design can be increased, and the variable capacitor Ct ′ can be easily handled.

  Next, the circuit module and communication device of the present invention will be described.

  The circuit module of the present invention is configured as a resonant circuit including the variable capacitor of the present invention, at least one of an inductor and a resistor, and a voltage supply unit that can apply a voltage to these. Since the variable capacitor according to the present invention is used as a capacitor constituting a resonance circuit, the capacitance change rate of the capacitor is large and a desired capacitance can be obtained with high accuracy. Thus, a desired resonance frequency can be obtained with high accuracy. In addition, since the capacitor has excellent power resistance, the capacitor is highly reliable, can be easily manufactured, and has high productivity. Further, when the variable capacitance element is an even number, it is easy to handle because it does not depend on the polarity of the DC bias voltage.

  Further, the communication device of the present invention has a configuration using the circuit module having the above configuration as a filter means. For example, the communication device of the present invention can be obtained by providing such filter means in the transmission circuit and the reception circuit, respectively, and connecting the transmission circuit and the reception circuit via a transmission / reception switching device. Such a filter means includes, for example, a band-pass filter that can be obtained by combining the above circuit module, an inductor, a capacitor, and the like, and a desired resonance frequency can be set accurately over a wide frequency range. The range is wide and a desired pass band can be obtained with high accuracy. As described above, according to the communication device of the present invention, a desired resonance frequency can be accurately set over a wide frequency range, so that a frequency range that can be used as a filter means is wide and a desired filter function can be obtained with high accuracy. It will be possible.

  In addition, this invention is not limited to the example of the above embodiment, A various change may be added in the range which does not deviate from the summary of this invention. For example, in the above-described embodiment, the first bias lines B11, B12, B13 and the second bias lines B21, B22, which are bias supply circuits, are shared, but the bias lines B11, B12, B13, B21, The variable capacitor Ct may be configured such that B22 is provided individually for each of the variable capacitance elements C1, C2, C3, and C4. Further, a bias voltage V1 may be applied from the input terminal I as shown in FIG.

  Moreover, the variable capacitor of the present invention comprising variable capacitors connected in series to a plurality of regions on the support substrate 1 may be formed, or the first and second bias lines may be formed of inductors or transmission lines. .

It is an equivalent circuit diagram showing an example of an embodiment of a variable capacitor of the present invention. It is a diagram which shows the example of the direct current bias voltage characteristic of the capacity | capacitance change rate in the 1st variable capacitor of this invention. (A), (b) is a conceptual diagram which shows the connection structure of the variable capacitance element when it sees in high frequency in the 1st variable capacitance capacitor of this invention, respectively. (A), (b) is an equivalent circuit diagram which shows the other example of embodiment of the variable capacitor of this invention, respectively. It is a top view of the see-through state which shows the example of the variable capacitor shown in FIG. FIG. 6 is a cross-sectional view taken along line A-A ′ of FIG. 5. It is a top view of the see-through state which shows the example of the variable capacitor shown in FIG. FIG. 8 is a cross-sectional view taken along line A-A ′ of FIG. 7. It is an equivalent circuit diagram which shows the other example of embodiment of the variable capacitor of this invention which provided the bias supply circuit separately. It is sectional drawing which shows the example of the conventional thin film capacitor. (A) And (b) is an equivalent circuit diagram of the conventional variable capacitor, respectively. It is a diagram which shows the frequency dependence of a capacity | capacitance when the DC bias voltage of various values is applied to the variable capacity element. FIG. 6 is a diagram showing specific numerical values of applied voltage dependence of capacitance change of a variable capacitance element when a high frequency voltage of 2 GHz is applied in a state where a DC bias voltage is applied to the variable capacitance element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Support substrate 2 ... Lower electrode layer
31, 32, 33, 34 ... conductor lines 4 ... thin film dielectric layer 5 ... upper electrode layer
61, 62, 63, 64, 65 ... Thin film resistor 7 ... Insulating layer 8 ... Lead electrode layer 9 ... Protective layer
10 ... Solder diffusion prevention layer
111, 112 ... solder terminal portion C1, C2, C3, C4, C5 ... variable capacitance element Ct ... variable capacitance capacitor B11, B12, B13 ... first bias line B21, B22, B23 ..・ Second bias line I ・ ・ ・ Input terminal O ・ ・ ・ Output terminal L1, L2 ・ ・ ・ Inductor R11, R12, R13, R21, R22, R23 ・ ・ ・ Resistance component V1 ・ ・ ・ First bias terminal V2 ・..Second bias terminal

Claims (9)

A plurality of variable capacitance elements using a thin film dielectric layer whose dielectric constant varies depending on the applied voltage are connected in series between the input terminal and the output terminal of the high-frequency signal, and a first bias on the high potential side of the applied voltage. A variable capacitance capacitor, wherein a line and a second bias line on a low potential side are alternately connected to both ends of each of the plurality of variable capacitance elements and between each element. Among the plurality of variable capacitance elements, a total value of capacitance values of the variable capacitance element group A in which the first bias line is connected to the input terminal side and a variable in which the first bias line is connected to the output terminal side. 2. The variable capacitor according to claim 1, wherein a total value of capacitance values of the capacitive element group B is substantially equal. The variable capacitor according to claim 2, wherein the variable capacitor is an even number. 4. The variable capacitance capacitor according to claim 3, wherein the variable capacitance element of the variable capacitance element group A and the variable capacitance element of the variable capacitance element group B form a pair of substantially equal capacitance values. . 4. The variable capacitor according to claim 3, wherein capacitance values of the plurality of variable capacitance elements are substantially equal. The variable capacitor according to claim 2, wherein the variable capacitor is an odd number. 5. The variable capacitance element connected to the input terminal and the variable capacitance element connected to the output terminal have larger capacitance values than the other variable capacitance elements. The variable capacitor according to claim 6. 8. A circuit module, wherein the variable capacitor according to claim 1 is used as a capacitor constituting a resonance circuit. 9. A communication apparatus, wherein the circuit module according to claim 8 is used as filter means.

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