JP2008277996A - Variable capacitance capacitor, filter circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a variable capacitance capacitor which can easily control the characteristics, and to provide a filter circuit. <P>SOLUTION: The variable capacitance capacitor includes a variable capacitance element group, comprising a plurality of variable capacitance elements connected in series between a first signal terminal and a second signal terminal, bias lines connected between the variable capacitance elements and to both sides of the variable capacitance element group; a first bias terminal to which at least one of the bias lines is connected; and a second bias terminal, to which at least different one of the bias lines from the bias line is connected, the two bias lines connected to both the sides of the variable capacitance element group which are each connected to the first or the second bias terminal, and at least one of the bias lines connected between the plurality of variable capacitance elements being connected to the first or the second bias terminal is to be connected or not. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention is used in communication devices and electronic parts such as microwave band and millimeter wave band, and has a dielectric layer whose relative dielectric constant changes depending on an applied voltage, and a variable capacitance capacitor capable of changing capacitance, The present invention relates to a voltage control type filter circuit whose filter characteristics can be varied by changing its capacitance value, and particularly relates to a filter circuit that can easily perform voltage control.

  2. Description of the Related Art A filter circuit that is configured using a variable capacitor and that changes filter characteristics by changing the capacitance of the capacitor is known.

  FIG. 6 is an equivalent circuit diagram showing an example of a conventional filter circuit, and shows a filter circuit having two parallel LC resonators.

  In FIG. 6, D1 and D2 are M resonance (magnetic field coupling) LC resonance circuits. Examples of the plurality of LC resonance circuits D1 and D2 include a 1/4 wavelength tip short-circuited dielectric resonator. Variable capacitance capacitors Ct2 and Ct4 are respectively connected in parallel to the LC resonance circuits D1 and D2 via a direct current limiting capacitor (fixed capacitance element) Cd to form an LC resonance unit. Further, RF blocking inductors Lb2 and Lb4 for supplying a control voltage are connected to the variable capacitors Ct2 and Ct4, respectively. As a result, the control voltage is applied from the bias terminal V2 to the variable capacitors Ct2 and Ct4 and flows to the reference potential (ground potential in the figure). Here, the DC limiting capacitor Cd is normally set so as not to affect the impedance of the variable capacitors Ct2 and Ct4 in the case of a high frequency signal. The LC parallel resonance circuits D1 and D2 are coupled via a variable capacitor Ct3 serving as a coupling capacitor and a DC limiting capacitor Cd. Further, the LC parallel resonant circuits D1 and D2 include a variable capacitor Ct1 and a DC limiting capacitor Cd, a variable capacitor as input / output capacitance components between the input signal terminal I and the output signal terminal O for coupling an external circuit. It is connected via Ct5 and a direct current limiting capacitor Cd. Thus, a filter circuit is configured. In order to adjust the capacitances of the variable capacitors Ct1, Ct3, and Ct5, bias terminals V1, V3, and V1 are connected via RF blocking inductors Lb1, Lb3, and Lb5, respectively.

As the variable capacitor, a ferroelectric oxide thin film having a perovskite structure such as strontium titanate or strontium barium titanate is used as a dielectric layer, and the gap is sandwiched between the upper electrode layer and the lower electrode layer. A structure is known in which a capacitance is changed by changing a relative dielectric constant of a dielectric layer by applying a predetermined control voltage (see, for example, Patent Document 1).
JP-A-11-260667

  However, in order to actually obtain desired filter characteristics in a filter using a conventional variable capacitor, different capacitance change rates are required for the plurality of variable capacitors. For example, in the example of the symmetrical voltage controlled capacitance variable filter shown in the equivalent circuit diagram of FIG. 6, the pass band is mainly set by the variable capacitors Ct2 and Ct4, the stop band is set by the variable capacitor Ct3, and the input / output impedance is set. Adjustment is made by changing the capacitances of the variable capacitors Ct1 and Ct5.

  Here, the capacity change rate with respect to a constant applied voltage is ΔC / C = | C−C ′ | / C (C: initial capacity value, C ′: capacity value when applied voltage, C−C ′: capacity change amount) In the example shown in FIG. 6, for example, in order to support two communication systems of the K-PCS band (1750 MHz band) and the US-PCS band (1850 MHz), a variable capacitor is provided for each of the two communication systems. The desired filter characteristics are obtained by adjusting the capacitance values of Ct1 to Ct5.

  Further, in one communication system, Ct2 and Ct4 form resonant circuits together with D1 and D2, respectively, mainly changing the passband, and Ct3 changes the stopband together with coupling with D1 and D2, and Ct1, Ct5 Since the input / output impedance is mainly changed, the capacitance change rates of the variable capacitors Ct1 to Ct5 necessary for the respective purposes are different. Therefore, the capacitance change rates necessary for the variable capacitors Ct1 to Ct5 are the capacitance change rates ΔCt2 / Ct2 (= ΔCt4 / Ct4), ΔCt3 / Ct3, ΔCt1 / Ct1 (= ΔCt5 / Ct5) obtained by the same applied voltage. And will be different.

  That is, in a filter circuit that requires different capacitance change rates, when using a variable capacitor having the same capacitance change rate ΔC / C, desired circuit characteristics cannot be obtained with a constant applied voltage value. Therefore, since it is necessary to adjust to different capacitance change rates by adjusting the control voltage value, there has been a problem that the desired control voltage value applied to each variable capacitor is different. In addition, when the control voltage applied to the variable capacitor is different, there is a problem that the number of voltage control terminals is large. Furthermore, since a plurality of voltage controls to be applied are required, there is a problem that the control is complicated.

  The present invention has been devised in view of the problems in the prior art as described above, and its purpose is to share a control voltage applied to a plurality of variable capacitors and reduce the number of voltage control terminals. It is an object of the present invention to provide a variable capacitor that can realize different capacitance change rates and a filter circuit that can easily perform voltage control using the variable capacitor.

  The variable capacitor of the present invention includes (1) a first signal terminal, a second signal terminal, and a plurality of variable capacitance elements connected in series between the first signal terminal and the second signal terminal. At least one of the variable capacitance element group, a plurality of bias lines connected between the variable capacitance elements (between adjacent variable capacitance elements) and on both sides of the variable capacitance element group, and the bias line are connected. A first bias terminal and a second bias terminal connected to at least one of the bias lines different from the bias line connected to the first bias terminal, and connected to both sides of the variable capacitance element group Each of the two bias lines is connected to either the first bias terminal or the second bias terminal, and is connected to a bias line between the plurality of variable capacitance elements. At least one of is one that is selectably configured whether to connect to either of the first bias terminal or the second bias terminal. That is, in a variable capacitor whose capacitance changes according to the voltage applied between the first bias terminal and the second bias terminal, the capacitance change when the voltage is changed from the first voltage to the second voltage The rate can be controlled by the connection relationship between the first bias terminal and the second bias terminal and the bias line.

  In the variable capacitor of the present invention, (2) in the configuration of (1), the bias line connected to the first bias terminal or the second bias terminal among the bias lines is the variable capacitor. The elements are alternately connected to the first bias terminal and the second bias terminal in order from one direction of element arrangement.

  In the variable capacitor of the present invention, (3) in the configuration of (2), one of the bias lines connected to both sides of the variable capacitor group is the first bias terminal, and the other is the second bias. The first bias terminal and the first signal terminal are shared, and the second bias terminal and the second signal terminal are shared.

  Further, the filter circuit of the present invention is (4) provided between the input signal terminal and the output signal terminal, between the LC resonance part having a capacitive component part, and between the input signal terminal and the LC resonance part, An input coupling unit that adjusts an impedance on an input side of the LC resonance unit; an output coupling unit that is provided between the LC resonance unit and the output signal terminal, and that adjusts an impedance on an output side of the LC resonance unit; And at least one of the capacitance component section, the input coupling section, and the output coupling section is the first signal terminal and the second signal terminal of the variable capacitor according to any one of the above (1) to (3) Are connected.

  In the filter circuit according to the present invention, (5) in the configuration of (4), each of the capacitance component unit, the input coupling unit, and the output coupling unit is any one of the above (1) to (3). The first signal terminal and the second signal terminal of the variable capacitor are connected and functioned, the first bias terminals are connected in common, and the second bias terminals are connected in common. It is what.

  In addition, the filter circuit of the present invention is (6) provided between the input signal terminal and the output signal terminal, between a plurality of LC resonance parts having a capacitive component part, and between the input signal terminal and the LC resonance part. An input coupling unit that adjusts the impedance on the input side of the LC resonance unit, and an output coupling unit that is provided between the LC resonance unit and the output signal terminal and adjusts the impedance on the output side of the LC resonance unit And an interstage coupling unit provided between the plurality of LC resonance units, wherein at least one of the capacitance component unit, the input coupling unit, the output coupling unit, and the interstage coupling unit is the above (1 ) To (3) are connected to the first signal terminal and the second signal terminal of the variable capacitor.

  In the filter circuit according to the present invention, (7) In the configuration of (6), each of the capacitance component unit, the input coupling unit, the output coupling unit, and the interstage coupling unit may include (1) to ( 3) The first signal terminal and the second signal terminal of the variable capacitor of any one of 3) are connected to function, and the first bias terminals are connected in common, and the second bias terminals are connected in common. Are connected in common.

  According to the variable capacitor of the present invention, a plurality of variable capacitance elements connected in series can be obtained by appropriately changing the connection relationship between the first bias terminal, the second bias terminal, and the bias line according to the configuration of (1). The control voltage value applied to each can be changed. For this reason, even when the same control voltage is applied between the first bias terminal and the second bias terminal, different capacitance change rates can be obtained.

  Further, according to the variable capacitor of the present invention, the control voltage can be applied to each of the plurality of variable capacitors due to the configuration of (2).

  Further, according to the variable capacitor of the present invention, the first and second bias terminals for applying the control voltage and the first and second signal terminals for applying the high-frequency signal are provided by the configuration of (3). Since they can be shared, the number of necessary terminals can be reduced, and the configuration can be simplified.

  That is, according to the variable capacitor of the present invention, the combination of the series connection and the parallel connection of the variable capacitance elements when viewed in a direct current can be varied, so that the applied voltage applied to each variable capacitance element is large. Therefore, the rate of change in capacitance of the variable capacitor can be varied while maintaining the same control voltage (applied voltage, bias voltage) applied to the variable capacitor.

  Further, the variable capacitance capacitor of the present invention can adjust the capacitance variable rate of the variable capacitor even if the change in relative permittivity with respect to the bias voltage of the plurality of variable capacitors is substantially the same. Since the thickness of the thin film dielectric layer and the like can be made common, it is only necessary to change the capacitance forming portion (electrode area) to cope with the change in the design and manufacture of the variable capacitor, and the design and manufacture becomes easy. .

  In addition, according to the filter circuit of the present invention, the capacity change rate of the variable capacitor can be varied while maintaining the same applied voltage applied to the variable capacitor by the configurations of (4) to (6). The voltage control for obtaining the filter characteristics is easy.

  In addition, in order to obtain desired filter characteristics, it is possible to reduce the trouble of newly designing and manufacturing a variable capacitor having a different capacitance change rate, and as a result, it is possible to shorten the adjustment time and design time of the filter circuit.

  Further, the filter characteristics of the pass band and the stop band can be easily controlled by the plurality of LC resonance parts and the interstage coupling part between the LC resonance parts.

  Furthermore, even in the case of a filter circuit using a plurality of variable capacitors having different capacitance change rates, the applied voltage applied to each variable capacitor can be made the same, so that the applied voltage is applied to the plurality of variable capacitors. Therefore, a common voltage control terminal can be used, and a simple circuit configuration can be obtained. In addition, since the voltage control of the applied voltage supplied to the plurality of variable capacitors can be made common, the voltage control is facilitated and the number of voltage control terminals can be reduced. In particular, according to the configuration of (5), all the voltage controls of the capacitance component unit, the input coupling unit, and the output coupling unit can be made common, and the configuration can be simplified. Further, according to the configuration of (7), it is possible to share all voltage control of the capacitance component unit, the input coupling unit, the output coupling unit, and the interstage coupling unit, and a simpler configuration can be achieved.

  As described above, according to the present invention, it is possible to provide a variable capacitor and a filter circuit whose characteristics can be easily changed by voltage control.

  Hereinafter, the variable capacitance circuit of the present invention will be described in detail with reference to the drawings.

  1A to 1C show an example of an embodiment of a filter circuit of the present invention using one variable capacitor of the present invention, and are equivalent circuit diagrams of the filter. In addition, although it is the same also in the following drawings, the same code | symbol is attached | subjected to the same location and the overlapping description is abbreviate | omitted.

  In the equivalent circuit diagrams shown in FIGS. 1A to 1C, a symbol Ct indicating a configuration surrounded by a broken line is a capacitance at the applied voltage V between the first signal terminal S <b> 1 and the second signal terminal S <b> 2. Five variable capacitance elements C1 to C5 having a change rate X (= ΔC / C) are connected in series, and bias lines e1 to e6 are respectively connected to electrodes of the variable capacitance elements, and these bias lines are connected to the RF blocking inductor Lb11. , Lb12, Lb13, Lb14, Lb15, Lb16, a variable capacitor connected to a bias terminal V for supplying an applied voltage and a reference potential terminal (connected to the ground potential in the figure), and D1 λ / 4 short-circuited transmission line, Cin is an input coupling capacitive element constituting an input coupling section, Cout is an output coupling capacitive element constituting an output coupling section, and Cd is a DC limit. A capacitive element, I is an input signal terminal, and O is an output signal terminal. Thus, the filter circuit F1 is configured. In particular, at least one of the bias lines e2 to e5 (bias lines between the variable capacitance elements) is formed so that it can be selected whether or not to connect to the bias terminal V or the reference potential terminal. The capacitance change rate as a variable capacitor can be controlled by the connection relationship between the bias lines e1 to e6 including the bias lines e2 to e5, the bias terminal V, and the reference potential terminal.

  The bias terminal V and the reference potential terminal constitute a first bias terminal and a second bias terminal.

  The RF blocking inductors Lb11 to Lb16 prevent a high frequency signal inputted / outputted between the input signal terminal I and the output signal terminal O from leaking to the bias terminal V and the reference potential terminal, and are sufficient for the high frequency signal. The one with high impedance is used. In addition, a strip line having a 1 / 4λ line length with respect to the wavelength of a resistor or a high-frequency signal can be used. The DC limiting capacitor element Cd prevents a DC voltage from the bias terminal V and the reference potential terminal from leaking to other elements constituting the filter circuit F1, and a normal capacitor having a dielectric layer sandwiched between electrodes is used. However, if the capacitance is sufficiently large so as not to affect the capacitance of the variable capacitance elements C1 to C5 in the high frequency band, the capacitance as a variable capacitance capacitor and the rate of change in capacitance will not be affected. preferable.

  First, the variable capacitor of the present invention will be described.

  In FIG. 1, the variable capacitance elements C1 to C5 constitute a variable capacitance element group. The bias lines e1 to e6 are connected to both sides of the variable capacitance element group and between the variable capacitance elements. Since the bias lines e1 to e6 are provided in advance and have a connection end (terminal portion) that can be connected to either the bias terminal V or the reference potential terminal, a desired capacitance change rate can be obtained. The connection relationship can be selected accordingly. A connection relationship between the bias lines e1 to e6, the bias terminal V, and the reference potential terminal, and an example of the capacitance variable rate by the connection relation will be described.

  First, the initial capacitance value of each of the variable capacitance elements C1 to C5 is C (capacitance value when the first voltage is applied), the control voltage value V1 (second voltage) is the capacitance value when C ′, and the capacitance change The rate X = (C−C ′) / C, the initial capacitance value of the variable capacitor Ct is Ctv, the capacitance value when the voltage is applied is Ctv ′, and the capacitance change rate Xt = (Ctv−Ctv ′) / Ctv.

  As shown in FIG. 1A, the bias line e1 of the variable capacitor is connected to the bias terminal V via the RF blocking inductor Lb11. The bias line e6 of the variable capacitor Ct is connected to the GND terminal (reference potential terminal, that is, the ground potential) via the RF blocking inductor Lb16. When the control voltage value V1 is applied to the bias terminal V, since C1 to C5 are connected in series, the voltage V ′ applied to each of the variable capacitance elements C1 to C5 is divided into V1 / 5 and thus the variable capacitance. The capacitance change rate X of the elements C1 to C5 is X / 5. Therefore, the capacitance change rate Xt of the variable capacitor Ct is X / 5.

  Further, the bias lines e1 and e3 of the variable capacitor Ct as shown in FIG. 1B are connected to the bias terminal V via the RF blocking inductors Lb11 and Lb13, respectively. The bias lines e2 and e6 of the variable capacitor Ct are connected to the GND terminal via the RF blocking inductors Lb12 and Lb16, respectively. In such a configuration, in terms of direct current, it can be regarded as a parallel connection with the variable capacitance elements C3, C4, and C5 connected in series with the variable capacitance elements C1 and C2. Therefore, V1 '= V2' = V1 is applied to the voltages V1 'and V2' applied to the variable capacitance elements C1 and C2, respectively. Further, since the variable capacitance elements C3, C4, and C5 are connected in series, the voltage V 'applied to each of the variable capacitance elements C3, C4, and C5 is divided into V1 / 3. The capacitance value Ctv ′ of the variable capacitor Ct at the time of voltage application is 1 / Ctv ′ = 1 / C (1−X) + 1 / C (1−X) + 1 / C (1−X / 3) + 1 / C ( 1−X / 3) + 1 / C (1−X / 3), Ctv ′ = C (1−X) · (1−X / 3) / (2 · (1−3 / X) + 3 · (1 -X)), and the capacitance change rate Xt of the variable capacitor Ct is Xt = ((C / 5-C. (1-X). (1-X / 3) / (2. (1-X / 3 ) + 3 * (1-X))) / (C / 5) = 1-5 * (1-X) * (1-X / 3) / (2 * (1-X / 3) + (3 * ( 1-X)).

  Furthermore, the bias lines e1, e3, e5 of the variable capacitor Ct as shown in FIG. 1C are connected to the bias terminal V via the RF blocking inductors Lb11, Lb13, Lb15, respectively. The bias lines e2, e4, e6 of the variable capacitor Ct are connected to the GND terminal via the RF blocking inductors Lb12, Lb14, Lb16, respectively. In such a configuration, each of the variable capacitance elements C1, C2, C3, C4, and C5 can be regarded as a parallel connection in terms of direct current. Therefore, the voltage V ′ applied to each variable capacitance element C1, C2, C3, C4, C5 is equal to the voltage V1 applied to the variable capacitance capacitor Ct, and the capacitance of each variable capacitance element C1 to C5. The change rate is X, and the capacitance change rate Xt of the variable capacitor Ct is also equal to X.

  As described above, in the variable capacitor Ct in which n variable capacitors are connected in series, when a constant control voltage value V1 is applied to the bias terminal V, the capacitance change rate Xt is freely set from X / n to X. be able to. In particular, the value between X / n and X can be set as follows. In other words, according to the method of connecting n + 1 bias lines to the bias terminal and the GND terminal, n variable capacitance elements are connected in series with y single variable capacitance elements and (ny) in direct current. The variable capacitance elements can be connected in parallel. The capacitance change rate Xt of the variable capacitor Ct in this case is Xt = 1−n · (1-X) · (1−X / (ny)) / (y · (1−X / (ny). )) + (Ny) · (1-X)). (However, y ≦ n−1, where n is a positive integer.) That is, the variable capacitance capacitor Ct is determined by the number (n) of variable capacitance elements and the number (y) of variable capacitance elements singly connected in parallel. The capacitance change rate Xt can be varied without varying the applied voltage V1.

  For example, when the capacitance change rate X of each of the variable capacitance elements C1 to C5 is 50%, in FIG. 1A, the capacitance change rate Xt of the variable capacitance capacitor Ct is 10%. Similarly, in FIG. 1B, Xt = 34%, and in FIG. 1C, Xt = 50%, and the capacitance change rate Xt of the variable capacitor Ct is set with the same applied voltage applied to the variable capacitor Ct. Can be variable.

In addition, in the adjustment to obtain the desired filter characteristics, it is possible to reduce the time and effort of designing and manufacturing a variable capacitor having a different capacitance change rate. As a result, the adjustment time and design time of the filter circuit can be shortened. Thus, the connection relationship between the bias lines e1 to e6 and the bias terminals V and GND terminals can be freely set, but as shown in FIGS. 1A to 1C, the bias lines e1 to e6 include: The bias lines connected to the bias terminal V or the GND terminal are alternately connected to the bias terminals V and GND terminals in order from one direction of the arrangement direction of the variable capacitance elements C1 to C5. By alternately connecting in this way, a control voltage can be applied to each of the plurality of variable capacitance elements.

  Next, an example of a method for producing the variable capacitor Ct of the present invention will be described.

  FIG. 2 is a plan view of a principal part in a see-through state showing an example of a variable capacitor Ct having five variable capacitors C1 to C5 with respect to the variable capacitor Ct of the present invention. FIG. A sectional view taken along line AA ′ of the variable capacitor Ct shown in FIG. 3, and FIG. 3B is a sectional view taken along line BB ′ of the variable capacitor Ct shown in FIG.

  2 and 3 show the configuration of the variable capacitance element group and the bias line in the variable capacitance capacitor Ct, and the illustration of the first bias terminal and the second bias terminal is omitted.

  2 and 3, 1 is a support substrate, 2 is a lower electrode layer, 3 is a dielectric layer, 4 is an upper electrode layer, 5 is an insulating layer, 6 is an extraction electrode layer, 7 is a protective layer, and 8 is solder diffusion. The prevention layers 111, 112 and 113, 114, 115, 116, 117, 118 are solder terminal portions. The solder diffusion prevention layer 8 and the solder terminal portions 111 and 112 constitute an input terminal as a first signal terminal and an output terminal as a second signal terminal, respectively. The solder diffusion prevention layer 8 and the solder terminal portions 113, 114, 115, 116, 117, and 118 are connection ends that constitute a bias line, respectively. In order to connect the variable capacitance elements C1 to C5 in series, the variable capacitance elements C1 and C2 and the variable capacitance elements C3 and C4 are configured to share the lower electrode layer 2.

  The support substrate 1 is a ceramic substrate such as alumina ceramic, a single crystal substrate such as sapphire, or the like. A lower electrode layer 2, a dielectric layer 3 and an upper electrode layer 4 are sequentially formed on the support substrate 1 over almost the entire surface of the support substrate 1. After the formation of these layers, the upper electrode layer 4, the dielectric layer 3 and the lower electrode layer 2 are sequentially etched into a predetermined shape.

  When forming the lower electrode layer 2, the dielectric layer 3, and the upper electrode layer 4, particles are formed between the lower electrode layer 2 and the dielectric layer 3 and between the dielectric layer 3 and the upper electrode layer 4. It is desirable to minimize the contamination of impurities that can cause the characteristics of the variable capacitor Ct to deteriorate. Therefore, it is desirable that the lower electrode layer 2, the dielectric layer 3 and the upper electrode layer 4 are continuously formed by the same film forming apparatus without opening the film forming chamber to the atmosphere. For this reason, sputtering is suitable as a specific film forming method.

Since the lower electrode layer 2 requires high-temperature sputtering to form the dielectric layer 3, it needs to be made of a high melting point material so as to withstand the high temperature. Specifically, it is made of a metal material such as Pt, Pd, or Ir or an oxide metal such as IrO ₂ . This lower electrode layer 2 is also formed by high temperature sputtering. Furthermore, the lower electrode layer 2 is heated to 700 to 900 ° C. which is the sputtering temperature of the dielectric layer 3 after being formed by high-temperature sputtering, and is maintained for a certain period of time until the sputtering of the dielectric layer 3 is started. Become.

  The thickness of the lower electrode layer 2 is determined in consideration of the resistance component from the variable capacitance element C1 to the variable capacitance element C2, the resistance component from the variable capacitance element C3 to the variable capacitance element C4, and the continuity of the lower electrode layer 2. The thicker one is desirable, but when considering the adhesiveness with the support substrate 1, the relatively thinner one is desirable, and both are determined. Specifically, it is 0.1 μm to 10 μm. If the thickness of the lower electrode layer 2 is less than 0.1 μm, the resistance of the lower electrode layer 2 itself increases, and the continuity of the lower electrode layer 2 may not be ensured. On the other hand, if it is thicker than 10 μm, the internal stress increases, and the adhesion to the support substrate 1 may be lowered, or the support substrate 1 may be warped.

  The dielectric layer 3 is preferably a high dielectric constant dielectric layer made of a perovskite oxide crystal containing at least Ba, Sr, and Ti. The dielectric layer 3 is formed on the surface (upper surface) of the lower electrode layer 2. For example, using a dielectric material from which a perovskite oxide crystal can be obtained as a target, film formation by sputtering is performed until a desired thickness is obtained. At this time, by performing high temperature sputtering at a high substrate temperature, for example, 800 ° C., a low loss dielectric layer 3 having a high dielectric constant and a large capacitance change rate can be obtained without performing a heat treatment after sputtering. .

  As the material of the upper electrode layer 4, Au having a low resistivity is desirable in order to reduce the resistance of this layer, but in order to improve the adhesion with the dielectric layer 3, it is desirable to use Pt or the like as the adhesion layer. . The thickness of the upper electrode layer 4 is 0.1 μm to 10 μm. The lower limit of the thickness is set in consideration of the resistance and continuity of the upper electrode layer 4 itself as in the lower electrode layer 2. Further, the upper limit of the thickness is set in consideration of the adhesion with the dielectric layer 3.

  After film formation as described above, the upper electrode layer 4, the dielectric layer 3 and the lower electrode layer 2 are sequentially etched into a predetermined shape. Etching is performed by wet etching or dry etching after uniformly applying a resist on the entire surface by spin coating or the like, patterning the resist into a predetermined shape by photolithography. Since the capacitance values of the variable capacitance elements C1 to C5 are determined by the area of the upper electrode layer 4, it is desirable to use dry etching with higher accuracy in the etching of the upper electrode layer 4.

  The dry etching can be performed using, for example, an electron cyclotron resonance apparatus (ECR apparatus) and argon plasma as an etchant.

  The dielectric layer 3 may be etched by either wet etching or dry etching.

  The lower electrode layer 2 may be etched by either wet etching or dry etching. However, when the lower electrode layer 2 is thick, dry etching is performed in the same manner as the upper electrode layer 4 from the viewpoint of patterning accuracy. It is desirable to carry out by etching.

  In the etching of the upper electrode layer 4, the dielectric layer 3 and the lower electrode layer 2 as described above, the lower surface of the dielectric layer 3 is smaller than the upper surface of the lower electrode layer 2, and the lower surface of the upper electrode layer 4 is the dielectric layer 3. Etching is performed so as to be smaller than the upper surface. As a result, the dielectric layer 3 does not exist at the outer edge portion of the lower electrode layer 2 where the electric field tends to concentrate, so that the leakage current characteristics are improved.

  In this way, variable capacitance elements C1 to C5 can be obtained.

  Here, in order to electrically connect between the input terminal (first signal terminal) and the variable capacitor C1 and between the variable capacitor C5 and the output terminal (second signal terminal), It is desirable to form a conductive layer made of a conductive material at a position where the first and second signal terminals are formed. This conductive layer may be formed by forming a new film after forming the variable capacitors C1 to C5. However, when the lower electrode layer 2 is patterned, patterning is performed so that these conductive layers are formed at the same time. By performing, the same material and the same process as the lower electrode layer 2 may be used. Here, it is preferable that the lower electrode layer 2 of the variable capacitance element C5 and the conductive layer at the position where the output terminal is formed be patterned so as to be electrically connected.

  The solder terminal portion 113 constituting the bias line (e1) is between the connection points of the input terminal and the variable capacitance element C1, and the solder terminal portion 114 constituting the bias line (e2) is the connection between the variable capacitance element C1 and the variable capacitance element C2. Between the connection points, the solder terminal portion 115 constituting the bias line (e3) is between the connection points of the variable capacitance element C2 and the variable capacitance element C3, and the solder terminal portion 116 constituting the bias line (e4) is the variable capacitance element C3. The solder terminal portion 117 constituting the bias line (e5) between the connection point of the variable capacitance element C4 and the solder terminal portion constituting the bias line (e6) between the connection point of the variable capacitance element C4 and the variable capacitance element C5. Reference numeral 118 is provided so as to be electrically connected between connection points of the variable capacitance element C5 and the output terminal. Specifically, a conductive layer is formed in advance at positions where the solder terminal portions 113 to 118 are formed. This conductive layer may be formed in the same material and in the same process as the lower electrode layer so as to be formed simultaneously with the patterning of the lower electrode layer 2. At this time, the conductive layers at the positions where the solder terminal portions 114, 116, and 118 are formed may be patterned so as to be electrically connected to the lower electrode layer 2. The bias line is formed by the above-described solder diffusion prevention layer 8, the solder terminal portions 113 to 118, and this conductive layer.

  Next, the insulating layer 5 is necessary for ensuring insulation between the extraction electrode layer 6 and the lower electrode layer 2 formed thereon. The material of the insulating layer 5 is preferably made of at least one of silicon nitride and silicon oxide in order to improve moisture resistance. These films are preferably formed by a chemical vapor deposition (CVD) method or the like in consideration of coverage.

  The insulating layer 5 can be processed into a desired shape by a dry etching method using a normal resist. The insulating layer 5 is a conductive layer serving as a base for the solder terminal portions 115 and 117 constituting the bias line in order to secure the connection between the solder terminal portions 115 and 117 constituting the bias line and the lead electrode layer 6. A reaching through hole is provided. In addition, it is preferable that only the upper electrode layer 3 and the solder terminal portions 111, 112, 113, 114, 115, 116, 117, and 118 are exposed from the insulating layer 5 from the viewpoint of improving moisture resistance.

  Next, the lead electrode layer 6 is provided between the upper electrode layer 4 of the first variable capacitance element C1 and the input terminal, that is, the conductive layer of the input terminal forming portion, and the upper electrodes of the variable capacitance element C2 and the variable capacitance element C3. The layers 5 and the upper electrode layer 4 of the variable capacitance element C4 and the upper electrode layers 4 of the variable capacitance element C5 are connected through the through holes of the insulating layer 5, respectively.

  By forming the lead electrode layer 6 in this way, the variable capacitance elements C1 to C5 are sequentially connected in series from the input terminal to the output terminal. Further, the lead electrode layer 6 extending over the variable capacitance elements C2 and C3 is connected to the solder terminal portion 115 constituting the bias line through the through hole of the insulating layer 5. Further, the lead electrode layer 6 extending over the variable capacitance elements C4 and C5 is connected to the solder terminal portion 117 constituting the bias line through the through hole of the insulating layer 5. As a material for the extraction electrode layer 6, it is desirable to use a low-resistance metal such as Au or Cu. Further, an adhesive layer such as Ti or Ni may be used in consideration of adhesiveness with the insulating layer 5 with respect to the extraction electrode layer 6.

  When the extraction electrode layer 6 is formed, it is preferable to form a layer made of the material constituting the extraction electrode layer 6 at the positions where the solder terminal portions 111 to 118 are formed. This is because the mounting is facilitated by aligning the heights of the positions where the solder terminal portions 111 to 118 are formed.

  Next, the protective layer 7 is formed so that the solder terminal portions 111, 112, 113, 114, 115, 116, 117, 118 are exposed and covered entirely. The protective layer 7 is used to mechanically protect the constituent members of the variable capacitor Ct including the variable capacitor C1, and to protect it from contamination by chemicals and the like. As a material of the protective layer 7, a material having high heat resistance and excellent coverage with respect to a step is preferable. Specifically, a polyimide resin, a BCB (benzocyclobutene) resin, or the like is used. These are formed by applying a resin material and then curing at a predetermined temperature.

  The solder diffusion prevention layer 8 is applied to the solder terminal portions 111, 112, 113, 114, 115, 116 during reflow or mounting when the solder terminal portions 111, 112, 113, 114, 115, 116, 117, 118 are formed. , 117 and 118 are formed to prevent the solder from diffusing into the extraction electrode layer 6 or the lower electrode layer 2. As a material of the solder diffusion preventing layer 8, Ni is suitable. On the surface of the solder diffusion preventing layer 8, in order to improve the solder wettability, Au, Cu or the like having a high solder wettability may be formed to about 0.1 μm.

  Finally, solder terminal portions 111, 112, 113, 114, 115, 116, 117, 118 are formed on the solder diffusion preventing layer 8. This is formed to facilitate mounting of the variable capacitor on the external wiring board. These solder terminal portions 111, 112, 113, 114, 115, 116, 117, 118 print solder paste using a predetermined mask on the solder terminal portions 111, 112, 113, 114, 115, 116, 117, 118. Thereafter, it is generally formed by performing reflow.

  According to the variable capacitor Ct described above, the solder terminal portions 113, 114, 115, 116, 117, and 118 that constitute the bias line are formed directly on the support substrate 1, so that each element such as the variable capacitor C1 is formed. The number of layers constituting the is reduced. Further, since the formation process of each conductor layer, dielectric layer, etc. constituting each element can be made common, it can be formed very easily despite the relatively complicated structure.

  Thus, by forming in advance a bias line having the solder terminal portions 113 to 117 between the variable capacitance elements C1 to C5 and on both sides of the variable capacitance element group composed of the variable capacitance elements C1 to C5, The connection between the solder terminal portions 113 to 117 of the bias line and the first bias terminal and the second bias terminal can be appropriately set in accordance with a desired capacitance change rate.

  2 and 3, the first bias terminal and the second bias terminal are omitted. However, the solder terminal portions 113 are formed on the support substrate 1 in the same manner as the solder terminal portions 111 to 118 and constitute the bias line. ˜118 may be appropriately selected and electrically connected, or may be electrically connected to the solder terminal portions 113 to 118 constituting the bias line via the switching element. Further, the first bias terminal and the second bias terminal do not have to be formed on the same support substrate 1. For example, when the structure formed on the support substrate 1 is mounted on a wiring substrate or the like, You may form in the wiring board side.

  For example, the case where each connection state shown in FIG. 1 is set using a wiring board will be described. In order to obtain the connection state shown in FIG. 1A, a connection line is formed on the wiring board side so as to connect from the solder terminal portion 113 to the first bias terminal, and connected from the solder terminal portion 118 to the second bias terminal. Such a connection line may be formed, and the wiring board and the structure formed on the support substrate 1 may be arranged so as to face each other. By forming this connection line like a strip line having a 1 / 4λ line length of a high-frequency signal, the connection line has a function as the RF blocking inductors Lb11 and Lb16. Similarly, in order to achieve the connection state shown in FIG. 1B, connection lines are formed so as to connect from the solder terminal portions 113 and 115 to the first bias terminal, and the solder terminal portions 114 and 118 respectively A connection line that connects up to two bias terminals may be formed, and the structure formed on the wiring board and the support substrate 1 may be disposed facing each other. Similarly, in order to obtain the connection state shown in FIG. 1C, connection lines are formed so as to connect from the solder terminal portions 113, 115, 117 to the first bias terminal, respectively, and the solder terminal portions 114, 116, Connection lines that connect from 118 to the second bias terminal may be formed, and the wiring board and the structure formed on the support substrate 1 may be disposed facing each other.

  Although the variable capacitor Ct described above has been described with respect to an example in which the number of variable capacitors is an odd number, it may be an even number as shown in FIG.

  In the above example, the first signal terminal S1 and the second signal terminal S2, and the bias terminal V and the GND terminal are completely separated. However, as shown in FIG. When one of the bias lines connected to both sides of the element group is connected to the bias terminal V and the other is connected to the GND terminal, the bias terminal V and the first signal terminal S1 are shared. You may share 2 signal terminal S2. In this case, since the number of terminals can be reduced, a variable capacitor Ct that is easier to handle and has a simple configuration can be realized.

  In the above example, the bias line is connected to the bias terminal V and the reference potential terminal via the RF blocking inductor, but instead of the RF blocking inductor, a resistor having a sufficiently high impedance for a high frequency signal. May be used.

  Furthermore, in the above example, the bias line and the RF blocking inductor or resistor are separated, but an RF blocking inductor or resistor may be incorporated in the bias line. For example, an inductor component or a resistor may be formed between the conductive layer constituting the bias line and the electrode layers 2 and 6 of the variable capacitance elements C1 to C5.

  Next, an example in which such a variable capacitor is used in a filter circuit will be described. 1A to 1C are provided between the input signal terminal I and the output signal terminal O, between the LC resonance part having a capacitive component part, and between the input signal terminal I and the LC resonance part, A filter comprising: an input coupling unit that adjusts the impedance on the input side of the LC resonance unit; and an output coupling unit that is provided between the LC resonance unit and the output signal terminal O and adjusts the impedance on the output side of the LC resonance unit. This is an example in which the variable capacitor of the present invention is used in the capacitance component section of the circuit.

  In FIGS. 1A to 1C, the LC resonance unit includes a transmission line D1, and a variable capacitance capacitor Ct connected in parallel to the transmission line D1 via a DC limiting capacitive element Cd. Consists of. The first signal terminal S1 of the variable capacitor Ct is connected to the DC limiting capacitor element Cd, and the second signal terminal S2 is connected to the ground potential. Here, the resonance frequency in the LC resonance unit can be changed by changing the capacitance of the variable capacitor Ct.

  Here, the capacitance change rate Xt can be changed from X / 5 to X by the applied voltage V1 supplied to the variable capacitor Ct. For this reason, even if the applied voltage is constant, the filter circuit can operate as a filter circuit that can be switched to a plurality of desired filter characteristics.

  In this example, the example in which the variable capacitor Ct of the present invention is used only for the capacitance component portion has been described. However, the variable capacitor Ct of the present invention is used for either the input coupling portion, the output coupling portion, or both. Can do. By using the variable capacitor of the present invention for these, the impedance on the input side and the impedance on the output side can be adjusted respectively. In addition, the number of terminals can be reduced by making the bias terminals V and GND terminals of the variable capacitors Ct used in the capacitive component section, the input coupling section, and the output coupling section common. Even in this case, the capacity change rate can be set freely with respect to the constant control voltage value V1, so that the capacity change rate suitable for each part can be realized, and the filter has excellent characteristics. A circuit can be realized. Thus, according to the filter circuit of the present invention, voltage control for obtaining desired filter characteristics is facilitated.

Next, FIG. 5 shows another example of the embodiment of the filter circuit of the present invention, and is an equivalent circuit diagram of a filter using five variable capacitors of the present invention. (In the filter circuit shown in FIG. 6, it is almost the same as the example using the variable capacitors of the present invention for the variable capacitors Ct1 to Ct5.)
FIG. 5 is provided between the input signal terminal I and the output signal terminal O, a plurality of LC resonance units having a capacitive component portion, and between the input signal terminal I and the LC resonance unit, and the input of the LC resonance unit. Provided between the LC coupling unit and the input coupling unit that adjusts the impedance on the side, and between the LC coupling unit and the output coupling unit that regulates the impedance on the output side of the LC resonant unit This is an example in which the variable capacitance capacitor of the present invention is used in all of the capacitive component section, the input coupling section, the output coupling section, and the interstage coupling section. Specifically, the configuration is as follows.

  In the equivalent circuit diagram shown in FIG. 5, the symbols Ct1, Ct2, Ct3, Ct4, and Ct5 are all connected in series with five variable capacitance elements C1 to C5 having a capacitance change rate X (= ΔC / C) at the applied voltage V. These are variable capacitance capacitors in which bias connection lines e1 to e6 are connected to the electrodes of the variable capacitance elements, respectively. D1 and D2 are λ / 4 short-circuited transmission lines, and variable capacitors Ct2 and Ct4 are respectively connected in parallel to the plurality of transmission lines D1 and D2 to form a plurality of LC resonance units. . Further, the transmission lines D1 and D2 are M-coupled together with the variable capacitor Ct3 as an interstage coupling portion. The variable capacitors Ct1 and Ct5 are an input coupling unit and an output coupling unit for coupling with an external circuit. Cd is a DC limiting capacitance element, I is an input signal terminal, and O is an output signal terminal. Thus, the filter circuit F2 is configured. Lb11, Lb21, Lb22, Lb23, Lb24, Lb25, Lb26, Lb31, Lb32, Lb33, Lb34, Lb41, Lb42, Lb43, Lb44, Lb45, Lb46, and Lb51 are RF blocking inductors. The impedance is set so as not to affect the impedance of Ct5 and variable capacitance elements C1 to C5 and to prevent a high frequency signal from leaking to the bias terminal V. V is a bias terminal for supplying an applied voltage.

  In the example of the filter circuit F2 shown in FIG. 5, the input / output impedance is mainly input / output by using the variable capacitors Ct2 and Ct4 of the LC resonance unit in the pass band and the variable capacitor Ct3 of the interstage coupling unit in the stop band. Adjustments are made to obtain desired filter characteristics by changing the capacitance values of the variable capacitors Ct1 and Ct5 of the coupling unit.

  For example, in order to support two communication systems of the K-PCS band (1750 MHz band) and the UMTS band (1950 MHz), the capacitance values of the variable capacitors Ct1 to Ct5 are adjusted to obtain desired filter characteristics. Become. The variable capacitors Ct2 and Ct4 form a resonance circuit together with D1 and D2, respectively, mainly changing the pass band, Ct3 changing the stop band together with the coupling with D1 and D2, and Ct1 and Ct5 mainly changing the input / output impedance. The capacitance change rates of the variable capacitors Ct1 to Ct5 are different from ΔCt2 / Ct2 (= ΔCt4 / Ct4) = α, ΔCt3 / Ct3 = β, ΔCt1 / Ct1 (= ΔCt5 / Ct5) = γ. Necessary.

  For example, a case where α = 50%, β = 42%, and γ = 10% when the capacitance change rate X of each of the variable capacitance elements C1 to C5 is 50% will be described.

  First, a method of setting γ = 10% for the variable capacitors Ct1 and Ct5 will be described.

  As shown in FIG. 5, the RF blocking inductor Lb11 is used to connect the bias line e1 of the variable capacitor Ct1 to the bias terminal V. Similarly, the RF blocking inductor Lb51 is used to connect the bias line e6 of the variable capacitor Ct5 to the bias terminal V. The other ends of the variable capacitors Ct1 and Ct5 are connected to the GND terminal via a λ / 4 short-circuited transmission line. That is, the second signal terminal S2 of the variable capacitor Ct1 and the terminal of the bias line e6 are commonly connected, and are connected to the GND terminal via the transmission line D1. Similarly, the first signal terminal S1 of the variable capacitor Ct5 and the terminal of the bias line e1 are commonly connected, and are connected to the GND terminal via the transmission line D2.

  At this time, since the variable capacitance elements C1 to C5 are connected in series also in direct current, the voltage V ′ applied to each of the variable capacitance elements C1 to C5 is divided to V1 / 5, and each variable capacitance element The capacity change rate X of X is X / 5. For this reason, the capacitance change rate Xt of the variable capacitors Ct1 and Ct5 can be set to X / 5. The capacitance value can be set to the capacitance change rate Xt = X / 5 = 10% = γ by the applied voltage V1 supplied to the variable capacitors Ct1 and Ct5.

  Next, a method of setting β = 42% for the variable capacitor Ct3 will be described.

  Similarly, an RF blocking inductor is used in the variable capacitor Ct3, and is connected to the bias terminals e2 and e4 of the variable capacitor Ct3 to the bias terminal V via the RF blocking inductors Lb32 and Lb34, respectively. In addition, RF blocking inductors Lb31 and Lb33 are connected to the GND terminal on the bias lines e1 and e3 of the variable capacitor Ct3, respectively. The second signal terminal S2 of the variable capacitor Ct3 is connected to the GND terminal via the transmission line D2. For this reason, the second signal terminal S2 of the variable capacitor Ct3 and the terminal of the bias line e6 are commonly connected, and are connected to the GND terminal via the transmission line D2.

  In such a configuration, the variable capacitor Ct3 can be regarded as a parallel connection of the variable capacitors C1, C2, C3 and the variable capacitors C4, C5 connected in series with each other in terms of DC. V1 '= V2' = V1 is applied to the voltages V1 ', V2' applied to the variable capacitance elements C1, C2, C3, respectively. Further, since the variable capacitance elements C4 and C5 are connected in series, the voltage V 'applied to each of the variable capacitance elements C4 and C5 is divided into V1 / 2. The capacitance change rate Xt of the variable capacitor Ct is Xt = 1−n · (1-X) · (1−X / (ny)) / (y · (1−X / (ny)) + (N−y) · (1−X)), Xt = 1−5 · (1−X) · (1−X / 2) / (3 · (1−X / 2) + (2 · (1) -X)) The capacitance value can be set to the capacitance change rate Xt = 42% = β by the applied voltage V1 supplied to the variable capacitor Ct3.

  Next, a method of setting α = 50% for the variable capacitors Ct2 and Ct4 will be described.

  Similarly, the variable capacitance capacitors Ct2 and Ct4 also use RF blocking inductors, and are connected to the bias lines e1, e3, and e5 of the variable capacitance capacitors Ct2 and Ct4 via RF blocking inductors Lb21, Lb23, Lb25, Lb41, Lb43, and Lb45, respectively. Connect to bias terminal V. Further, the bias lines e2, e4, e6 of the variable capacitors Ct2, Ct4 are connected to the GND terminal via RF blocking inductors Lb22, Lb24, Lb26, Lb42, Lb44, Lb46, respectively. In such a configuration, since each of the variable capacitance elements C1, C2, C3, C4, and C5 can be regarded as a parallel connection in terms of DC, each of the variable capacitance elements C1, C2, C3, C4, and C5 Is equal to the voltage V1 applied to the variable capacitor, and the capacitance change rate of each of the variable capacitors C1 to C5 is X. For this reason, the capacitance change rate Xt of the variable capacitors Ct2 and Ct4 can also be made equal to X. Therefore, the variable capacitors Ct2 and Ct4 can have a capacitance value of capacitance change rate Xt = 50% = α by the applied voltage V1 supplied to the bias terminal V.

  That is, even when the same bias voltage is applied to the variable capacitor having the same configuration using the variable capacitance element having the capacitance change rate X = 50%, the variable capacitors Ct1 and Ct5 have the capacitance change rate Xt = 10%. = Γ, the capacitance change rate of the variable capacitor Ct3 can be Xt = 42% = β, and the variable capacitance capacitors Ct2 and Ct4 can be the change rate of capacitance Xt = 50% = α. In this way, since the capacitance change rate Xt of the variable capacitor Ct can be varied while keeping the same applied voltage applied to the variable capacitor Ct, voltage control for obtaining desired filter characteristics is facilitated.

Further, in the example shown in FIG. 5, the plurality of variable capacitors Ct1 to Ct5 share the bias terminal V as the first bias terminal, and the GND terminal as the second bias terminal is also connected to the same potential. In this way, even in the case of a filter circuit using a plurality of variable capacitors having different capacitance change rates, the applied voltage applied to each variable capacitor can be made the same. A voltage control terminal for applying an applied voltage to the variable capacitor can be made common, and a simple circuit configuration can be achieved. In addition, since the voltage control of the applied voltage supplied to the plurality of variable capacitors can be made common, the voltage control is facilitated and the number of voltage control terminals can be reduced. Even in this case, by appropriately adjusting the connection relationship between the bias line and the bias terminal V and the GND terminal, a desired capacitance change rate can be achieved even when the same bias voltage is applied.

Also, the filter characteristics of the pass band and stop band can be controlled by appropriately adjusting the connection relationship between the bias line and the bias terminal V and the GND terminal by using a plurality of LC resonance parts and interstage coupling parts between the LC resonance parts. In the example shown in FIG. 5 above, the example in which the variable capacitor of the present invention is used in all of the capacitive component unit, the input coupling unit, the output coupling unit, and the interstage coupling unit has been described. At least one of the variable capacitors of the present invention may be used.

  In addition, this invention is not limited to the example of the above embodiment, A various change may be added in the range which does not deviate from the summary of this invention. For example, when the output (input) terminal of the variable capacitor is connected to GND as in the variable capacitor Ct of FIG. 1 or Ct2 and Ct4 of FIG. 5, the RF blocking inductors Lb16, Lb22, LB24, Lb26, Lb42, LB44. , Lb46 may be omitted. Further, a bias circuit may be configured using a resistor or the like instead of the RF blocking inductor.

  1 and 5 is a parallel resonance circuit, a series resonance circuit or a combination of a parallel resonance circuit and a series resonance circuit may be used depending on the purpose.

(A), (b), (c) is an equivalent circuit diagram which shows an example of embodiment of the filter circuit of this invention using the variable capacitor of this invention, respectively. It is a principal part top view of the see-through state which shows the example of the variable capacitor used for FIG. (A), (b) is the sectional view on the A-A 'line of FIG. 2, and the sectional view on the B-B' line, respectively. (A), (b) is an equivalent circuit diagram which shows the other example of embodiment of the variable capacitor of this invention, respectively. It is an equivalent circuit diagram which shows the other example of embodiment of the filter circuit of this invention. It is an equivalent circuit diagram which shows the other example of the conventional filter circuit.

Explanation of symbols

F1, F2 ... Filter circuit of the present invention Ct, Ct1, Ct2, Ct3, Ct4, Ct5 ... Variable capacitors C1, C2, C3, C4, C5 ... Variable capacitors e1, e2, e3, e4 , E5, e6 ... bias line S1 ... first signal terminal S2 ... second signal terminal Cin ... input coupling capacitor Cout ... output coupling capacitor I ... input signal terminal O ... Output signal terminal Cd DC limiting element Lb11, Lb12, Lb13, Lb14, Lb15, Lb16, Lb21, Lb22, Lb23, Lb24, Lb25, Lb26, Lb31, Lb32, Lb33, Lb34, Lb41, Lb42, Lb43, Lb44, Lb45, Lb46, Lb51 ... RF blocking inductor V ... Bias terminal 1 ... Support base Plate 2 ... Lower electrode layer 3 ... Thin film dielectric layer 4 ... Upper electrode layer 5 ... Insulating layer 6 ... Lead-out electrode layer 7 ... Protective layer 8 ... Solder diffusion prevention layer 111, 112, 113, 114, 115, 116, 117, 118 ... solder terminal part

Claims (7)

A first signal terminal;
A second signal terminal;
A variable capacitance element group consisting of a plurality of variable capacitance elements connected in series between the first signal terminal and the second signal terminal;
A plurality of bias lines connected between the plurality of variable capacitance elements and on both sides of the variable capacitance element group;
A first bias terminal to which at least one of the bias lines is connected;
A second bias terminal to which at least one of the bias lines different from the bias line connected to the first bias terminal is connected;
The two bias lines connected to both sides of the variable capacitance element group are each connected to either the first bias terminal or the second bias terminal,
At least one of the bias lines between the plurality of variable capacitance elements is configured to be selectable to be connected or not connected to either the first bias terminal or the second bias terminal. Capacitor capacitor.   Among the bias lines, the bias lines connected to the first bias terminal or the second bias terminal are the first bias terminal and the second bias terminal in order from one direction of the arrangement direction of the variable capacitance elements. The variable capacitor according to claim 1, which is alternately connected to each other. One of the bias lines connected to both sides of the variable capacitance element group is connected to the first bias terminal, and the other is connected to the second bias terminal.
The first bias terminal and the first signal terminal are shared,
The variable capacitor according to claim 2, wherein the second bias terminal and the second signal terminal are shared. Provided between the input signal terminal and the output signal terminal, an LC resonance unit having a capacitive component, and between the input signal terminal and the LC resonance unit, and adjusts the impedance on the input side of the LC resonance unit An input coupling unit, and an output coupling unit that is provided between the LC resonance unit and the output signal terminal and adjusts an impedance on an output side of the LC resonance unit,
At least one of the capacitance component unit, the input coupling unit, and the output coupling unit is connected to the first signal terminal and the second signal terminal of the variable capacitor according to any one of claims 1 to 3. , Filter circuit.   Each of the capacitance component unit, the input coupling unit, and the output coupling unit functions by connecting the first signal terminal and the second signal terminal of the variable capacitor according to claim 1. 5. The filter circuit according to claim 4, wherein the first bias terminals are connected in common and the second bias terminals are connected in common. Provided between the input signal terminal and the output signal terminal are a plurality of LC resonance parts having a capacitance component part, and between the input signal terminal and the LC resonance part, and the impedance on the input side of the LC resonance part is Provided between the input coupling section to be adjusted, the LC resonance section and the output signal terminal, and between the output coupling section for adjusting impedance on the output side of the LC resonance section and the plurality of LC resonance sections. An interstage coupling part,
4. The first signal terminal and the second signal of the variable capacitor according to claim 1, wherein at least one of the capacitance component unit, the input coupling unit, the output coupling unit, and the inter-stage coupling unit. Filter circuit connecting terminals.   4. The first signal terminal and the second signal terminal of the variable capacitor according to claim 1, wherein each of the capacitance component unit, the input coupling unit, the output coupling unit, and the interstage coupling unit is provided. The filter circuit according to claim 6, wherein the first bias terminals are connected in common and the second bias terminals are connected in common.

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