JP2006066647A - Variable capacitor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a variable capacitor, small in a capacity changing rate by high-frequency signal while enlarging the capacity changing rate by a DC bias. <P>SOLUTION: The variable capacitor is provided with a plurality of variable capacity elements C1-C5 connected in series and whose capacities are changed by a DC bias voltage, and bias lines B11-B15, B21-B25 connected to respective variable capacity elements C1-C5 to impress the DC bias voltage. In such a variable capacitor, the bias lines B11-B15, B21-B25 are provided with at least one of a resistance component or an inductance component having a capacity enough to intercept a high-frequency signal, and the partial pressure of the DC bias voltage applied on each bias lines B11-B15, B21-B25 is smaller than that of the DC bias voltage applied on each variable capacity elements C1-C5 while values of resistances of the bias lines B11-B15, B21-B25 are reduced as temperatures of the lines are raised. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a variable capacitor that can operate satisfactorily with low dielectric loss even in a high-frequency region. In particular, the capacitance can be changed greatly by applying a DC bias voltage. The present invention relates to a variable capacitor that can suppress distortion.

A strontium titanate (SrTiO ₃ ) thin film that is a paraelectric material and a strontium barium titanate ((Ba, Sr) TiO ₃ ) thin film that is a ferroelectric material are conventionally used as dielectric thin film capacitors for ICs. It is expected to be a dielectric material suitable for reducing the area of a dielectric thin film capacitor for ICs because it has a higher dielectric constant than _two thin films, Si ₃ N ₄ thin films, and Ta ₂ O ₅ thin films.

  A thin film capacitor using a ferroelectric oxide thin film having a perovskite structure such as strontium titanate or strontium barium titanate as a dielectric layer has been proposed (see, for example, Patent Document 1).

  In the thin film capacitor disclosed in Patent Document 1, a first electrode layer 202, a thin film dielectric layer 203, and a second electrode layer 204 are sequentially covered on a support substrate 201 as shown in a cross-sectional view in FIG. It is wearing. Specifically, after a conductor layer to be the first electrode layer 202 is deposited on substantially the entire surface of the support substrate 201, pattern processing is performed on the electrode shape of the first electrode layer 202, and the first electrode layer having a predetermined shape is formed. 202 is formed. Next, a thin film dielectric layer 203 is formed on the first electrode layer 202. The thin film dielectric layer 203 is formed by placing a mask at a predetermined position and forming it by a thin film forming method, or by spin coating, and then patterning it into a predetermined shape. Note that the thin film dielectric layer 203 is heat-cured as necessary.

  Next, the second electrode layer 204 is formed by patterning the electrode shape of the second electrode 204 after forming a conductor layer on substantially the entire surface of the thin film dielectric layer 203. Here, in the thin-film dielectric layer 203, a facing region that is actually sandwiched between the first electrode layer 202 and the second electrode layer 204 is a capacitance generation region.

Such a thin film capacitor 200 controls the dielectric constant of the thin film dielectric layer 203 to a desired value by applying a predetermined bias signal (bias voltage) to the thin film dielectric layer 203 in actual use. Therefore, the capacitance characteristic can be controlled, and the capacitor functions as a variable capacitor.
Japanese Patent Laid-Open No. 11-260667

  When the variable capacitor as described above is used in a high-frequency electronic component, a variable-capacitance DC bias voltage and a high-frequency signal voltage (high-frequency voltage) are simultaneously applied to the variable capacitor. At this time, when the high frequency voltage is high, the capacitance of the variable capacitor also changes depending on the high frequency voltage. When such a variable capacitor is used for a high-frequency electronic component, noise due to waveform distortion or intermodulation distortion occurs due to capacitance change due to a high-frequency voltage. In order to reduce noise caused by waveform distortion and intermodulation distortion, it is necessary to reduce the high-frequency electric field strength and to reduce the capacitance change due to the high-frequency voltage. For this purpose, it is effective to increase the thickness of the dielectric layer. However, if the thickness of the dielectric layer is increased, the DC electric field strength is also reduced, and the capacity change rate is also lowered.

  In addition, since a current easily flows through a capacitor at a high frequency, the variable capacitor may be damaged due to heat generated by the loss resistance of the capacitor while the variable capacitor is used at a high frequency. It is effective to increase the thickness of the dielectric layer and reduce the amount of heat generated per unit volume in order to cope with such a problem of withstand power. However, as described above, the thickness of the dielectric layer is simply increased. Then, since the DC electric field intensity is also reduced, there is a problem that the capacity change rate due to the DC bias is also lowered.

  The present invention has been devised in view of the above problems in the prior art, and its object is to enable an applied DC bias voltage to be efficiently applied to a dielectric layer. An object of the present invention is to provide a variable capacitor that has a high capacitance change rate due to a DC bias, a low capacitance change rate due to a high-frequency signal, a low intermodulation distortion, and an excellent power resistance.

  Another object of the present invention is to provide a variable capacitor that has a wide usable frequency range and can be miniaturized.

  The first variable capacitor according to the present invention is applied to 1) a plurality of variable capacitance elements that are connected in series and whose capacitance is changed by a DC bias voltage, and the DC bias voltage connected to each of these variable capacitance elements is applied. A variable capacitor having a bias line, the bias line having at least one of a resistance component and an inductance component, and having a size such that the resistance component and the inductance component block a high-frequency signal, and The divided voltage of the DC bias voltage is smaller than the divided voltage of the DC bias voltage applied to the variable capacitance element, and the resistance value of the bias line decreases as the temperature increases.

  The first variable capacitor of the present invention is 2) In the configuration of 1) above, the resistance component of the bias line blocks a high-frequency signal of 100 MHz or more, and the variable capacitance element of the variable capacitance element is within a use temperature range. It is characterized by having a magnitude of 1/100 or less of the insulation resistance.

  The second variable capacitor according to the present invention includes 3) a plurality of variable capacitance elements that are connected in series and whose capacitance is changed by a DC bias voltage, and the DC bias voltage connected to each of these variable capacitance elements. A variable capacitor having an individual bias line to be applied and a common bias line connected to the individual bias lines, wherein the common bias line and the individual bias line have at least one of a resistance component and an inductance component. The resistance component and the inductance component are sized to cut off a high-frequency signal, and the DC bias voltage applied to the common bias line and the individual bias line is divided by the DC bias voltage applied to the variable capacitance element. The common bias line is smaller than the pressure. Resistance of the fine the individual bias line is characterized in that the decrease with temperature rise.

  In the second variable capacitor of the present invention, 4) in the configuration of 3) above, the resistance component of the common bias line and the individual bias line cuts off a high frequency signal of 100 MHz or more and is within the operating temperature range. The sum of the resistance component distributed to the individual bias line of the common bias line and the resistance component of the individual bias line is 1/100 or less of the insulation resistance of the variable capacitance element. It is.

The first and second variable capacitors of the present invention are 5) In any one of the above configurations 1) to 4), the variable capacitance element is (Ba _x , Sr _1-x ) _y Ti _1-y Provided with a thin film dielectric layer consisting of O _3-z (where 0 <x <1, 0 <y <1, z is a value slightly larger than 0 and considerably smaller than 1) It is good to do.

  According to the first variable capacitor of the present invention, since it is configured as described in 1) above, the DC bias voltage is applied to each variable capacitance element via the bias line. A variable capacitor in which a plurality of variable capacitance elements are connected in parallel is obtained, and the capacity change rate of each variable capacitance element due to the DC bias voltage of the bias signal can be utilized to the maximum. On the other hand, since the high-frequency signal applied to the bias signal is blocked by a bias line having one of a sufficiently large resistance component and inductance component, a plurality of variable capacitance elements have a high frequency with respect to the high-frequency signal input to the variable capacitor. It becomes a variable capacitor connected in series. Therefore, since the high frequency voltage (voltage of the high frequency signal) is divided by each variable capacitance element, the capacitance change due to the high frequency signal can be reduced, and waveform distortion, intermodulation distortion, and the like can be suppressed.

  Further, the divided voltage of the DC bias voltage applied to the bias line is smaller than the divided voltage of the DC bias voltage applied to the variable capacitance element. In other words, since the DC bias voltage is divided by the ratio of the resistance value of the bias line resistance component and the insulation resistance of the variable capacitance element, the applied DC bias voltage is more efficiently applied to the variable capacitance element. And has a good capacity change rate.

  Furthermore, the temperature coefficient of the resistance component of the variable capacitance element is normally negative, and the temperature coefficient of the resistance value of the bias line is both negative and takes the same sign, so even if the temperature changes, the resistance of the bias line Since the ratio between the value and the insulation resistance of the variable capacitance element can be maintained at the same level, the applied DC bias voltage is efficiently applied to the variable capacitance element even if the temperature changes.

  Also, according to the first variable capacitor of the present invention, when configured as in 2) above, each variable capacitance element is connected in series in a high frequency region of 100 MHz or higher by blocking a high frequency signal of 100 MHz or higher. Therefore, in a high frequency region of the GHz band that is actively used in the communication field in recent years, it becomes a variable capacitor with small waveform distortion and intermodulation distortion and excellent power durability.

  Furthermore, by setting the resistance component of the bias line within the operating temperature range to 1/100 or less of the insulation resistance of the variable capacitance element, 95% or more of the applied DC bias can be applied to the variable capacitance element. A desired capacity value can be obtained by changing the capacity efficiently.

  Further, according to the second variable capacitor of the present invention, since it is configured as in the above 3), the same effect as that of the first variable capacitor of the present invention can be obtained, and common to a plurality of individual bias lines. Since the common bias line and the individual bias line have at least one of a resistance component and an inductance component, at least one of the resistance component and the inductance component of the same size bias line is provided. In the first variable capacitor according to the present invention, the resistance component is configured to be secured by including both the common bias line and the individual bias lines, rather than only the individual bias lines connected to the variable capacitance elements. And the shape of the part that realizes the inductance component can be reduced. Even when the individual bias line is manufactured, even if the size of the part that realizes at least one of the resistance component and the inductance component of the individual bias line cannot be increased due to restrictions on the element shape of the variable capacitance element, etc. In addition, a sufficiently large resistance component and inductance component can be secured.

  Furthermore, the temperature coefficient of the resistance component of the variable capacitance element is normally negative, and the temperature coefficient of the resistance value of the common bias line and the individual bias line is both negative and has the same sign, so that it is common even if the temperature changes. Since the ratio between the resistance value of the bias line and the individual bias line and the insulation resistance of the variable capacitance element can be maintained at the same level, the applied DC bias voltage is efficiently applied to the variable capacitance element even if the temperature changes. It will be.

  Further, according to the second variable capacitor of the present invention, when configured as in the above 4), similarly to the first variable capacitor of the present invention, in the GHz band actively used in the recent communication field. In a high-frequency region, a variable capacitor having small waveform distortion and intermodulation distortion and excellent power durability is obtained. Furthermore, it is applied by making the sum of the resistance component distributed to the individual bias lines of the common bias line and the resistance component of the individual bias line within the operating temperature range be 1/100 or less of the insulation resistance of the variable capacitance element. 95% or more of the DC bias voltage can be applied to the variable capacitance element, and a desired capacitance value can be obtained by changing the capacitance more efficiently.

The first and second variable capacitors of the present invention are thin film dielectric layers in which the variable capacitance element is made of (Ba _x , Sr _1-x ) _y Ti _1-y O ₃ -z as in 5) above. Therefore, the capacitance change rate of the variable capacitance element can be increased and the loss can be reduced.

  Hereinafter, examples of embodiments of a variable capacitor of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a circuit diagram showing an example of an embodiment of a first variable capacitor according to the present invention when five variable capacitance elements are connected in series. In FIG. 1, C1, C2, C3, C4, and C5 are variable capacitance elements (first variable capacitance element C1, second variable capacitance element C2, third variable capacitance element C3, and fourth variable capacitance element C4. The fifth variable capacitance element C5) has insulation resistances Rc1, Rc2, Rc3, Rc4, and Rc5. B11, B12, B21, and B22 are bias lines having at least one of a resistance component and an inductor component (in the figure, resistance components R11, R12, R21, and R22 are shown). In FIG. 1, the high-frequency signal and the DC bias voltage are applied from a common terminal, where symbol I represents an input terminal and symbol O represents an output terminal.

  Then, the input-side terminal portion of the first variable capacitance element C1, the series connection point of the second variable capacitance element C2 to the third variable capacitance element C3, and the fourth variable capacitance element C4 to the fifth variable capacitance element. Bias lines B11 and B12 having resistance components R11 and R12 are respectively provided between the series connection points of C5.

  The output side terminal portion of the fifth variable capacitance element C5, the series connection point of the third variable capacitance element C3 to the fourth variable capacitance element C4, and the first variable capacitance element C1 to the second variable capacitance element. Bias lines B21 and B22 having resistance components R21 and R22 are respectively provided between the series connection points of C2.

  In FIG. 1, the resistance components R11, R12, R21, and R22 of the bias lines B11, B12, B21, and B22 are resistance components that are larger than the impedance in the frequency region of the high-frequency signal of the variable capacitance elements C1 to C5 connected in series. In order to cut off the high frequency signal, the high frequency signal passes through the variable capacitance elements C1 to C5 connected in series, and the DC bias voltage is independently applied to each of the variable capacitance elements C1 to C5.

  As a result, the DC bias voltage is individually applied to each of the variable capacitance elements C1 to C5. Therefore, in terms of DC, the variable capacitance elements C1 to C5 become variable capacitors connected in parallel, and each of the bias signals is applied to each variable capacitance element C1 to C5. The capacitance change rate of the variable capacitance elements C1 to C5 can be utilized to the maximum. On the other hand, since the high frequency signal is cut off by the bias lines B11, B12, B21, and B22, the high frequency signal becomes a variable capacitor in which variable capacitance elements C1 to C5 are connected in series. Therefore, since the high frequency voltage is divided into the variable capacitance elements C1 to C5, the capacitance change due to the high frequency signal can be reduced, and waveform distortion, intermodulation distortion, and the like can be suppressed.

  Here, if the resistance components R11, R12, R21, and R22 of the bias lines B11, B12, B21, and B22 are too small, the high-frequency signal also flows through the bias lines B11, B12, B21, and B22. The capacitance change due to the high frequency signal of C5 becomes large, the phase is more than -90 °, and the Q value is lowered. On the other hand, if the resistance components R11, R12, R21, and R22 of the bias lines B11, B12, B21, and B22 are too large, the DC bias voltage applied to each of the variable capacitance elements C1 to C5 decreases due to the voltage division, and the capacitance changes. It will be smaller. Therefore, the resistance components R11, R12, R21, and R22 of the bias lines B11, B12, B21, and B22 need to be in an appropriate range, for example, the following size.

FIG. 2 shows the insulation resistances of the variable capacitance elements C1 to C5 in FIG. 1 for setting the lower limit values of the resistance components R11, R12, R21, and R22 of the bias lines B11, B12, B21, and B22. = Rc4 = Rc5 = 10 GΩ, R11 = R12 = R21 = R22 = R, and the relationship between the magnitudes and phases of the resistance components R11, R12, R21, R22 of the bias lines B11, B12, B21, B22 is obtained by simulation It is a diagram which shows the result. In FIG. 2, the horizontal axis represents the frequency (unit: Hz), the vertical axis represents the phase (unit: deg), and the characteristic curves show the phases when R is set to 500 kΩ, 1 MΩ, 5 MΩ, 10 MΩ, and 50 MΩ, respectively. The frequency characteristics are shown. Note that the 1.0E + 05 on the horizontal axis in FIG. 2, 10 ⁵ i.e. indicates 100k, and 1.0E + 06, indicating a ¹⁰⁵ i.e. 1M.

  From the results shown in FIG. 2, it can be seen that as the resistance components R11, R12, R21, and R22 of the bias lines B11, B12, B21, and B22 increase, the phase approaches −90 ° even in the low frequency region. When the resistance value R of the bias lines B11, B12, B21, and B22 is 1 MΩ or more, the high-frequency signal of 100 MHz or more is substantially cut off, and the high-frequency signal is connected in series to the bias lines B11, B12, B21, and B22 without leaking. Since the variable capacitance elements C1 to C5 are passed through, the variable capacitor having small waveform distortion and intermodulation distortion and excellent power durability even in the high frequency region of the GHz band which is actively used in the recent communication field. It becomes.

  3 shows the insulation resistances of the variable capacitance elements C1 to C5 in the configuration shown in FIG. 1 in order to set the upper limit values of the resistance components R11, R12, R21, and R22 of the bias lines B11, B12, B21, and B22. The change in the ratio of the voltage of the DC bias voltage applied to each of the variable capacitance elements C1 to C5 with respect to the ratio of the resistance value Rc of Rc1 to Rc5 and the resistance value R of the bias lines B11, B12, B21, B22 is obtained by simulation. It is a diagram which shows the result. That is, the DC bias voltage applied between the input / output terminals I and O by the resistance components R11, R12, R21 and R22 of the bias lines B11, B12, B21 and B22 is the bias lines B11, B12, B21 and B22. Are divided into the variable capacitance elements C1 to C5, and the voltage division ratio is determined by the resistance values R of the resistance components R11, R12, R21, R22 of the bias lines B11, B12, B21, B22 and the variable capacitance elements. It is determined by the ratio of the resistance values Rc of the insulation resistances Rc1 to Rc5 of C1 to C5. Here, Rc1 = Rc2 = Rc3 = Rc4 = Rc5 = Rc, R11 = R12 = R21 = R22 = R, the resistance component ratio Rc / R, and the DC bias applied to each variable capacitance element C1 to C5 The change of the voltage ratio of the voltage was obtained by simulation. In FIG. 3, the horizontal axis represents the resistance component ratio Rc / R, the vertical axis represents the ratio of the voltage applied to the variable capacitance element, and the black dots and the characteristic curves indicate the change.

  From the results shown in FIG. 3, as Rc / R decreases, that is, as the insulation resistances Rc1 to Rc5 of the variable capacitors C1 to C5 decrease, or the resistance components R11, R12, R21 of the bias lines B11, B12, B21, B22, It can be seen that as R22 increases, the ratio of the DC bias voltage applied to each of the variable capacitance elements C1 to C5 decreases.

  Then, by setting the ratio Rc / R of the insulation resistances Rc1 to Rc5 of the variable capacitance elements C1 to C5 and the resistance components R11, R12, R21, and R22 of the bias lines B11, B12, B21, and B22 to 5 or more, the variable capacitance Since the divided voltage of the DC bias voltage applied to the elements C1 to C5 is larger than the divided voltage of the DC bias voltage applied to the bias lines B11, B12, B21, and B22, it is applied between the input / output terminals I and O. More than half of the DC bias voltage to be applied is applied to the variable capacitance elements C1 to C5, and a desired capacitance value can be obtained efficiently.

  Further, 95% or more of the DC bias voltage applied between the input / output terminals I and O is applied to the variable capacitance elements C1 to C5, and in order to obtain a desired capacitance value very efficiently, the variable capacitance elements C1 to C1 can be obtained. The ratio Rc / R between the insulation resistances Rc1 to Rc5 of C5 and the resistance components R11, R12, R21, R22 of the bias lines B11, B12, B21, B22 is 100 or more, that is, the resistances of the bias lines B11, B12, B21, B22 It has been found that the sizes of the components R11, R12, R21, and R22 need to be 1/100 or less of the insulation resistances Rc1 to Rc5 of the variable capacitance elements C1 to C5.

  As can be seen from the results shown in FIGS. 2 and 3, in the configuration shown in FIG. 1, the resistance components R11, R12, R21, and R22 of the bias lines B11, B12, B21, and B22 are set to 1 MΩ or more, and The insulation resistances Rc1 to Rc5 of the variable capacitance elements C1 to C5 may be 1/100 or less.

  As a result, in a high frequency region in the GHz band, which is actively used in the recent communication field, a variable capacitor with small waveform distortion and intermodulation distortion and excellent power resistance is obtained, and the applied DC bias voltage is 95. % Or more can be applied to the variable capacitance elements C1 to C5, the capacitance can be changed more efficiently, and a desired capacitance value can be obtained.

  Next, each of FIGS. 4 to 8 shows an actual variable capacitor element manufactured based on the configuration shown in FIG. 1, FIG. 4 is a plan view showing a transparent state, and FIG. 6 is a cross-sectional view taken along the line AA ′ in FIG. 4, FIG. 7 is a cross-sectional view taken along the line BB ′ in FIG. 4, and FIG. It is sectional drawing in CC 'line.

  4 to 8, 1 is a support substrate, 2 is a lower electrode layer, 31, 32, 33 and 34 are conductor lines, 4 is a thin film dielectric layer, and 5 is an upper electrode layer. 61, 62, 63 and 64 are thin film resistors, 7 is an insulating layer, 8 is an extraction electrode layer, 9 is a protective layer, 10 is a solder diffusion prevention layer, 111, Reference numerals 112 denote solder terminal portions. The solder diffusion prevention layer 10 and the solder terminal portions 111 and 112 constitute an input terminal I and an output terminal O. 4 and 6, C1 to C5 indicate variable capacitance elements whose capacitances are changed by a DC bias voltage, respectively.

  The support substrate 1 is a ceramic substrate such as alumina, or a single crystal substrate such as sapphire. Then, the lower electrode layer 2, the thin film dielectric layer 4, and the upper electrode layer 5 are sequentially formed on the entire surface of the support substrate 1 on the support substrate 1. After the formation of all layers, the upper electrode layer 5, the thin film dielectric layer 4, and the lower electrode layer 2 are sequentially etched into a predetermined shape.

  The lower electrode layer 2 needs to have a high melting point because high-temperature sputtering is required to form the thin film dielectric layer 4. Specifically, Pt, Pd, etc. may be used. Further, the lower electrode layer 2 is heated to 700 to 900 ° C. which is the sputtering temperature of the thin film dielectric layer 4 after the sputtering is completed, and is held for a certain period of time until the sputtering of the thin film dielectric layer 4 is started. Become.

  The thickness of the lower electrode layer 2 is such that the resistance component from the output terminal (solder terminal portion 112, solder diffusion prevention layer 10) to the fifth variable capacitance element C5, or the first variable capacitance element C1 to the second variable capacitance element. C2, the resistance component from the third variable capacitance element C3 to the fourth variable capacitance element C4, the fifth variable capacitance element C5 to the sixth variable capacitance element C6, and the continuity of the lower electrode layer 2 are taken into consideration In this case, the thicker one is desirable, but when considering the adhesion to the support substrate 1, the thinner one is desirable, and both are determined in consideration. Specifically, it is 0.1 μm to 10 μm. This is because if the thickness is less than 0.1 μm, the resistance of the lower electrode layer 2 itself increases, and the continuity of the lower electrode layer 2 may not be ensured. This is because there is a possibility that the adhesion with the substrate may be lowered or the support substrate 1 may be warped.

  The thin film dielectric layer 4 is preferably a high dielectric constant dielectric layer made of perovskite oxide crystal particles containing at least Ba, Sr, and Ti. The thin film dielectric layer 4 is formed on the surface of the lower electrode layer 2 described above. For example, sputtering is performed until a desired thickness is reached using a dielectric material from which perovskite-type oxide crystal particles can be obtained as a target. By performing sputtering at a high substrate temperature, for example, 800 ° C., the low loss thin film dielectric layer 4 having a high dielectric constant and a large capacitance change rate can be obtained without performing a heat treatment after sputtering.

  The material of the upper electrode layer 5 is desirably Au having a low resistivity in order to reduce the resistance of the electrode. However, in order to improve the adhesion with the thin film dielectric layer 4, it is desirable to use Pt or the like as the adhesion layer. The thickness of the upper electrode layer 5 is 0.1 μm to 10 μm. The lower limit of the thickness is set in consideration of the resistance of the upper electrode layer 5 itself, like the lower electrode layer 2. Further, the upper limit of the thickness is set in consideration of adhesion.

  The bias line B11 includes conductor lines 32 and 33 and a thin film resistor 61, and includes an input terminal (solder terminal portion 111, solder diffusion prevention layer 10) that is an input terminal portion of the first variable capacitance element C1, The connection point between the second variable capacitance element C2 and the third variable capacitance element C3, that is, the upper electrode layer 5 of the second variable capacitance element C2 and the upper electrode layer 5 of the third variable capacitance element C3 are connected. It is provided between the extraction electrode layer 8. Similarly, the bias line B12 includes conductor lines 32 and 34 and a thin film resistor 62, and is provided between the input terminal and a connection point between the fourth variable capacitance element C4 and the fifth variable capacitance element C5. It has been.

  The bias line B21 includes a conductor line 31 and a thin film resistor 63, and is a connection point between the third variable capacitance element C3 and the fourth variable capacitance element C4, that is, the third variable capacitance element C3 and the third variable capacitance element C3. 4 is provided between the common lower electrode layer 2 of the variable capacitance element C4 and the output terminal (solder terminal portion 112, solder diffusion prevention layer 10) which is the output end of the fifth variable capacitance element C5. Yes. Similarly, the bias line B22 includes a conductor line 31 and a thin film resistor 64, and is provided between a connection point between the first variable capacitance element C1 and the second variable capacitance element C2 and the output terminal. ing.

  The conductor lines 31, 32, 33 and 34 can be obtained by forming a new film after forming the lower electrode layer 2, the thin film dielectric layer 4 and the upper electrode layer 5 described above. In that case, it is desirable to use a lift-off method. Further, it can be formed by patterning the shape having the conductor lines 31, 32, 33, 34 when the lower electrode layer 2 is patterned.

  As a material of the conductor lines 31, 32, 33, 34, Au (gold) which is a low resistance is desirable in order to suppress variations in resistance values of the bias lines B11, B12, B21, B22. Since the resistance of ˜64 is sufficiently high, it may be formed by the same material and the same process as the lower electrode layer 2 such as Pt (platinum).

  Next, it is desirable that the material of the thin film resistors 61 to 64 constituting the bias lines B11, B12, B21, B22 has a specific resistance of 1 Ωcm or more and a negative temperature characteristic of the resistance value. By using such a high-resistance material, the device can be manufactured without increasing the shape of the device even when the bias lines B11, B12, B21, and B22 are provided, which is advantageous for miniaturization. . Specific examples of the thin film resistors 61 to 64 include tantalum nitride, TaSiN, Ta—Si—O, and NiCr. For example, in the case of tantalum nitride, a resistive film having a desired composition ratio and resistivity can be formed by a reactive sputtering method in which sputtering is performed by adding nitrogen using Ta (tantalum) as a target. By appropriately selecting the sputtering conditions, a resistance film having a specific resistance of 1 Ωcm or more can be produced. Furthermore, after the sputtering is completed, a resist is applied, processed into a predetermined shape, and then easily patterned by an etching process such as reactive ion etching (RIE).

  Further, in the variable capacitor shown in FIG. 4, the resistance components of the bias lines B11, B12, B21, and B22 block a high frequency signal of 100 MHz or more and have a magnitude of 1/100 or less of the insulation resistance of the variable capacitance elements C1 to C5. For this purpose, the resistance values of the thin film resistors 61 to 64 need to be 10 MΩ or less, assuming that the insulation resistances of the variable capacitance elements C1 to C5 are 1 GΩ. When a material having a specific resistance of 1 Ωcm or more is used as the material for the thin film resistors 61 to 64, the film thickness is 40 nm and the aspect ratio (length / width) is 4 or more in order to realize the resistance value. The thin film resistors 61 to 64 having an aspect ratio that can be realized without increasing the element shape can be manufactured.

  Bias lines B11, B12, B21, and B22 including these thin film resistors 61 to 64 are directly formed on the support substrate 1. As a result, an insulating layer for securing insulation from the lower electrode layer 2, the upper electrode layer 5, and the lead electrode layer 8, which is required when the thin film resistors 61 to 64 are formed on the variable capacitance elements C1 to C5, is provided. This is unnecessary, and the number of layers constituting the variable capacitor can be reduced.

  Next, the insulating layer 7 is necessary for ensuring insulation between the lead electrode layer 8 and the lower electrode layer 2 formed thereon. Further, since this insulating layer 7 covers the bias lines B11, B12, B21, and B22, which can prevent the thin film resistors 61 to 64 from being oxidized, the resistance of the bias lines B11, B12, B21, and B22. The value can be made constant over time, improving reliability. In order to improve moisture resistance, the material of the insulating layer 7 may be made of, for example, at least one of silicon nitride and silicon oxide. These are preferably formed by a chemical vapor deposition (CVD) method or the like in consideration of coverage.

  The insulating layer 7 can be formed into a desired shape by a dry etching method using a normal resist. The insulating layer 7 is provided with a through hole that exposes a part of the conductor lines 33 and 34 in order to secure the coupling between the thin film resistors 61 and 62 and the lead electrode layer 8. In addition, it is preferable that only the upper electrode layer 5 and the solder terminal portions 111 and 112 be exposed from the insulating layer 7 from the viewpoint of improving moisture resistance.

  Next, the lead electrode layer 8 connects the upper electrode layer 5 of the first variable capacitance element C1 and one of the solder terminal portions 111 or the upper electrode layers 5 to each other so that the first variable capacitance element C1 is connected to the solder terminal. The second variable capacitance element C2 and the third variable capacitance element C3, and the fourth variable capacitance element C4 and the fifth variable capacitance element C5 are connected in series while being connected to the unit 111. . Furthermore, the lead electrode layer 8 extending over each of the second variable capacitance element C2, the third variable capacitance element C3, and the fourth variable capacitance element C4 and the fifth variable capacitance element C5 includes the insulating layer 7. The through holes are connected to the conductor lines 33 and 34, respectively.

  As the material of the extraction electrode layer 8, it is desirable to use a low resistance metal such as Au or Cu (copper). In consideration of adhesion to the insulating layer 7, an adhesion layer such as Ti (titanium) or Ni (nickel) may be used.

  Next, the protective layer 9 is formed. The protective layer 9 mechanically protects the element from the outside and protects it from contamination by chemicals. When the protective layer 9 is formed, the solder terminal portions 111 and 112 are exposed. The material of the protective layer 9 is preferably a material having high heat resistance and excellent step coverage, and specifically, a polyimide resin, a BCB (benzocyclobutene) resin, or the like is used.

  The solder diffusion preventing layer 10 is formed to prevent diffusion of solder to the electrodes during reflow or mounting when forming the solder terminal portions 111 and 112. Ni is suitable as the material. In addition, in order to improve solder wettability, Au, Cu, etc. having high solder wettability may be formed on the surface of the solder diffusion preventing layer 10 to about 0.1 μm.

  Finally, solder terminal portions 111 and 112 are formed. This is formed to facilitate mounting. In general, it is formed by printing a solder paste on the solder diffusion preventing layer 10 and then performing reflow.

  Although the variable capacitor manufactured as described above can change its capacitance greatly by applying a DC bias voltage, it becomes a variable capacitor that can suppress capacitance change, noise, and nonlinear distortion due to a high-frequency signal.

  Furthermore, FIG. 9 shows another example of the embodiment of the first variable capacitor of the present invention in the case where 11 variable capacitance elements are connected in series. According to this example, an increase in the number of variable capacitance elements connected in series has the same effect as increasing the thickness of the dielectric layer in terms of high frequency, and further reduces intermodulation distortion caused by high frequency signals. And withstand power is improved.

  In the example shown in FIG. 9, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, and C11 are variable capacitance elements, and the respective insulation resistances are Rc1, Rc2, Rc3, Rc4, Rc5, Rc6, Rc7, Rc8, Rc9, Rc10, Rc11. The bias lines B11, B12, B13, B14, B15, B21, B22, B23, B24, B25 are bias lines having at least one of a resistance component and an inductor component (in the figure, resistance components R11, R12, R13, R14). , R15, R21, R22, R23, R24, and R25. In the example shown in FIG. 9, the application of the high-frequency signal and the DC bias voltage is made from a common terminal, where symbol I represents an input terminal and symbol O represents an output terminal.

  The connection method of each bias line B11, B12, B13, B14, B15, B21, B22, B23, B24, B25 is the case where the five variable capacitance elements C1 to C5 shown in FIG. 4 are connected in series. It is the same.

  Also in the example shown in FIG. 9, the resistance components R11, R12, R13 of the bias lines B11, B12, B13, B14, B15, B21, B22, B23, B24, B25 are the same as in the example shown in FIG. The upper and lower limits of R14, R15, R21, R22, R23, R24, and R25 were determined.

  FIG. 10 shows the lower limit values of the resistance components R11, R12, R13, R14, R15, R21, R22, R23, R24, and R25 of the bias lines B11, B12, B13, B14, B15, B21, B22, B23, B24, and B25. 9 is set to Rc1 = Rc2 = Rc3 = Rc4 = Rc5 = Rc6 = Rc7 = Rc8 = Rc9 = Rc10 = Rc11 = 10 GΩ, and R11 = R12 = R13 = R14 = R15 = R21 = R22 = R23 = R24 = R25 = R is the same diagram as FIG. 2 and shows the result of the relationship between the magnitude of the resistance component of the bias line and the phase obtained by simulation. is there. In FIG. 10, the horizontal axis represents the frequency (unit: Hz), the vertical axis represents the phase (unit: deg), and the characteristic curves are set when R is set to 1 MΩ, 5 MΩ, 10 MΩ, 20 MΩ, 30 MΩ, and 50 MΩ, respectively. The frequency characteristic of the phase of is shown.

  As shown in FIG. 10, when the resistance value R of the bias line is 1 MΩ or more, the high-frequency signal of 100 MHz or higher is substantially cut off, so that the high-frequency signal is applied to the bias lines B11, B12, B13, B14, B15, B21, B22, The variable capacitance elements C1 to C11 connected in series without leaking to B23, B24, and B25 pass through, and the resistance components R11 of the bias lines B11, B12, B13, B14, B15, B21, B22, B23, B24, and B25, The lower limit value of R12, R13, R14, R15, R21, R22, R23, R24, R25 is 20 MΩ.

  FIG. 11 shows the upper limit of the resistance components R11, R12, R13, R14, R15, R21, R22, R23, R24, R25 of the bias lines B11, B12, B13, B14, B15, B21, B22, B23, B24, B25. In order to set the values, in the example shown in FIG. 9, the insulation resistances Rc1 to Rc11 = Rc of the variable capacitance elements C1 to C11 and the bias lines B11, B12, B13, B14, B15, B21, B22, B23, B24, Simulation of changes in the DC bias voltage applied to each of the variable capacitance elements C1 to C11 with respect to the ratio of the resistance components R11, R12, R13, R14, R15, R21, R22, R23, R24, and R25 to the resistance value R of B25 It is the same diagram as FIG. 3 which shows the result calculated | required by (3). Again, Rc1 = Rc2 = Rc3 = Rc4 = Rc5 = Rc6 = Rc7 = Rc8 = Rc9 = Rc10 = Rc11 = Rc, R11 = R12 = R13 = R14 = R15 = R21 = R22 = R23 = R24 = R25 = R did. Also in FIG. 11, the horizontal axis represents the resistance component ratio Rc / R, the vertical axis represents the ratio of the voltage applied to the variable capacitance element, and the black dots and the characteristic curves show the change.

  As shown in FIG. 11, the ratio Rc / R between the insulation resistance Rc of the variable capacitance elements C1 to C11 and the resistance R of the bias lines B11, B12, B13, B14, B15, B21, B22, B23, B24, B25 is 5 Thus, the DC bias voltage applied to the variable capacitance elements C1 to C11 is divided into the DC bias applied to the bias lines B11, B12, B13, B14, B15, B21, B22, B23, B24, and B25. Since it becomes larger than the divided voltage, more than half of the DC bias voltage applied between the input / output terminals I and O is applied to the variable capacitance elements C1 to C11, and a desired capacitance value can be obtained efficiently. Further, 95% or more of the DC bias voltage applied between the input / output terminals I and O is applied to the variable capacitance elements C1 to C11, and in order to obtain a desired capacitance value very efficiently, the variable capacitance elements C1 to C11 The ratio of the insulation resistance Rc to the resistance R of the bias lines B11, B12, B13, B14, B15, B21, B22, B23, B24, B25 is 100 or more, that is, the bias lines B11, B12, B13, B14, B15, The resistance components R11, R12, R13, R14, R15, R21, R22, R23, R24, and R25 of B21, B22, B23, B24, and B25 are set according to the insulation resistances Rc1, Rc2, Rc3, Rc4, Rc5, Rc6, Rc7, Rc8, Rc9, Rc10, and Rc11 must be 1/100 or less.

  From the results shown in FIGS. 10 and 11, the resistance components R11, R12, R13, R14 of the bias lines B11, B12, B13, B14, B15, B21, B22, B23, B24, B25 in the example shown in FIG. , R15, R21, R22, R23, R24, R25 have a size of 20 MΩ or more, and the insulation resistances Rc1, Rc2, Rc3, Rc4, Rc5, Rc6, Rc7, Rc8, Rc9, Rc10 of the variable capacitance elements C1 to C11, It may be 1/100 or less of Rc11. As a result, it becomes a variable capacitor with low waveform distortion and intermodulation distortion and excellent power resistance in the high frequency region of the GHz band which is actively used in the recent communication field, and about 95% of the applied DC bias. Can be applied to the variable capacitance elements C1 to C11, the capacitance can be changed more efficiently, and a desired capacitance value can be obtained.

  FIG. 12 and FIG. 13 show actual variable capacitor elements manufactured based on the example shown in FIG. 12 is a plan view showing a see-through state similar to FIG. 4, and FIG. 13 is a plan view in the middle of production similar to FIG.

  In these drawings, the same portions as those in FIGS. 4 and 5 are denoted by the same reference numerals, and description thereof will be omitted.

  In FIG. 12 and FIG. 13, C1 to C11 indicate an odd number of variable capacitance elements whose capacitance changes due to a DC bias. The bias line B11 is from the conductor lines 32 and 33 and the thin film resistor 61, the bias line B12 is from the conductor lines 32 and 34 and the thin film resistor 62, and the bias line B13 is from the conductor lines 32 and 35 and the thin film resistor 63 to the bias line. B14 is composed of conductor lines 32 and 36 and thin film resistor 64, and bias line B15 is composed of conductor lines 32 and 37 and thin film resistor 65, respectively. The bias line B11 is connected to the second variable capacitance element C2 and the third variable capacitance element C3 from an input terminal (solder terminal portion 111, solder diffusion prevention layer 10) which is an input terminal portion of the first variable capacitance element C1. A connection point, that is, is provided between the upper electrode layer 5 of the second variable capacitance element C2 and the lead electrode layer 8 that connects the upper electrode layer 5 of the third variable capacitance element C3. The same applies to the lines B12 to B15.

  The bias line B21 is from the conductor line 31 and the thin film resistor 66, the bias line B22 is from the conductor line 31 and the thin film resistor 67, the bias line B23 is from the conductor line 31 and the thin film resistor 68, and the bias line B24 is The bias line B25 includes the conductor line 31 and the thin film resistor 69, and the bias line B25 includes the conductor line 31 and the thin film resistor 70, respectively. The bias line B21 is a connection point between the third variable capacitor C3 and the fourth variable capacitor C4, that is, the common lower electrode layer 2 of the third variable capacitor C3 and the fourth variable capacitor C4. And the output terminal (solder terminal portion 112, solder diffusion prevention layer 10) which is the output terminal portion of the fifth variable capacitance element C5, and the same applies to the bias lines B22 to B25. .

  The variable capacitors of the examples shown in FIGS. 12 and 13 can be made to change greatly by applying a DC bias voltage by making the same as in the case of the examples shown in FIGS. As a result, the capacitance change, noise, and nonlinear distortion caused by the variable capacitor can be further reduced.

  FIG. 14 is a circuit diagram showing an example of an embodiment of the second variable capacitor of the present invention in the case where five variable capacitance elements are connected in series. In FIG. 14, C1, C2, C3, C4 and C5 are variable capacitive elements (first variable capacitive element C1, second variable capacitive element C2, third variable capacitive element C3, fourth variable capacitive element C4. The fifth variable capacitance element C5) has insulation resistances Rc1, Rc2, Rc3, Rc4, and Rc5. B11, B12, B21 and B22 are individual bias lines having at least one of a resistance component and an inductor component (in the figure, resistance components R11, R12, R21 and R22 are shown), and BI and BO are resistance components and A common bias line having at least one of the inductor components (in the figure, resistance components RI and RO are shown).

  In the example shown in FIG. 14, the application of the high-frequency signal and the DC bias voltage is made from a common terminal, where symbol I represents an input terminal and symbol O represents an output terminal.

  A series connection point of the input terminal portion of the first variable capacitance element C1 and the second variable capacitance element C2 to the third variable capacitance element C3, the fourth variable capacitance element C4 to the fifth variable capacitance element C5. Are provided with individual bias lines B11 and B12 having resistance components R11 and R12 through a common bias line BI having a resistance component RI.

  In addition, the series connection point of the output terminal portion of the fifth variable capacitance element C5 and the third variable capacitance element C3 to the fourth variable capacitance element C4, the first variable capacitance element C1 to the second variable capacitance element C2. Bias lines B21 and B22 having resistance components R21 and R22 are provided via a common bias line BO having a resistance component RO.

  In the example shown in FIG. 14, the resistance components R11, R12, R21, and R22 of the bias lines B11, B12, B21, and B22 are resistances larger than the impedance in the frequency domain of the high-frequency signal of the variable capacitors C1 to C5 connected in series. In order to cut off the high frequency signal, the high frequency signal passes through the variable capacitance elements C1 to C5 connected in series, and the DC bias voltage is independently applied to each of the variable capacitance elements C1 to C5.

  As a result, the DC bias voltage is applied independently to each of the variable capacitance elements C1 to C5, so that a variable capacitor in which an odd number of variable capacitance elements C1 to C5 are connected in parallel becomes a DC signal. The capacity change rate of each of the variable capacitance elements C1 to C5 can be utilized to the maximum. On the other hand, since the high frequency signal is cut off by the bias lines B11, B12, B21, B22, the variable capacitance elements C1 to C5 are variable capacitors connected in series in terms of high frequency. Therefore, since the high frequency voltage is divided into the variable capacitance elements C1 to C5, the capacitance change due to the high frequency signal can be reduced, and waveform distortion, intermodulation distortion, and the like can be suppressed.

  Here, if the resistance components R11, R12, R21, and R22 of the individual bias lines B11, B12, B21, and B22 are too small, the high-frequency signal also flows through the individual bias lines B11, B12, B21, and B22. The change becomes large, and the Q value is lowered when the phase is more than -90 °. On the other hand, if the resistance components R11, R12, R21, R22 of the individual bias lines B11, B12, B21, B22 and the resistance components RI, RO of the common bias lines BI, BO are too large, the variable capacitance elements C1 to C5 are divided by voltage division. The DC bias voltage applied to is reduced, and the capacitance change is reduced. Therefore, the resistance components R11, R12, R21, and R22 of the individual bias lines B11, B12, B21, and B22 and the resistance components RI and RO of the common bias lines BI and BO must be in an appropriate range. .

FIG. 15 is shown in FIG. 14 in order to set the lower limit values of the resistance components R11, R12, R21, R22 of the individual bias lines B11, B12, B21, B22 and the resistance components RI, RO of the common bias lines BI, BO. In the example, the insulation resistances of the variable capacitance elements C1 to C5 are Rc1 = Rc2 = Rc3 = Rc4 = Rc5 = 10 GΩ, RI = RO = R11 = R12 = R21 = R22 = R, and bias lines B11, B12, B21, B22, FIG. 10 is a diagram similar to FIG. 2 and FIG. 9 showing the result of the relationship between the magnitude of the resistance component of BI and BO and the phase obtained by simulation. Note that the 1.0E + 05 in FIG. 15, ¹⁰⁵ i.e. indicates 100k, and 1.0 E + 06, indicating a ¹⁰⁶ i.e. 1M.

  As shown in FIG. 15, it can be seen that as the resistance component R of the bias lines B11, B12, B21, B22, BI, BO increases, the phase approaches -90 ° even in the low frequency region. When the resistance value R of the bias lines B11, B12, B21, B22, BI, BO is 0.5 MΩ or more, the high frequency signal of 100 MHz or higher is substantially cut off, and the high frequency signal is biased by the bias lines B11, B12, B21, B22, BI. Therefore, the waveform distortion and the intermodulation distortion are small even in the high frequency region of the GHz band that is actively used in the recent communication field. In addition, the variable capacitor has excellent power resistance.

  Further, in the example shown in FIG. 1, the lower limit value can be reduced from 1 MΩ to 0.5 MΩ, compared with the case where the common bias lines BI and BO have no resistance component. This is because when the common bias lines BI and BO having resistance components are provided, the resistance components of the common bias lines BI and BO are distributed to the individual bias lines B11, B12, B21, and B22, and are supplied to the common bias lines BI and BO. This is because the resistance values of the bias lines B11, B12, B21, B22, BI, and BO can be made equal to {(number of individual bias lines) / 2} +1 times when there is no resistance component. In the case of manufacturing the element, it is effective for the restriction on the resistance values of the bias lines B11, B12, B21, B22, BI, and BO depending on the element shape and the like.

  FIG. 16 is a diagram for setting the upper limit values of the resistance components R11, R12, R21, R22 of the individual bias lines B11, B12, B21, B22 and the resistance components RI, RO of the common bias lines BI, BO. In the example shown in FIG. 4, the sum of the resistance component and the resistance component of the individual bias line when the resistance components of the common bias lines BI and BO are distributed to the individual bias lines B11, B12, B21, and B22, and the variable capacitance elements C1 to C1. The change in the DC bias voltage applied to each of the variable capacitance elements C1 to C5 with respect to the ratio of the insulation resistance Rc of C5 to the resistance value R of the bias lines B11, B12, B21, B22, BI, and BO is simulated. It is a diagram which shows the calculated | required result. Here, Rc1 = Rc2 = Rc3 = Rc4 = Rc5 = Rc, RI = RO = R ′, R11 = R12 = R21 = R22 = R, resistance component ratio Rc / (2R ′ + R), and each variable capacitance element The change in the ratio of the DC bias voltage applied to C1 to C5 was determined by simulation.

  According to the result shown in FIG. 16, the smaller the resistance component ratio Rc / (2R ′ + R), that is, the smaller the insulation resistance Rc of the variable capacitance elements C1 to C5, or the bias lines B11, B12, B21, B22, BI, It can be seen that the ratio of the DC bias voltage applied to each of the variable capacitance elements C1 to C5 decreases as the resistance of BO increases. Then, the insulation resistance Rc of the variable capacitance elements C1 to C5, the resistance component distributed to the individual bias lines B11, B12, B21, and B22 of the common bias lines BI and BO, and the individual bias lines B11, B12, B21, and B22. By setting the ratio Rc / R to the sum of the resistance components to 5 or more, the divided voltage of the DC bias voltage applied to the variable capacitance elements C1 to C5 is applied to the bias lines B11, B12, B21, B22, BI, BO. Since it is greater than the divided voltage of the applied DC bias voltage, more than half of the DC bias voltage applied between the input / output terminals I and O is applied to the variable capacitance elements C1 to C5, and a desired capacitance value is efficiently obtained. Obtainable. Furthermore, 95% or more of the DC bias voltage applied between the input / output terminals I and O is applied to the variable capacitance elements C1 to C5, and in order to obtain a desired capacitance value very efficiently, the variable capacitance elements C1 to C5 Ratio of the insulation resistance Rc to the total R of the resistance components distributed to the individual bias lines B11, B12, B21, B22 of the common bias lines BI, BO and the resistance components of the individual bias lines B11, B12, B21, B22 Rc / R is 100 or more, that is, the resistance components 2RI, 2RO distributed to the individual bias lines B11, B12, B21, B22 of the common bias lines BI, BO and the resistance components of the individual bias lines B11, B12, B21, B22 The sum of R11, R12, R21, and R22 needs to be 1/100 or less of the insulation resistances Rc1, Rc2, Rc3, Rc4, and Rc5 of the variable capacitance elements C1 to C5.

  From the results shown in FIGS. 15 and 16, the resistance components RI, RO, R11, R12, R21, and R22 of the common and individual bias lines BI, BO, B11, B12, B21, and B22 in the example shown in FIG. The size may be 0.5 MΩ or more.

  As a result, it becomes a variable capacitor with low waveform distortion and intermodulation distortion and excellent power resistance in the high frequency region of the GHz band that is actively used in the recent communication field, and 95% of the applied DC bias voltage. The above can be applied to the variable capacitance elements C1 to C5, and the capacitance can be changed more efficiently to obtain a desired capacitance value.

  On the other hand, the resistance component distributed to each individual bias line B11, B12, B21, B22 of the common bias line BI, BO depends on the number of variable capacitance elements C1 to C5 connected in series, that is, the number of individual bias lines. Different. However, like the second variable capacitor of the present invention, the insulation resistance Rc with the variable capacitance elements C1 to C5 and the resistance distributed to the individual bias lines B11, B12, B21, and B22 of the common bias lines BI and BO. By defining the ratio Rc / R of the component and the total R of the resistance components of the individual bias lines B11, B12, B21, and B22, regardless of the number of individual bias lines, that is, the variable capacitance elements connected in series Regardless of the number, the condition under which the DC bias voltage is more efficiently applied to the variable capacitance element can be determined.

  FIG. 17 is a diagram showing a simulation result indicating this, in which the number of variable capacitance elements connected in series is changed, and the other conditions are the same as those of the simulation in FIG. 16 described above. .

  As shown in FIG. 17, regardless of the number of variable capacitance elements connected in series, the insulation resistance Rc with the variable capacitance element, the resistance component distributed to each individual bias line of the common bias line, and the resistance of the individual bias line The condition for applying the DC bias voltage to the variable capacitance element more efficiently can be determined by the ratio Rc / R with the sum R of the components.

  18 and 19 show an actual variable capacitor element manufactured based on the example shown in FIG. 18 is a plan view in a transparent state similar to FIG. 4 and FIG. 12, and FIG. 19 is a plan view in the middle of production similar to FIG. 5 and FIG.

  In these drawings, the same parts as those in FIGS. 4, 12, 5 and 13 are denoted by the same reference numerals, and description thereof will be omitted.

  18 and 19, 1 is a support substrate, 2 is a lower electrode layer, 31, 32, 33, and 34 are conductor lines, 4 is a thin film dielectric layer, and 5 is an upper electrode layer. Yes, 61, 62, 63, 64, 65, 66 are thin film resistors, 7 is an insulating layer, 8 is a lead electrode layer, 9 is a protective layer, 10 is a solder diffusion prevention layer, 111 and 112 are solder terminal portions. The solder diffusion prevention layer 10 and the solder terminal portions 111 and 112 constitute an input terminal I and an output terminal O. In FIGS. 18 and 19, C1 to C5 indicate variable capacitance elements whose capacitance changes due to a DC bias.

  The support substrate 1 is a ceramic substrate such as alumina, or a single crystal substrate such as sapphire. Then, the lower electrode layer 2, the thin film dielectric layer 4, and the upper electrode layer 5 are sequentially formed on the entire surface of the support substrate 1 on the support substrate 1. After all the layers are formed, the upper electrode layer 5, the thin film dielectric layer 4, and the lower electrode layer 2 are sequentially etched into a predetermined shape.

  The lower electrode layer 2 needs to have a high melting point because high-temperature sputtering is required to form the thin film dielectric layer 4. Specifically, Pt, Pd (palladium) or the like. Further, the lower electrode layer 2 is heated to 700 to 900 ° C. which is the sputtering temperature of the thin film dielectric layer 4 after the sputtering is completed, and is held for a certain period of time until the sputtering of the thin film dielectric layer 4 is started. Become.

  The thickness of the lower electrode layer 2 is such that the resistance component from the output terminal (solder terminal portion 112, solder diffusion prevention layer 10) to the fifth variable capacitance element C5, or the first variable capacitance element C1 to the second variable capacitance element. Considering the continuity of the lower electrode layer 2 and the resistance component from C2, the third variable capacitor C3 to the fourth variable capacitor C4, the fifth variable capacitor C5 to the sixth variable capacitor C6 However, when considering the adhesion to the support substrate 1, it is desirable that the thickness is relatively thin. Specifically, the thickness is 0.1 μm to 10 μm. This is because if the thickness is less than 0.1 μm, the resistance of the lower electrode layer 2 itself increases, and the continuity of the lower electrode layer 2 may not be ensured. This is because there is a possibility that the adhesion with the substrate may be lowered or the support substrate 1 may be warped.

  The thin film dielectric layer 4 is preferably a high dielectric constant dielectric layer made of perovskite oxide crystal particles containing at least Ba, Sr, and Ti. The thin film dielectric layer 4 is formed on the surface of the lower electrode layer 2 described above. For example, using a dielectric material from which perovskite-type oxide crystal particles can be obtained as a target, sputtering is performed until a desired thickness is reached. By performing sputtering at a high substrate temperature, for example, 800 ° C., the low loss thin film dielectric layer 4 having a high dielectric constant and a large capacitance change rate can be obtained without performing a heat treatment after sputtering.

  The material of the upper electrode layer 5 is desirably Au having a low resistivity in order to reduce the resistance of the electrode. However, in order to improve the adhesion with the thin film dielectric layer 4, it is desirable to use Pt or the like as the adhesion layer. The thickness of the upper electrode layer 5 is 0.1 μm to 10 μm. The lower limit of the thickness is set in consideration of the resistance of the upper electrode layer 5 itself, similarly to the lower electrode layer 2. The upper limit of the thickness is set in consideration of adhesion.

  The individual bias line B11 is composed of conductor lines 32 and 33 and a thin film resistor 63, and is connected to the input terminal (solder terminal portion 111, solder diffusion prevention layer 10) which is the input terminal portion of the first variable capacitance element C1. The connection point between the second variable capacitance element C2 and the third variable capacitance element C3, that is, the upper electrode layer 5 of the second variable capacitance element C2 and the upper electrode layer 5 of the third variable capacitance element C3 are connected. It is provided between the extraction electrode layer 8. Similarly, the individual bias line B12 includes conductor lines 32 and 34 and a thin film resistor 64, and is connected between the input terminal I and the connection point between the fourth variable capacitor C4 and the fifth variable capacitor C5. Is provided.

  A common bias line BI is provided between the individual bias lines B11 and B12 and the input terminal I. The common bias line BI includes a conductor line 32 and a thin film resistor 61, and the individual bias lines B11 and B12 are connected in parallel to the input terminal I via the common bias line BI. .

  The individual bias line B21 includes a conductor line 31 and a thin film resistor 65, and is a connection point between the third variable capacitance element C3 and the fourth variable capacitance element C4, that is, the third variable capacitance element C3 and the third variable capacitance element C3. Provided between the common lower electrode layer 2 of the fourth variable capacitance element C4 and the output terminal (solder terminal portion 112, solder diffusion prevention layer 10) which is the output end of the fifth variable capacitance element C5. ing. Similarly, the individual bias line B22 is composed of a conductor line 31 and a thin film resistor 66, and is connected between the connection point between the first variable capacitance element C1 and the second variable capacitance element C2 and the output terminal O. Is provided.

  A shared common bias line BO is provided between the individual bias lines B21 and B22 and the output terminal O. The common bias line BO is composed of a conductor line 31 and a thin film resistor 62, and the individual bias lines B21 and B22 are connected in parallel to the input terminal I via the common bias line BO. .

  The conductor lines 31, 32, 33 and 34 can be obtained by forming a new film after forming the lower electrode layer 2, the thin film dielectric layer 4 and the upper electrode layer 5 described above. In that case, it is desirable to use a lift-off method. Further, it can be formed by patterning the lower electrode layer 2 into a shape having the conductor lines 31, 32, 33, 34 when patterning.

  As the material of the conductor lines 31, 32, 33, 34, Au having a low resistance is desirable in order to suppress variation in the resistance value of the bias line, but the resistance of the thin film resistors 61 to 66 is sufficiently high. You may form by the same material and the same process as lower electrode layers 2, such as Pt.

  Next, the material of the thin film resistors 61 to 66 constituting the bias lines B11, B12, B21, B22, BI, and BO preferably has a specific resistance of 1 Ωcm or more. By using such a high-resistance material, the device can be manufactured without increasing the shape of the device even when the bias lines B11, B12, B21, B22, BI, and BO are provided, and the device can be miniaturized and integrated. It will be advantageous. Specific examples of the thin film resistors 61 to 66 include tantalum nitride, TaSiN, and Ta—Si—O. For example, in the case of tantalum nitride, a resistive film having a desired composition ratio and resistivity can be formed by a reactive sputtering method in which Ta is used as a target and nitrogen is added to perform sputtering. By appropriately selecting the sputtering conditions, a resistance film having a specific resistance of 1 Ωcm or more can be produced. Furthermore, after the sputtering is completed, a resist is applied and formed into a predetermined shape, and then can be easily patterned by an etching process such as reactive ion etching (RIE).

  In the variable capacitor of the example shown in FIG. 18, the resistance components of the bias lines B11, B12, B21, B22, BI, and BO block high-frequency signals of 100 MHz or more, and the insulation resistance of the variable capacitors C1 to C5. In order to make the magnitude 1/100 or less, the resistance values of the thin film resistors 61 to 66 need to be 0.5 MΩ or more as described above. When a material having a specific resistance of 1 Ωcm or more is used as a material for the thin film resistors 61 to 64, the film thickness is 40 nm and the aspect ratio (length / width) is 2 or more in order to realize the resistance value. The thin film resistors 61 to 66 having an aspect ratio that can be realized without increasing the element shape can be manufactured.

  Bias lines B11, B12, B21, B22, BI, and BO including these thin film resistors 61 to 66 are directly formed on the support substrate 1. As a result, an insulating layer for securing insulation from the lower electrode layer 2, the upper electrode layer 5, and the lead electrode layer 8, which is required when the thin film resistors 61 to 64 are formed on the variable capacitance elements C1 to C5, is provided. This is unnecessary, and the number of layers constituting the variable capacitor can be reduced.

  Next, the insulating layer 7 is necessary for ensuring insulation between the lead electrode layer 8 and the lower electrode layer 2 formed thereon. Furthermore, since this insulating layer 7 covers the bias lines B11, B12, B21, B22, BI, and BO and can prevent the thin film resistors 61 to 66 from being oxidized, the bias lines B11, B12, B21, The resistance values of B22, BI, and BO can be made constant over time, and the reliability is improved. In order to improve moisture resistance, the material of the insulating layer 7 may be made of, for example, at least one of silicon nitride and silicon oxide. These films are preferably formed by a chemical vapor deposition (CVD) method or the like in consideration of coverage.

  The insulating layer 7 can be formed into a desired shape by a dry etching method using a normal resist. The insulating layer 7 is provided with a through hole that exposes a part of the conductor lines 33 and 34 in order to secure the coupling between the thin film resistors 61 and 62 and the lead electrode layer 8. In addition, it is preferable that only the upper electrode layer 5 and the solder terminal portions 111 and 112 be exposed from the insulating layer 7 from the viewpoint of improving moisture resistance.

  Next, the lead electrode layer 8 connects the upper electrode layer 5 of the first variable capacitance element C1 and one terminal forming portion 111 or the upper electrode layers 5 to form a terminal of the first variable capacitance element C1. The second variable capacitance element C2 and the third variable capacitance element C3, and the fourth variable capacitance element C4 and the fifth variable capacitance element C5 are connected in series while being connected to the unit 111. Further, the lead electrode layer 8 extending over each of C2 and C3 and C4 and C5 is coupled to the conductor lines 33 and 34 through the through holes of the insulating layer 7, respectively.

  As the material of the extraction electrode layer 8, it is desirable to use a low resistance metal such as Au or Cu. In consideration of adhesion with the insulating layer 7, an adhesion layer such as Ti or Ni may be used.

  Next, the protective layer 9 is formed. The protective layer 9 mechanically protects the device from the outside and protects it from contamination by chemicals. When the protective layer 9 is formed, the solder terminal portions 111 and 112 are exposed. As a material of the protective layer 9, a material having high heat resistance and excellent coverage with respect to a step is preferable. Specifically, polyimide resin, BCB (benzocyclobutene) resin, or the like is used.

  The solder diffusion preventing layer 10 is formed to prevent diffusion of solder to the electrodes during reflow or mounting when forming the solder terminal portions 111 and 112. Ni is suitable as the material. In addition, in order to improve solder wettability, Au, Cu, etc. having high solder wettability may be formed on the surface of the solder diffusion preventing layer 10 to about 0.1 μm.

  Finally, solder terminal portions 111 and 112 are formed. This is formed to facilitate mounting. It is generally formed by printing a solder paste on the solder diffusion preventing layer 10 and then performing reflow.

  As described above, according to the present invention, while the capacity change rate due to the DC bias voltage is increased, the capacity change rate due to the high-frequency signal is small, the intermodulation distortion is small, the power resistance is excellent, and the usable frequency region. And a variable capacitor that can be integrated in a small size.

  Next, a more specific embodiment of the variable capacitor of the present invention will be described. As an example, the second variable capacitor of the present invention shown in FIGS. 18 and 19 will be described as an example.

  The number of variable capacitance elements connected in series was five, and was manufactured as follows.

On the sapphire R substrate as the support substrate 1, Pt was deposited as the lower electrode layer 2 by sputtering at a substrate temperature of 500 ° C. A target made of (Ba _0.5 Sr _0.5 ) TiO ₃ was used as the thin film dielectric layer 4, the substrate temperature was 800 ° C., the film formation time was 15 minutes, and the films were formed in the same batch. Before the film formation was started, the annealing was performed at 800 ° C. for 15 minutes as an annealing for planarizing the Pt electrode. On top of this, Pt was deposited in the same batch as the upper electrode layer 5. Next, after applying a photoresist and processing the photoresist into a predetermined shape by a photolithography technique, the upper electrode layer 5 was etched by an ECR apparatus. Thereafter, the thin film dielectric layer 4 and the lower electrode layer 2 were similarly etched. The shape of the lower electrode layer 2 includes conductor lines 31 to 34. Next, tantalum nitride was deposited at 100 ° C. by sputtering as thin film resistors 61-66. After sputtering, the photoresist was formed into a predetermined shape by photolithography, and then etched using an RIE apparatus to remove the photoresist layer. The aspect ratios of the thin film resistors 61 to 66 were all 2.5.

Next, as the insulating layer 7, a SiO ₂ film was formed by a CVD apparatus using TEOS gas as a raw material. After processing the resist, it was etched into a predetermined shape by an RIE apparatus.

  Next, as the extraction electrode layer 8, Pt and Au were formed by sputtering and processed into a predetermined shape.

  Finally, the protective layer 9, the solder diffusion preventing layer 10, and the solder terminal portions 111 and 112 were sequentially formed. The protective layer 9 was made of polyimide resin, and the solder diffusion preventing layer 10 was made of Ni.

  The film thickness of the thin film resistors 61 to 66 was 43 nm, and the sheet resistance value was separately measured at room temperature of 25 ° C., and as a result, it was 510 kΩ / □. Thus, it was confirmed that the specific resistance of the thin film resistors 61 to 66 was about 2 Ωcm, and the resistance value of the thin film resistors 61 to 66 was 1.2 MΩ. Further, the total of the resistance distributed to the individual bias lines B11, B12, B21, and B22 of the common bias lines BI and BO and the resistance of the individual bias lines B11, B12, B21, and B22 is 3.5 MΩ.

  Furthermore, when the insulation resistances of the variable capacitance elements C1 to C5 were measured at the same atmospheric temperature, the insulation resistance value when DC 3 V was applied was 1 GΩ.

  Therefore, since the total of the resistance distributed to the individual bias lines B11, B12, B21, and B22 of the common bias lines BI and BO and the resistance of the individual bias lines B11, B12, B21, and B22 is 3.5 MΩ, DC3V is applied. The insulation resistance value at that time was 1/285 of 1 GΩ, which was 1/100 or less.

  The resistance value of the element was measured by changing the ambient temperature. In the case of −30 ° C., the total resistance value of the bias lines B11, B12, B21, and B22 was 7.8 MΩ, and the insulation resistance values of the variable capacitance elements C1 to C5 when DC 3 V was applied were 5 GΩ. In this case, the ratio Rc / R of both resistance values was 1/641, which was 1/100 or less.

  When the ambient temperature is 85 ° C., the total resistance value Rc of the bias lines B11, B12, B21, B22, BI and BO is 1.5 MΩ, and the insulation resistance values R of the variable capacitors C1 to C5 when DC3V is applied. Was 0.25 GΩ. In this case, the ratio Rc / R of both resistance values was 1/166, which was 1/100 or less.

  Within the operating temperature range, the insulation resistance Rc of the variable capacitance elements C1 to C5 and the resistances of the bias lines B11, B12, B21, B22, BI, BO all decrease as the temperature rises, and the ratio Rc / R was 1/100 or less. Therefore, the DC bias voltage applied to the variable capacitance elements C1 to C5 is 99% of the supply voltage at −30 ° C., 98% at 25 ° C., and 97% at 85 ° C., respectively. It was possible to make it almost equal within the operating temperature range.

  As described above, also in the present embodiment, while the variable capacitor of the present invention increases the capacitance change rate due to the DC bias voltage, the capacitance change rate due to the high frequency signal is small, the intermodulation distortion is small, and the power resistance is excellent. In addition, it was confirmed that the usable frequency range was wide and small integration was possible.

It is a circuit diagram showing an example of an embodiment of a first variable capacitor of the present invention in which five variable capacitance elements are connected in series. It is a phase characteristic figure in the example shown in FIG. It is an applied voltage characteristic figure in the example shown in FIG. It is a top view of the see-through state which shows an example of embodiment of the 1st variable capacitor of this invention in which five variable capacitance elements were connected in series. It is a top view which shows the state in the middle of preparation of an example of 1st Embodiment of the 1st variable capacitor of this invention in which five variable capacitance elements were connected in series. FIG. 5 is a cross-sectional view taken along line A-A ′ of FIG. 4. FIG. 5 is a sectional view taken along line B-B ′ of FIG. 4. FIG. 5 is a sectional view taken along line C-C ′ of FIG. 4. It is a circuit diagram which shows an example of embodiment of the 1st variable capacitor of this invention in which 11 variable capacitance elements were connected in series. FIG. 10 is a phase characteristic diagram in FIG. 9. It is an applied voltage characteristic view in FIG. It is a top view of the see-through state which shows an example of embodiment of the 1st variable capacitor of this invention to which 11 variable capacitance elements were connected in series. It is a top view which shows the state in the middle of preparation of an example of 1st Embodiment of the 1st variable capacitor of this invention with which 11 variable capacitance elements were connected in series. FIG. 5 is a circuit diagram showing an example of an embodiment of a second variable capacitor of the present invention having a common bias line in which five variable capacitance elements are connected in series. FIG. 15 is a phase characteristic diagram in FIG. FIG. 15 is a characteristic diagram of applied voltage in FIG. It is an applied voltage characteristic view in the 3rd example of an embodiment of the 2nd variable capacitor of the present invention which has a common bias line connected in series with 5, 11, and 15 variable capacity elements. It is a top view of the see-through state which shows an example of the embodiment of the 2nd variable capacitor of the present invention which has a common bias line where five variable capacity elements were connected in series. It is a top view which shows the state in the middle of preparation of an example of 2nd variable capacitor | condenser of this invention which has a common bias line in which five variable capacitance elements were connected in series. It is sectional drawing which shows the example of the conventional thin film capacitor.

Explanation of symbols

1 ... support substrate 2 ... lower electrode layer
31, 32, 33, 34, 35, 36, 37 ... conductor line 4 ... thin film dielectric layer 5 ... upper electrode layer
61, 62, 63, 64, 65, 66, 67, 68, 69, 70 ... thin film resistor 7 ... insulator layer 8 ... extraction electrode layer 9 ... protective layer
10 ... Solder diffusion prevention layer
111, 112... Solder terminals C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11... Variable capacitance elements B11, B12, B13, B14, B15. Or individual bias lines B21, B22, B23, B24, B25... Bias lines or individual bias lines BI, BO... Common bias lines R11, R12, R13, R21, R22, R23, RI, RO. Line resistance component Rc1, Rc2, Rc3, Rc4, Rc5, Rc6, Rc7, Rc8, Rc9, Rc10, Rc11 ... Insulation resistance of variable capacitance element I ... Input terminal O ... Output terminal

Claims (4)

A variable capacitor comprising a plurality of variable capacitance elements that are connected in series and whose capacitance is changed by a DC bias voltage, and a bias line that is connected to each of these variable capacitance elements and applies the DC bias voltage, The bias line has at least one of a resistance component and an inductance component, and has a size such that the resistance component and the inductance component block a high-frequency signal, and a voltage division of the DC bias voltage applied to the bias line is variable. A variable capacitor, wherein the resistance value of the bias line is smaller than a divided voltage of the DC bias voltage applied to a capacitive element, and decreases as the temperature increases. The resistance component of the bias line cuts off a high frequency signal of 100 MHz or more and has a magnitude of 1/100 or less of an insulation resistance of the variable capacitance element within a use temperature range. The variable capacitor described. A plurality of variable capacitance elements that are connected in series and whose capacitance is changed by a DC bias voltage, an individual bias line that is connected to each of these variable capacitance elements and that applies the DC bias voltage, and is connected to these individual bias lines. The common bias line and the individual bias line have at least one of a resistance component and an inductance component, and the resistance component and the inductance component are large enough to block high-frequency signals. And the divided voltage of the DC bias voltage applied to the common bias line and the individual bias line is smaller than the divided voltage of the DC bias voltage applied to the variable capacitance element, the common bias line and the individual bias line. The resistance value of temperature is Variable capacitor, characterized in that down with want. The resistance component of the common bias line and the individual bias line blocks a high frequency signal of 100 MHz or more, and the resistance component distributed to the individual bias line of the common bias line within the operating temperature range and the individual bias line. The variable capacitor according to claim 3, wherein the sum of the resistance component and the resistance component is 1/100 or less of the insulation resistance of the variable capacitance element.

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