JP2008211064A - Variable-capacity capacitor array and variable-capacity capacitor relay - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a variable-capacity capacitor array that is excellent in controllability of a capacity value and has no change in tunability, and a variable-capacity capacitor relay. <P>SOLUTION: The variable-capacity capacitor array is provided with a plurality of variable-capacity capacitor strings and a common signal terminal connected with each first terminal of a plurality of the variable-capacity capacitor strings. Each variable-capacity capacitor string is provided with a variable-capacity capacitor and an individual signal terminal connected to a second terminal of the variable-capacity capacitor. The variable-capacity capacitor is configured so that a plurality of variable-capacity elements are connected between a first terminal and a second terminal in series, and also, each first individual bias line and each second individual bias line are alternately connected to the following connection points in turn from the first terminal side, that is, a connection point between the first terminal and the first variable-capacity element from the first terminal, a connection point between each variable-capacity element, and a connection point between the second terminal and the first variable-capacity element from the second terminal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a variable capacitor array using a variable capacitor whose capacitance changes greatly by application of a DC bias voltage, and a variable capacitor relay using the same.

As a variable capacitor, in a structure in which a thin film lower electrode layer, a thin film dielectric layer, and a thin film upper electrode layer are laminated in this order on a support substrate having electrical insulation, titanic acid is used as a material for the thin film dielectric layer. barium strontium _{((Ba x Sr 1-x} ) y Ti 1-y O 3-z) ( hereinafter, also referred to as BST. However, y <1) with a dielectric material consisting of an upper and lower electrode layers Is known in which a predetermined bias potential is applied to change the capacitance of the thin film dielectric layer to change the capacitance (see, for example, Patent Document 1).

  Such a capacitance change in the variable capacitor extends to the high frequency region and can be used in the high frequency region. A useful electronic component capable of changing the frequency characteristics can be obtained by utilizing the capacitance change of the variable capacitor in the high frequency region due to the application of the DC bias voltage.

  For example, in a voltage controlled thin film resonator in which the above-described variable capacitor and thin film inductor are combined, the resonance frequency can be changed by applying a DC bias voltage. In addition, in a voltage controlled thin film bandpass filter that combines a variable capacitor or voltage controlled thin film resonator, a thin film inductor, and a thin film capacitor, the passband can be changed by applying a DC bias voltage. The variable capacitor can also be used for a voltage-controlled electronic component for microwaves (see, for example, Patent Document 2).

  In such a variable capacitor using a high dielectric constant thin film, in addition to high tunability and high Q value, there are high power durability, high insulation, low distortion characteristics, low temperature coefficient, and change with time. There is no need for it. The tunability indicates the variable amount of the variable capacitor, and is represented by the formula of tunability x = (C (0) −C (V)) / C (0) × 100 (%) ( Here, C (0) is a capacity before application of voltage (initial capacity), and C (V) is a capacity after application of voltage).

In addition, as the variable capacitor, a plurality of variable capacitors having the same configuration as the above-described variable capacitor are connected in series, and each variable capacitor is provided with a bias line for applying a DC bias voltage. Proposed. As a result, a DC bias voltage can be stably and uniformly applied to each variable capacitance element, and a high frequency voltage (high frequency signal) can be divided into individual variable capacitance elements. For this reason, a change in capacitance due to a DC bias voltage can be increased, a change in capacitance due to a high-frequency signal, noise, and non-linear distortion can be suppressed, and a variable capacitor having excellent power resistance can be obtained (for example, (See Patent Document 3).
JP-A-11-260667 JP-T 8-509103 JP 2004-165588 A

  The inventor pays attention to the high capacitance change rate, low distortion characteristics, high power durability, and the like of the variable capacitor shown in Patent Document 3 described above, and uses them as electronic components constituting a circuit that propagates a high-frequency signal. I tried to do that. For this purpose, it is necessary to set the initial capacitance value over a wide range and to have a high degree of design freedom in order to cope with a wide variety of applications.

  The present invention has been devised in view of the above circumstances. An object of the present invention is to provide a variable capacitor array and a variable capacitor array that have a desired tunability and can set an initial capacitance value to a desired value. It is to provide a capacitive capacitor relay.

  In the variable capacitor array of the present invention, 1) a plurality of variable capacitors are connected in series between a first terminal and a second terminal, and the first terminal counted from the first terminal and the first terminal is The connection points between the variable capacitance elements, the connection points between the variable capacitance elements, and the connection points between the first variable capacitance element and the second terminal counted from the second terminal are sequentially arranged from the first terminal side. A variable capacitor in which one individual bias line and a second individual bias line are alternately connected; an individual signal terminal connected to the second terminal; a plurality of variable capacitor strings each having; And a common signal terminal to which the first terminals of the variable capacitor string are connected in common.

  Further, the variable capacitor array of the present invention includes 2) a first bias terminal to which a plurality of the first individual bias lines are commonly connected for one of the variable capacitor strings in the configuration of 1) above, The variable capacitor string further includes a second bias terminal to which a plurality of the second individual bias lines are connected in common.

  The variable capacitor array according to the present invention is 3) In the configuration of 1), the variable capacitor array further includes a common bias terminal, and the plurality of variable capacitor strings include the first individual bias line and the second individual bias. A first variable capacitor capacitor string in which one of the lines is connected to the common bias terminal, and a second variable capacitor in which one of the first individual bias line and the second individual bias line is connected to the common bias terminal. And a capacitor string.

  The variable capacitor array of the present invention may further include 4) a common bias terminal in the configuration of 2), wherein the plurality of variable capacitor strings are formed of the first bias terminal and the second bias terminal. A first variable capacitor capacitor string, one of which is connected to the common bias terminal; a second variable capacitor capacitor string of which one of the first bias terminal and the second bias terminal is connected to the common bias terminal; Is included.

  In the variable capacitor array of the present invention, 5) in the configuration of 2), the variable capacitor includes an odd number of the variable capacitors, and the plurality of variable capacitor strings include the first bias terminal. Is shared with the common signal terminal, the second bias terminal is shared with the individual signal terminal, the first variable capacitor capacitor string, the first bias terminal is shared with the common signal terminal, and the second bias terminal Includes a second variable capacitor string shared by the individual signal terminals.

  In addition, the variable capacitor relay of the present invention is characterized in that a plurality of variable capacitor capacitor arrays having any of the configurations 2) to 5) are connected.

  According to the variable capacitor array and the variable capacitor relay of 1) to 6) of the present invention, at least two arbitrary ones among the common signal terminal and the individual signal terminal provided for each variable capacitor string. By using these terminals as input terminals and output terminals, the initial capacitance value can be adjusted to a desired value as described below. In this case, since the bias voltage is applied to each variable capacitance element, the maximum capacitance can be changed, and the tunability does not change regardless of how the input and output terminals are selected in the variable capacitance capacitor array. Therefore, a constant value can be maintained.

  For example, when the common signal terminal is an input terminal and the individual signal terminal provided for each variable capacitor string is an output terminal, each variable capacitor is connected in parallel in multiple rows, increasing the initial capacitance value. can do. Further, the degree of freedom in selecting the initial capacitance value is increased by the method for selecting the output terminal from the plurality of individual signal terminals, and a variable capacitor array having a desired initial capacitance value can be obtained. If the individual signal terminals are connected via an external switching element, the initial capacitance value can be selected more easily. Note that the input terminal and the output terminal may be interchanged.

  Further, when two variable capacitor strings are used and the individual signal terminals are respectively input / output terminals, two variable capacitor strings are connected in series, and the initial capacitance value can be reduced. Furthermore, since the first individual bias line and the second individual bias line are connected to each variable capacitance element, the variable capacitance elements are connected in parallel in terms of DC. Therefore, since a bias voltage is applied to each variable capacitance element, it is possible to provide a variable capacitance capacitor array in which the capacitance can be changed to the maximum and the tunability is kept constant.

  Further, by providing a common bias terminal, a first bias terminal, and a second bias terminal that electrically connect the first and second individual bias lines, it is possible to apply a bias voltage to each variable capacitance element at once. Since the bias voltage can be applied with a simple configuration, handling becomes easy.

  Further, by using the variable capacitor array and the variable capacitor relay as a part of the high frequency voltage controlled resonator of the present invention (as a part of the resonance circuit) or as a means for coupling the resonance circuits to each other, This means that a resonator is made using a variable capacitor array that has variable capacitance elements connected in series and connected in parallel in direct current, with low waveform distortion and intermodulation distortion noise, and withstands power. An electronic component that is an excellent voltage-controlled resonator for high frequency can be realized. Similarly, voltage-controlled high-frequency filters and antenna duplexers equipped with a resonance circuit produce voltage-controlled high-frequency filters and antenna duplexers with low waveform distortion and intermodulation distortion noise and excellent power durability. can do.

  Hereinafter, the variable capacitor array of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is an equivalent circuit diagram showing a first embodiment of the present invention.

  In FIG. 1, symbols C1 to C6 are variable capacitance elements, and B11 to B14 are first individual bias lines including at least one of a resistance component and an inductor component (in FIG. 1, the resistance components R11 to R14 are included). B21 to B24 are second individual bias lines (including resistance components R21 to R24 in FIG. 1) including at least one of a resistance component and an inductor component. P1a and P1b are first terminals, P2a and P2b are second terminals, Sa and Sb are individual signal terminals, and CS1 is a common signal terminal. The same applies to the following drawings, but the same portions are denoted by the same reference numerals, and redundant description is omitted.

  The variable capacitance elements C1 to C3 are connected in series between the first terminal P1a and the second terminal P2a, and the variable capacitance elements C4 to C6 are connected in series between the first terminal P1b and the second terminal P2b, respectively. Construct a capacitor. The individual signal terminal Sa is connected to the second terminal P2a of the variable capacitor, and the individual signal terminal Sb is connected to the second terminal P2b to constitute a variable capacitor string. Hereinafter, for convenience, they are referred to as a first variable capacitor string and a second variable capacitor string. The first terminal P1a of the first variable capacitor string and the first terminal P1b of the second variable capacitor string are commonly connected to the common signal terminal CS1. Further, the first variable capacitor string is connected between the first terminal P1a and the first variable capacitor C1 counted from the first terminal P1a, between the variable capacitors C2 and C3, and from the second terminal P2a to 1. The first individual bias lines B11 and B12 and the second individual bias lines B21 and B22 are alternately connected in order from the first terminal P1a side between the variable variable element C3 and the second terminal P2a. Similarly, in the second variable capacitor string, the first individual bias lines B13 and B14 and the second individual bias lines B23 and B24 are connected between the first terminal P1b and the second terminal P2b. In this way, the variable capacitor array is configured.

  High-frequency signals flow between the first terminals P1a and P1b and the second terminals P2a and P2b via the variable capacitance elements C1 to C3 and C4 to C6. At this time, the resistance components R11 to R14 and R21 to R24 of the first and second bias lines B11 to B14 and B21 to B24 are impedance components that are large with respect to the impedance in the frequency domain of the high frequency signal of the variable capacitance elements C1 to C6. And does not adversely affect the impedance of the high frequency band. Further, the high frequency signal does not leak to the bias lines B11 to B14 and B21 to B24.

  A bias signal for controlling the capacitance component of the variable capacitance element C1 flows between the first individual bias line B11 and the second individual bias line B21 via the variable capacitance element C1. Due to the voltage applied to the variable capacitance element C1, the variable capacitance element C1 has a dielectric constant corresponding to the voltage, and as a result, a desired capacitance component can be obtained. That is, a bias signal for controlling the capacitance of the variable capacitance element C1 to a desired value can be stably supplied only to the variable capacitance element C1, and the dielectric constant of the variable capacitance element C1 varies as desired by applying the bias signal. Therefore, the variable capacitance element can be easily controlled in the capacitance component. Similarly, the capacitance components of the variable capacitance elements C2 to C6 can be controlled.

  In this variable capacitor array, the initial capacitance value can be adjusted to a desired value by selecting at least two of the individual signal terminals Sa and Sb and the common signal terminal CS1 as input terminals and output terminals.

  For example, when the common signal terminal CS1 is an input terminal and the individual signal terminals Sa and Sb are output terminals, each variable capacitor is connected in parallel in two rows, and the initial capacitance value can be increased. Further, if the switching elements are connected to the individual signal terminals Sa and Sb and then both are electrically connected, the initial capacitance value can be further freely adjusted.

  Further, when the individual signal terminals Sa and Sb are used as the input terminal and the output terminal, the variable capacitance elements C1 to C6 are connected in series, and the initial capacitance value can be reduced.

  As described above, since a plurality of initial capacitance values can be obtained with one variable capacitor array by the method of selecting input / output terminals from the terminals (Sa, Sb, CS1) of the variable capacitor array, the degree of freedom in design. Can be high.

  Next, FIG. 2 shows an equivalent circuit diagram of the second embodiment of the present invention.

  The variable capacitor array shown in FIG. 2 is different from the variable capacitor array shown in FIG. 1 in the application method of the bias voltage. Specifically, a first bias terminal formed for each first individual bias line and a second bias terminal formed for each second individual bias line of the first and second variable capacitor strings are further provided. Provided. Thus, for each of the plurality of variable capacitor capacitor strings, a bias terminal for commonly connecting a plurality of first individual bias lines and a second bias terminal for commonly connecting a plurality of second individual bias lines are provided. Also good. Further, the first bias terminal and the second bias terminal need not be provided in all of the plurality of variable capacitor strings, and may be provided in at least one variable capacitor string.

  In FIG. 2, the first bias terminal is V1 (V1a, V1b), and the second individual bias terminal is V2 (V2a, V2b). Here, the first individual bias lines B11 and B12 of the first bias string are connected to the first bias terminal V1a, and the second individual bias lines B21 and B22 are connected to the second bias terminal V2a. The first individual bias lines B13 and B14 of the second bias string are connected to the first bias terminal V1b, and the second individual bias lines B23 and B24 are connected to the second bias terminal V2b.

  By connecting in this way, the variable capacitance elements C1 to C3 and C4 to C6 are connected in parallel in a direct current manner between the first bias terminal V1 and the second bias terminal V2. Therefore, a bias voltage equal to the potential difference between the first bias terminal V1 and the second bias terminal V2 is applied to each of the variable capacitance elements C1 to C6. As a result, the capacitance of each of the variable capacitance elements C1 to C6 can be changed to the maximum, and the tunability can be kept constant regardless of the connection method of the input / output terminals of the high frequency signal.

  In addition, with such a configuration, since a terminal for applying a bias voltage can be shared, a variable capacitor array that can be handled more easily can be obtained.

  Next, FIG. 3 shows an equivalent circuit diagram of an example of the third embodiment of the present invention.

  The variable capacitor array shown in FIG. 3 differs from the variable capacitor array shown in FIG. 1 in the application method of the bias voltage. Specifically, a common bias terminal is further provided, and one of the first individual bias line and the second individual bias line of the first and second variable capacitor string is connected to the common bias terminal.

  In FIG. 3, the common bias terminal is V3. Here, the second individual bias lines B21 to B24 of the first and second variable capacitor strings are electrically connected to the common bias terminal V3.

  By connecting in this way, the variable capacitance elements C1 to C3 and C4 to C6 are direct current between the common bias terminal V3, the second individual bias lines B21 to B24, and the first individual bias lines B11 to B14. Are connected in parallel. Therefore, a bias voltage equal to the potential difference between the common bias terminal V3 and the first individual bias line is applied to each of the variable capacitance elements C1 to C6. As a result, the capacitance of each of the variable capacitance elements C1 to C6 can be changed to the maximum, and the tunability can be kept constant regardless of the connection method of the input / output terminals of the high frequency signal.

  In addition, with such a configuration, since a terminal for applying a bias voltage can be shared, a variable capacitor array that can be handled more easily can be obtained. In particular, if the first individual bias lines B11 to B14 are grounded, the bias voltage only needs to be applied to the common bias terminal V3, so that the configuration becomes simple and the handling becomes easy.

  Next, FIG. 4 shows an equivalent circuit diagram of an example of the fourth embodiment of the present invention.

  The variable capacitor array shown in FIG. 4 is different from the variable capacitor array shown in FIG. 2 in the application method of the bias voltage. Specifically, a common bias terminal is further provided, and one of the first bias terminal and the second bias terminal of the first and second variable capacitor strings is connected to the common bias terminal.

  In FIG. 4, the second bias terminals V2a and V2b of the first and second variable capacitor strings are connected to the common bias terminal V3.

  By connecting in this way, the variable capacitance elements C1 to C3 and C4 to C6 are connected in parallel in a direct current manner between the common bias terminal V3 and the first bias terminals V1a and V1b. Therefore, a bias voltage equal to the potential difference between the common bias terminal V3 and the first bias terminal V1 is applied to each of the variable capacitance elements C1 to C6. As a result, the capacitance of each of the variable capacitance elements C1 to C6 can be changed to the maximum, and the tunability can be kept constant regardless of the connection method of the input / output terminals of the high frequency signal.

  In addition, with such a configuration, since a terminal for applying a bias voltage can be shared, a variable capacitor array that can be handled more easily can be obtained.

  5 and 6 are equivalent circuit diagrams showing modifications of the variable capacitor array shown in FIG.

  In FIG. 4, the second bias terminals V2a and V2b of the first and second variable capacitor strings are connected to the common bias terminal V3. However, as shown in FIG. 5, the second bias terminals of the first variable capacitor string are used. V2a may be connected to the first bias terminal V1b of the second variable capacitor string, and as shown in FIG. 6, the first bias terminal V1a of the first variable capacitor string and the second variable capacitor string The second bias terminal V2b may be connected, or the first bias terminals V1a and V1b of the first and second variable capacitor strings may be connected.

  In the example shown in FIGS. 1 to 6 above, an example in which an odd number (three) of variable capacitance elements are connected in series to a variable capacitance capacitor has been described. However, as shown in FIG. 4) variable capacitance elements may be connected in series.

  Further, the example in which the variable capacitors having the same number of variable capacitors are used in the first and second variable capacitor strings has been described. However, as shown in FIG. Three variable capacitors may be connected (three connected to the variable capacitors and four connected to the second variable capacitors).

  Furthermore, although the example of the variable capacitor array including the two variable capacitor strings of the first and second variable capacitor strings has been described, three or more variable capacitor strings may be connected to the common signal terminal.

  Next, FIG. 9 shows an equivalent circuit diagram of an example of the fifth embodiment of the present invention.

  The variable capacitor array shown in FIG. 9 is different from the variable capacitor array shown in FIG. 2 in the application method of the bias voltage. Specifically, in the first and second variable capacitor string, the first bias terminal is shared with the common signal terminal, and the second bias terminal is shared with the individual signal terminal. With such a configuration, at least two signal terminals selected as high-frequency signal input / output terminals out of the common signal terminal and the two individual signal terminals also serve as terminals for applying a bias voltage. And DC voltage (bias voltage) are applied in a superimposed manner.

  In FIG. 9, the first bias terminals V1a and V1b and the common signal terminal CS1 of the first and second variable capacitor strings are shared (shared) by being electrically connected. The second bias terminal V2a and the individual signal terminal Sa of the string are shared (shared) by being electrically connected, and the second bias terminal V2b and the individual signal terminal Sb of the second variable capacitor string are electrically connected. Is shared (shared) by being connected. Such a configuration can be realized when the variable capacitor includes an odd number of variable capacitors.

  Furthermore, in the example shown in FIG. 2, the example in which the resistance components R11 to R14 and R21 to R24 are provided in the first and second individual bias lines B11 to B14 and B21 to B24, respectively, has been described. On the other hand, in FIG. 9, one resistance component R1a is used in the first individual bias lines B11 and B12 of the first variable capacitor string. Similarly, one resistance component R1b, R2a, R2b is used for the first individual bias lines B13, B14, the second individual bias lines B21, B22, and the second individual bias lines B23, B24, respectively.

  In such a configuration, the bias voltage is applied as follows. First, the variable capacitance element C1 flows from the common signal terminal CS1 (V1) to the individual signal terminal Sa (V2a) through the second individual bias lines B21 and B22 via the variable capacitance element C1. The variable capacitance element C2 passes through the first individual bias lines B11 and B12 from the common signal terminal CS1 (V1), passes through the second individual bias lines B21 and B22 via the variable capacitance element C2, and passes through the individual signal terminal Sa. It flows to (V2a). The variable capacitance element C3 flows from the common signal terminal CS1 (V1) to the individual signal terminal Sa (V2a) through the first individual bias lines B11 and B12 and the variable capacitance element C3. The same applies to the variable capacitance elements C4 to C6. Therefore, the variable capacitance elements C1 to C3 and C4 to C6 are connected in parallel in a direct current manner between the common signal terminal CS1 (V1) and the individual signal terminals Sa and Sb (V2). Therefore, a bias voltage equal to the potential difference between the common signal terminal CS1 (V1) and the individual signal terminals Sa and Sb (V2) is applied to each of the variable capacitance elements C1 to C6. As a result, the capacitance of each of the variable capacitance elements C1 to C6 can be changed to the maximum, and the tunability can be kept constant regardless of the connection method of the input / output terminals of the high frequency signal.

  Further, by adopting such a configuration, a terminal for applying a bias voltage can be shared with a terminal for applying a high-frequency signal, so that the variable can be easily handled with a simpler configuration. A capacitor capacitor array can be used.

  Hereinafter, a specific configuration of the variable capacitor array of the present invention as shown in FIGS. 1 to 9 will be described.

  As an example, a variable capacitor array according to a second embodiment of the present invention shown in FIG. 2 will be described. FIG. 10 is a plan view of a second embodiment of the present invention in a see-through state, and FIG. 11 is a cross-sectional view taken along the line A-A ′ in FIG. 10.

  10 and 11, 1 is a support substrate, 2 is a lower electrode layer, 31 to 34 are conductor lines, 4 is a thin film dielectric layer, 5 is an upper electrode layer, 61 to 64 is a thin film resistor, 7 is an insulating layer, 8 is a lead electrode layer, 9 is a protective layer, 10 is a solder diffusion prevention layer, and 111, 112, 113, 114 are solder terminal portions. is there. The solder diffusion prevention layer 10 and the solder terminal portions 111 and 112a and 112b constitute a common signal terminal CS1 and individual signal terminals Sa and Sb. Further, the solder diffusion preventing layer 10 and the solder terminal portions 113a, 113b and 114a, 114b constitute the first bias terminals V1a, V1b and the second bias terminals V2a, V2b. In addition, a variable capacitance element is configured in a region where the lower electrode layer 2, the thin film dielectric layer 4, and the upper electrode layer 5 overlap in the thickness direction. Further, the first individual bias line and the second individual bias line are configured by combinations of conductor lines 31 to 34 and thin film resistors 61 to 64.

  The support substrate 1 is a ceramic substrate such as alumina ceramic, a single crystal substrate such as sapphire, or the like. Then, the lower electrode layer 2, the thin film dielectric layer 4, and the upper electrode layer 5 are sequentially formed on the support substrate 1 on almost the entire surface of the support substrate 1. After the formation of these layers, the upper electrode layer 5, the thin film dielectric layer 4 and the lower electrode layer 2 are sequentially etched into a predetermined shape. In order to connect the variable capacitance elements C1 to C3 and C4 to C6 in series from a solder terminal portion 111 to solder terminal portions 112a and 112b, which will be described later, the lower electrode layer is formed by the variable capacitance elements C1 and C2 and the variable capacitance elements C1 and C2. Pattern 2 to share 2.

  The lower electrode layer 2 needs to have a high melting point because high temperature sputtering is required for forming the thin film dielectric layer 4. Specifically, it is made of a metal material such as Pt or Pd. Further, after the formation of the lower electrode layer 2 by high-temperature sputtering, the thin film dielectric layer 4 is heated to 700 to 900 ° C., which is the sputtering temperature, and held for a certain period of time until the sputtering of the thin film dielectric layer 4 is started. It becomes.

  When considering the resistance component and the continuity of the lower electrode layer 2, the thickness of the lower electrode layer 2 is preferably thicker. However, when considering the adhesion to the support substrate 1, the thickness of the lower electrode layer 2 is preferably relatively thin. It is determined in consideration of both. Specifically, it is 0.1 μm to 10 μm. If the thickness of the lower electrode layer 2 is less than 0.1 μm, the resistance of the electrode itself increases and the continuity of the electrode may not be ensured. On the other hand, if it is thicker than 10 μm, the adhesion to the support substrate 1 may be lowered, or the support substrate 1 may be warped.

  The thin film dielectric layer 4 is preferably a high dielectric constant dielectric layer made of perovskite oxide crystal particles containing at least Ba, Sr, and Ti. The thin film dielectric layer 4 is formed on the surface of the lower electrode layer 2 described above. For example, using a dielectric material from which perovskite-type oxide crystal particles can be obtained as a target, film formation by sputtering is performed until a desired thickness is obtained. At this time, by performing sputtering at a high substrate temperature, for example, 800 ° C., the low-loss thin-film dielectric layer 4 having a high dielectric constant and a large capacitance change rate can be obtained without performing a heat treatment after sputtering.

  The material of the upper electrode layer 5 is desirably Au having a low resistivity in order to reduce the resistance of the electrode. However, in order to improve the adhesion with the thin film dielectric layer 4, it is desirable to use Pt or the like as the adhesion layer. The thickness of the upper electrode layer 5 is 0.1 μm to 10 μm. The lower limit of the thickness is set in consideration of the resistance of the electrode itself, similarly to the lower electrode layer 2. The upper limit of the thickness is set in consideration of the adhesiveness with the thin film dielectric layer 4.

  The first individual bias line of the first variable capacitor string is composed of conductor lines 31 to 33 and thin film resistors 61 and 62. The lead electrode layer 8 connected to the upper electrode layer 5 of the variable capacitor C1 is variable. It is connected to the extraction electrode layer 8 that connects the capacitive elements C2 and C3. The first individual bias line is connected to the solder terminal portion 113a. The second individual bias line is composed of the conductor line 34 and the thin film resistors 63 and 64, and is connected to the common lower electrode layer 2 connecting the variable capacitance elements C1 and C2, and the lower electrode layer 2 of the variable capacitance element C3. Yes. The second individual bias line is connected to the solder terminal portion 114a. The same applies to the second variable capacitor string.

  The conductor lines 31 to 34 can be formed by forming a new film after forming the lower electrode layer 2, the thin film dielectric layer 4 and the upper electrode layer 5 described above. In this case, it is desirable to use a lift-off method in order to protect the already formed lower electrode layer 2, thin film dielectric layer 4 and upper electrode layer 5. The conductor lines 31 to 34 can also be formed by patterning so that the conductor lines 31 to 34 are formed at the same time when the lower electrode layer 2 is patterned.

  As a material of the conductor lines 31 to 34, Au having a low resistance is desirable in order to suppress variation in resistance values of the first and second individual bias lines, but the resistance of the thin film resistors 61 to 64 is sufficiently high. Therefore, it may be formed using the same material and the same process as the lower electrode layer 2 using Pt or the like.

  Next, as a material of the thin film resistors 61 to 64 constituting the first and second individual bias lines, it is desirable that the material contains tantalum (Ta) and has a specific resistance of 1 mΩ · cm or more. Specific examples of the material include tantalum nitride, TaSiN, and Ta—Si—O. For example, in the case of tantalum nitride, thin film resistors 61 to 64 having a desired composition ratio and resistivity can be formed by a reactive sputtering method in which sputtering is performed by adding nitrogen using Ta as a target.

  By appropriately selecting the sputtering conditions, thin film resistors 61 to 64 having a film thickness of 40 nm or more and a specific resistance of 1 mΩ · cm or more can be formed. Furthermore, after the sputtering is completed, a resist is applied, processed into a predetermined shape, and then subjected to an etching process such as reactive ion etching (RIE), whereby patterning can be easily performed.

  Further, when the variable capacitor of the present invention is used at a frequency of 2 GHz and the capacitance of the variable capacitance element C1 is 7 pF, the thin film resistors 61 to 61 do not adversely affect the impedance from 1/10 (200 MHz) of this frequency. If 64 is set to a resistance value of 10 times or more the impedance of the variable capacitance element C1, the required resistance values of the first and second bias lines may be about 1.1 kΩ or more. Since the specific resistivity of the thin film resistors 61 to 64 in the variable capacitor according to the present invention is desirably 1 mΩ · cm or more, for example, when obtaining 10 kΩ as the resistance value of the first and second individual bias lines, the thin film resistors 61 to Since the aspect ratio (length / width) of 64 can be 50 or less when the film thickness is 50 nm, the thin film resistors 61 to 64 have an aspect ratio that can be realized without increasing the element shape.

  The first and second individual bias lines including these thin film resistors 61 to 64 are preferably formed directly on the support substrate 1. This eliminates the need for an insulating layer for securing insulation from the lower electrode layer 2, the upper electrode layer 4, and the extraction electrode layer 8, which is necessary when forming on the variable capacitance elements C <b> 1 to C <b> 6. It becomes possible to reduce the number of layers constituting C1 to C6. Furthermore, by using the high resistance thin film resistors 61 to 64, the variable capacitance elements C1 to C6 can be manufactured without increasing the shape.

  Next, the insulating layer 7 is necessary for ensuring insulation between the lead electrode layer 8 and the lower electrode layer 2 formed thereon. Further, since the insulating layer 7 covers the first and second individual bias lines and can prevent the thin film resistors 61 to 64 from being oxidized, the resistance values of the first and second bias lines are changed over time. Thus, reliability can be improved. The material of the insulating layer 7 is preferably made of at least one of silicon nitride and silicon oxide in order to improve moisture resistance. These films are preferably formed by a chemical vapor deposition (CVD) method or the like in consideration of coverage.

  The insulating layer 7 can be processed into a desired shape by a dry etching method using a normal resist. The insulating layer 7 has an insulating layer 7 on the conductor lines 32 and 33 in order to expose a part of the conductor lines 32 and 33 in order to secure the connection between the thin film resistors 61 to 64 and the lead electrode layer 8. Are provided with through holes reaching the conductor lines 32 and 33. In addition, it is preferable that only the upper electrode layer 5 and the solder terminal portions 111, 112, 13, and 114 be exposed from the insulating layer 7 from the viewpoint of improving moisture resistance.

  Next, the lead electrode layer 8 connects the upper electrode layer 5 of the variable capacitance elements C1 and C4 and the solder terminal portion 111, and connects the upper electrode layers 5 to each other, thereby connecting the variable capacitance elements C2 and C3. The variable capacitance elements C5 and C6 are connected in series. Further, the lead electrode layer 8 extending over the variable capacitance elements C2 and C5 and the variable capacitance elements C3 and C6 is connected to the conductor line 33 through the through hole of the insulating layer 7. As the material of the extraction electrode layer 8, it is desirable to use a low resistance metal such as Au or Cu. In addition, an adhesive layer such as Ti or Ni may be used for the extraction electrode layer 8 in consideration of adhesion to the insulating layer 7.

  Next, the protective layer 9 is formed so that the solder terminal portions 111 to 114 are exposed and covered entirely. The protective layer 9 is intended to mechanically protect the constituent members of the variable capacitor including the variable capacitor C1, and to protect it from contamination by chemicals and the like. However, when the protective layer 9 is formed, the solder terminal portions 111 to 114 are exposed. As a material of the protective layer 9, a material having high heat resistance and excellent coverage with respect to a step is preferable. Specifically, polyimide resin, BCB (benzocyclobutene) resin, or the like is used. These are formed by applying a resin material and then curing at a predetermined temperature.

  The solder diffusion preventing layer 10 is formed to prevent the solder terminal portions 111 to 114 from diffusing into the lower electrode layer 2 during reflow or mounting when the solder terminal portions 111 to 114 are formed. As a material of the solder diffusion preventing layer 10, Ni is suitable. Further, in order to improve the solder wettability, Au, Cu or the like having a high solder wettability may be formed on the surface of the solder diffusion preventing layer 10 to about 0.1 μm.

  Finally, solder terminal portions 111 to 114 are formed. This is formed to facilitate mounting of the variable capacitor on the external wiring board. These solder terminal portions 111 to 114 are generally formed by reflowing after a solder paste is printed on the solder terminal portions 111 to 114 using a predetermined mask.

  By forming in this way, the variable capacitance elements C1 to C3 are connected in series between the solder terminal portion 111 and the solder terminal portion 112a as described below. That is, the solder terminal portion 111 is connected to the upper electrode layer 5 of the first variable capacitance element C1 through the extraction electrode layer 8. The variable capacitance elements C1 and C2 are connected by sharing the lower electrode layer 2. The variable capacitance elements C <b> 2 and C <b> 3 are connected by connecting the upper electrode layers 5 through the extraction electrode layer 8. Finally, the variable capacitance element C3 and the solder terminal portion 112a are connected by the lower electrode layer 2 of the variable capacitance element C3 formed to extend to the position where the solder terminal portion 112a is formed. Similarly, the variable capacitance elements C4 to C6 are connected in series between the solder terminal portion 111 and the solder terminal portion 112b.

  Next, as another example of the specific configuration of the variable capacitor array of the present invention, the specific configuration of the fifth embodiment of the present invention shown in FIG. 9 will be described.

  FIG. 12 is a transparent plan view showing an example of the fifth embodiment of the present invention.

  FIG. 12 is different from the example shown in FIG. 11 in that the solder terminal portions 113 and 114 are shared with the solder terminal portions 111 and 112, and the solder terminal portions 113 and 114 are omitted. In order to obtain such a configuration, the connection method of the first and second individual bias lines is as follows. That is, the first individual bias line of the first variable capacitor string has the conductor line 35 connected to the upper electrode layer 5 of the variable capacitor C <b> 1 via the lead electrode layer 8. A conductor line 36 is connected to the lead electrode layer 8 that connects the variable capacitance elements C2 and C3. A thin film resistor 65 is arranged so as to connect the conductor lines 35 and 36. The conductor lines 35 and 36 and the thin film resistor 65 constitute a first individual bias line. The second individual bias line has a conductor line 37 connected to the lower electrode layer 2 of the variable capacitance element C3, and is connected to the conductor line 37 via the thin film resistor 66 to the lower electrode layer 2 connecting the variable capacitance elements C1 and C2. Configured.

  With such a configuration, it is possible to provide a variable capacitor array that can be easily handled with a simple configuration.

  Next, an example of an embodiment of the variable capacitor relay of the present invention will be described with reference to FIG. FIG. 13 is an equivalent circuit diagram showing an example of an embodiment of the variable capacitor relay of the present invention.

  In the example shown in FIG. 13, a plurality (two in FIG. 13) of variable capacitor arrays according to the fifth embodiment of the present invention are arranged, and the individual signal terminals Sb and Sa are electrically connected between the plurality of variable capacitor arrays. Connected. The individual signal terminals Sa and the individual signal terminals Sb at both ends in the arrangement direction of the variable capacitor array, that is, the individual signal terminals Sa positioned at the top in the vertical direction of FIG. By providing the individual signal terminal Sb with a function as an input / output terminal for a high frequency signal, four variable capacitors are connected in series, and the degree of freedom in designing the initial capacity can be further improved. Furthermore, a plurality of variable capacitor relays as shown in FIG. 13 are arranged, and external switching elements are connected to the common signal terminal CS1, the individual signal terminals Sa and Sb, and the switching elements of the common signal terminal CS1 are connected to each other. By connecting the switching elements of the individual signal terminals Sa and Sb, the initial capacity can be further freely designed, and a highly versatile variable capacitor relay can be provided.

  In addition, by using the variable capacitor array and the variable capacitor relay of the present invention as a part of the voltage controlled resonator for high frequency (as part of the resonance circuit) or as a means for coupling the resonance circuits to each other, Is connected in series and connected in parallel with DC, and a resonator is made using variable capacitance elements. The voltage control type for high frequency with low waveform distortion and intermodulation distortion noise and excellent power durability. An electronic component that is a resonator can be realized. Similarly, in a voltage-controlled high-frequency filter and a voltage-controlled antenna duplexer equipped with a resonance circuit, a waveform can be obtained by using variable capacitance elements that are connected in series for high frequencies and connected in parallel for DC. A voltage-controlled high-frequency filter and an antenna duplexer with low distortion and intermodulation distortion noise and excellent power resistance can be manufactured.

1 is an equivalent circuit diagram showing a first embodiment of a variable capacitor array of the present invention. It is an equivalent circuit diagram showing a second embodiment of the variable capacitor array of the present invention. FIG. 6 is an equivalent circuit diagram showing a third embodiment of the variable capacitor array of the present invention. FIG. 6 is an equivalent circuit diagram showing a fourth embodiment of the variable capacitor array of the present invention. FIG. 5 is an equivalent circuit diagram showing a modification of FIG. 4. It is an equivalent circuit diagram which shows the other example of the modification of FIG. FIG. 5 is an equivalent circuit diagram illustrating a modification of FIGS. FIG. 5 is an equivalent circuit diagram illustrating a modification of FIGS. FIG. 9 is an equivalent circuit diagram showing a fifth embodiment of the variable capacitor array of the present invention. It is a top view of the see-through state which shows typically an example of 2nd Embodiment of the variable capacitor array of this invention shown in FIG. It is A-A 'line sectional drawing of FIG. FIG. 10 is a perspective view schematically showing an example of a fifth embodiment of the variable capacitor array of the present invention shown in FIG. 9. It is an equivalent circuit diagram showing an embodiment of a variable capacitor relay of the present invention.

Explanation of symbols

1: Support substrate 2: Lower electrode layer 31-37: Conductor line 4: Dielectric layer 5: Upper electrode layer 61, 62, 63, 64, 65, 66: Thin film resistor 7: Insulator layer 8: Lead electrode layer 9 : Protection layer 10: Solder diffusion prevention layer 111, 112, 113, 114: Solder terminal portion C1, C2, C3, C4, C5, C6: Variable capacitance element P1a, P1b: First terminal P2a, P2b: Second terminal Sa , Sb: Individual signal terminal CS1: Common signal terminal B11-B14: First individual bias line B21-B24: Second individual bias line

Claims (6)

A plurality of variable capacitance elements are connected in series between the first terminal and the second terminal, the connection point between the first terminal and the first variable capacitance element counted from the first terminal, and each variable capacitance. A first individual bias line and a second individual bias line are arranged in order from the first terminal side at a connection point between the elements and a connection point between the first variable capacitance element counted from the second terminal and the second terminal. Alternately connected variable capacitors, individual signal terminals connected to the second terminal, a plurality of variable capacitor strings each of which has,
A variable capacitor array comprising: a common signal terminal to which the first terminals of the plurality of variable capacitor strings are connected in common. For one variable capacitor string, a first bias terminal to which a plurality of the first individual bias lines are connected in common;
2. The variable capacitor array according to claim 1, further comprising a second bias terminal to which a plurality of the second individual bias lines are connected in common with respect to one of the variable capacitor strings. A common bias terminal;
The plurality of variable capacitor strings are:
A first variable capacitor capacitor string in which one of the first individual bias line and the second individual bias line is connected to the common bias terminal;
2. The variable capacitor array according to claim 1, further comprising: a second variable capacitor string in which one of the first individual bias line and the second individual bias line is connected to the common bias terminal. . A common bias terminal;
The plurality of variable capacitor strings are:
A first variable capacitor capacitor string in which one of the first bias terminal and the second bias terminal is connected to the common bias terminal;
3. The variable capacitor array according to claim 2, further comprising: a second variable capacitor capacitor string in which one of the first bias terminal and the second bias terminal is connected to the common bias terminal. The variable capacitor has an odd number of the variable capacitors,
The plurality of variable capacitor strings are:
A first variable capacitor capacitor string in which the first bias terminal is shared with the common signal terminal and the second bias terminal is shared with the individual signal terminal;
3. The variable according to claim 2, further comprising: a second variable capacitor capacitor string in which the first bias terminal is shared with the common signal terminal and the second bias terminal is shared with the individual signal terminal. Capacitor capacitor array.   6. A variable capacitor relay comprising a plurality of the variable capacitor arrays according to claim 2 connected to each other.

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