JP2006049572A - Semiconductor device and manufacturing method therefor - Google Patents

Semiconductor device and manufacturing method therefor Download PDF

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JP2006049572A
JP2006049572A JP2004228509A JP2004228509A JP2006049572A JP 2006049572 A JP2006049572 A JP 2006049572A JP 2004228509 A JP2004228509 A JP 2004228509A JP 2004228509 A JP2004228509 A JP 2004228509A JP 2006049572 A JP2006049572 A JP 2006049572A
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semiconductor device
semiconductor element
semiconductor
resin
electrode
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Katsuhiko Nishiyama
克彦 西山
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Toyota Motor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/4809—Loop shape
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
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    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

<P>PROBLEM TO BE SOLVED: To solve the controversial point that there is an anxiety about a reliability because the working time and working cost of a semiconductor device are increased, and there is the possibility of the application of a pressure to the semiconductor device in the case of a resin seal because a high dimensional precision is required in a member such as a semiconductor element, while a spacer tool must be mounted and demounted in the case of a solder joint since the resin seal of the semiconductor element has been conducted by a transfer molding in the conventional semiconductor device. <P>SOLUTION: In the semiconductor device 1, a pair of electrodes (a metal plate 31 and an upper electrode 4) are arranged oppositely on both surface sides of the semiconductor element 2. In the semiconductor device 1, supporters (an insulator 32 and a metallic foil 33a) having thicknesses larger than that of the semiconductor element 2 are interposed between a pair of the electrodes. In the semiconductor device 1, the supporters are formed in an approximately annular shape so as to surround the periphery of the semiconductor element 2. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体素子の両面側に一対の電極が対向配置される半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device having a pair of electrodes opposed to each other on both sides of a semiconductor element, and a method for manufacturing the same.

ＩＧＢＴやサイリスタ等のパワー半導体素子を備える半導体装置は作動時の発熱が大きいため、半導体素子の両面側に一対の電極を配し、これらの電極をそれぞれの半導体素子面とはんだ層を介して接合し、半導体素子の両面から電極へ放熱を行うように構成して、放熱性を向上させた半導体装置が従来から考案されている（特許文献１参照）。
このような両面放熱型の半導体装置が備える半導体素子は、封止樹脂により封止されているが、放熱性を確保するために両側の電極の外面は封止せずに露出させておくことが重要である。
前述のように半導体装置の半導体素子を樹脂封止する場合、トランスファーモールドと呼ばれる封止方法が一般的に良く用いられている。このトランスファーモールドでは、上型と下型とで構成される成形型のキャビティ内に、両面に電極がはんだ接合された半導体素子を封入し、加熱軟化させたエポキシ樹脂等の樹脂をキャビティ内に充填することで樹脂封止が行われる。
このように、樹脂封止の際に用いられる成形型は、軟化して流動性を有する樹脂により封止される半導体装置の外形を形づくるための枠として用いられるものである（封止時に成形型を用いないと樹脂が流れ出して所望の形状を形づくることができない）。
特開２００３−１１００６４号公報 Since semiconductor devices including power semiconductor elements such as IGBTs and thyristors generate a large amount of heat during operation, a pair of electrodes are arranged on both sides of the semiconductor element, and these electrodes are joined to each semiconductor element surface via a solder layer. In the past, a semiconductor device has been devised in which heat radiation is improved from both sides of a semiconductor element to improve heat dissipation (see Patent Document 1).
The semiconductor element included in such a double-sided heat dissipation type semiconductor device is sealed with a sealing resin, but it is important to expose the outer surfaces of the electrodes on both sides without sealing in order to ensure heat dissipation. It is.
As described above, when a semiconductor element of a semiconductor device is sealed with a resin, a sealing method called transfer molding is generally used. In this transfer mold, a semiconductor element with electrodes soldered on both sides is enclosed in a mold cavity composed of an upper mold and a lower mold, and heat-softened epoxy resin or the like is filled in the cavity. By doing so, resin sealing is performed.
As described above, the mold used for resin sealing is used as a frame for shaping the outer shape of a semiconductor device that is softened and sealed with a resin having fluidity (molding mold during sealing). Without using the resin, the resin cannot flow out to form the desired shape).
JP 2003-110064 A

図１１には、半導体素子１１１の下面側にはんだ層１１５を介して下部電極１１３を接合し、上面側にはんだ層およびスペーサ部材１１４を介して上部電極１１２を接合して構成した半導体装置１０１を成形型１２０のキャビティ１２０ａ内にセットし、該キャビティ１２０ａ内に封止樹脂１３０を充填して、トランスファーモールドが行われる様子を示している。
トランスファーモールドにて樹脂封止を行う場合、半導体装置１０１の上部電極１１２の上面と成形型１２０の上型１２１の天井面１２１ａとの間、および半導体装置１０１の下部電極１１３の下面と成形型１２０の下型１２２の底面１２２ａとの間に隙間が殆ど生じないように、成形型１２０のキャビティ１２０ａ内に半導体装置１０１をセットしなければならない。
なぜなら、上部電極１１２の上面と上型１２１の天井面１２１ａとの間、および下部電極１１３の下面と下型１２２の底面１２２ａとの間に隙間があると、この隙間に封止樹脂１３０が入り込んで上部電極１１２の上面および下部電極１１３の下面に封止樹脂１３０が付着し、半導体装置１０１の放熱性が極端に悪化してしまうからである。 FIG. 11 shows a semiconductor device 101 configured by bonding a lower electrode 113 to a lower surface side of a semiconductor element 111 via a solder layer 115 and bonding an upper electrode 112 to an upper surface side via a solder layer and a spacer member 114. It shows a state in which transfer molding is performed by setting in the cavity 120a of the mold 120 and filling the cavity 120a with the sealing resin 130.
When resin sealing is performed by transfer molding, between the upper surface of the upper electrode 112 of the semiconductor device 101 and the ceiling surface 121a of the upper mold 121 of the molding die 120, and the lower surface of the lower electrode 113 of the semiconductor device 101 and the molding die 120. The semiconductor device 101 must be set in the cavity 120a of the mold 120 so that there is almost no gap between the bottom surface 122a of the lower mold 122.
This is because if there is a gap between the upper surface of the upper electrode 112 and the ceiling surface 121a of the upper mold 121 and between the lower surface of the lower electrode 113 and the bottom surface 122a of the lower mold 122, the sealing resin 130 enters the gap. This is because the sealing resin 130 adheres to the upper surface of the upper electrode 112 and the lower surface of the lower electrode 113, and the heat dissipation of the semiconductor device 101 is extremely deteriorated.

上部電極１１２と天井面１２１ａとの間、および下部電極１１３と底面１２２ａとの間の隙間の大きさは、具体的には、封止樹脂に含まれるフィラーの粒径以下に抑える必要がある（隙間の大きさがフィラー粒径より大きいと封止樹脂１３０が隙間へ流入してしまう）。
逆に、成形型１２０の上型１２１と下型１２２とには、キャビティ１２０ａに充填された封止樹脂が漏れ出すのを防ぐために、閉じる方向へ大きな圧力がかけられているので、上部電極１１２の上面と下部電極１１３の下面との間の寸法が上型１２１の天井面１２１ａと下型１２２の底面１２２ａとの間の寸法よりも大きくなってしまうと、その圧力が半導体素子１１１に伝達されて半導体素子１１１が破壊してしまう。
従って、半導体装置１０１を製造する際には、トランスファーモールドを行う場合には、上部電極１１２の上面と下部電極１１３の下面との間の寸法を高精度に造り込む必要がある。 Specifically, the size of the gap between the upper electrode 112 and the ceiling surface 121a and between the lower electrode 113 and the bottom surface 122a needs to be suppressed to be equal to or smaller than the particle size of the filler contained in the sealing resin ( If the size of the gap is larger than the filler particle size, the sealing resin 130 flows into the gap).
On the contrary, since the upper mold 121 and the lower mold 122 are subjected to a large pressure in the closing direction in order to prevent the sealing resin filled in the cavity 120a from leaking, the upper electrode 112 is closed. If the dimension between the upper surface of the lower mold 113 and the lower surface of the lower electrode 113 becomes larger than the dimension between the ceiling surface 121a of the upper mold 121 and the bottom surface 122a of the lower mold 122, the pressure is transmitted to the semiconductor element 111. As a result, the semiconductor element 111 is destroyed.
Therefore, when the semiconductor device 101 is manufactured, when transfer molding is performed, it is necessary to make a dimension between the upper surface of the upper electrode 112 and the lower surface of the lower electrode 113 with high accuracy.

半導体装置１０１の前記寸法を高精度に造り込むにためには、半導体素子１１１や上下電極１１２・１１３に寸法精度が高い部材を用いる必要がある。また、半導体素子１１１と上下電極１１２・１１３とをはんだ接合する際の各部材の位置寸法を高精度に保持する必要があるため、はんだ接合を行う際には上下電極１１２・１１３間に所定の高さ寸法を有したスペーサ治具を介装し、はんだ接合が終了した後にスペーサ治具を取り外す必要がある。
このように、トランスファーモールドを行うためには、半導体素子１１１等の部材に高い寸法精度が求められるとともに、はんだ接合時にスペーサ治具の取り付け、取り外しが必要となることから、半導体装置１０１の加工時間や加工費が増大する。また、樹脂封止の際に半導体装置１０１に圧力がかかる恐れがあるため、信頼性にも不安がある。
また、トランスファーモールドを行う際に、上部電極１１２と成形型１２０における上型１２１の天井面１２１ａとの間、および下部電極１１３と下型１２２の底面１２２ａとの間の隙間が大きくて、封止樹脂がその隙間へ流入した場合には、上部電極１１２および下部電極１１３の外面に付着硬化した封止樹脂を研磨して除去する等の非常に手間がかかる余分な工程が必要となって加工費用が増大してしまうという問題も生じる。 In order to build the dimensions of the semiconductor device 101 with high accuracy, it is necessary to use members with high dimensional accuracy for the semiconductor element 111 and the upper and lower electrodes 112 and 113. In addition, since it is necessary to maintain the position dimensions of each member when the semiconductor element 111 and the upper and lower electrodes 112 and 113 are soldered together with high accuracy, a predetermined interval is required between the upper and lower electrodes 112 and 113 when performing the soldering. It is necessary to interpose a spacer jig having a height dimension and to remove the spacer jig after soldering is completed.
Thus, in order to perform transfer molding, high dimensional accuracy is required for members such as the semiconductor element 111, and it is necessary to attach and remove the spacer jig at the time of solder joining. And processing costs increase. In addition, since there is a possibility that pressure is applied to the semiconductor device 101 during resin sealing, there is also anxiety in reliability.
Further, when performing transfer molding, the gap between the upper electrode 112 and the ceiling surface 121a of the upper mold 121 in the mold 120 and between the lower electrode 113 and the bottom surface 122a of the lower mold 122 is large, and sealing is performed. In the case where the resin flows into the gap, an extra process that is very time-consuming such as polishing and removing the sealing resin that adheres and hardens on the outer surfaces of the upper electrode 112 and the lower electrode 113 is required. There is also a problem that increases.

上記課題を解決する半導体装置およびその製造方法は、以下の特徴を有する。
即ち、請求項１記載のごとく、半導体素子の両面側に一対の電極が対向配置される半導体装置であって、該一対の電極間に、半導体素子の厚みよりも大きな厚みを有する支持体が介在しており、該支持体における一方の電極との接合面と、他方の電極との接合面とが絶縁されている。
これにより、半導体素子の厚み寸法や半導体素子を接合するはんだの厚み寸法の精度にかかわらず、支持体の厚み寸法により半導体装置の厚み寸法を規制することができる。
つまり、支持体をスペーサとして用いているので、従来のように寸法精度が高い半導体素子を用いたり、スペーサ治具を用いたりしなくても半導体装置の厚み寸法を一定寸法に維持することができる。
従って、一対の電極の外面に封止樹脂を付着させることなく、また半導体素子に圧力をかけることなくトランスファーモールドを行うことが可能となり、信頼性の高い半導体装置を安価な加工費にて製造することができる。 A semiconductor device and a manufacturing method thereof that solve the above problems have the following characteristics.
That is, as described in claim 1, a semiconductor device in which a pair of electrodes are disposed opposite to each other on both sides of a semiconductor element, and a support having a thickness larger than the thickness of the semiconductor element is interposed between the pair of electrodes. In addition, the bonding surface of the support with one electrode and the bonding surface with the other electrode are insulated.
Accordingly, the thickness dimension of the semiconductor device can be regulated by the thickness dimension of the support body regardless of the accuracy of the thickness dimension of the semiconductor element and the thickness dimension of the solder joining the semiconductor element.
That is, since the support is used as a spacer, the thickness dimension of the semiconductor device can be maintained at a constant level without using a semiconductor element with high dimensional accuracy as in the prior art or without using a spacer jig. .
Accordingly, transfer molding can be performed without attaching sealing resin to the outer surfaces of the pair of electrodes and without applying pressure to the semiconductor element, and a highly reliable semiconductor device can be manufactured at low cost. be able to.

また、請求項２記載のごとく、前記支持体は、半導体素子の周囲を囲む略環形状に形成される。
これにより、成形型を用いることなく、支持体により囲まれる空間に封止樹脂を注入して樹脂封止を行うことが可能となる。
従って、成形型を用いて樹脂封止を行う場合のように、半導体装置の厚み寸法を高精度に維持する必要がなく、封止樹脂の使用量も少量に抑えることも可能となる。
また、成形型を用いないので、半導体装置の組立工程でスペーサ治具の組み付け・取り外しを行う必要もなく、加圧により半導体素子の信頼性が低下する心配もない。 According to a second aspect of the present invention, the support is formed in a substantially ring shape surrounding the periphery of the semiconductor element.
Accordingly, it is possible to perform resin sealing by injecting the sealing resin into the space surrounded by the support without using a mold.
Therefore, it is not necessary to maintain the thickness dimension of the semiconductor device with high accuracy as in the case of performing resin sealing using a molding die, and the amount of sealing resin used can be suppressed to a small amount.
Further, since no molding die is used, it is not necessary to assemble / remove the spacer jig in the assembling process of the semiconductor device, and there is no fear that the reliability of the semiconductor element is reduced by pressurization.

また、請求項３記載のごとく、前記半導体装置における、前記一対の電極および支持体にて囲まれた空間には、電極または支持体にて被覆されていない開口部が存在する。
これにより、開口部から電極および支持体にて囲まれた空間の中に封止樹脂を注入して半導体素子を樹脂封止することが可能となる。 According to a third aspect of the present invention, there is an opening that is not covered with the electrode or the support in the space surrounded by the pair of electrodes and the support in the semiconductor device.
Thus, the semiconductor element can be resin-sealed by injecting the sealing resin into the space surrounded by the electrode and the support from the opening.

また、請求項４記載のごとく、請求項１〜請求項３の何れかに記載の半導体装置を、上型および下型からなる成形型のキャビティ内に封入し、該キャビテイ内に封止樹脂を充填することにより、半導体素子の樹脂封止を行う。
この場合、半導体素子の厚み寸法や半導体素子を接合するはんだの厚み寸法の精度にかかわらず、支持体の厚み寸法により半導体装置の厚み寸法を規制することができるので、
従来のように寸法精度が高い半導体素子を用いたり、スペーサ治具を用いたりしなくても半導体装置の厚み寸法を一定寸法に維持することができ、一対の電極の外面に封止樹脂を付着させることなく、成形型を用いたトランスファーモールドを行うことが可能である。また、モールド時に半導体素子を加圧してしまって半導体装置の信頼性が低下する心配もない。 Further, as described in claim 4, the semiconductor device according to any one of claims 1 to 3 is enclosed in a cavity of a molding die composed of an upper die and a lower die, and sealing resin is placed in the cavity. The resin sealing of the semiconductor element is performed by filling.
In this case, since the thickness dimension of the semiconductor device can be regulated by the thickness dimension of the support, regardless of the thickness dimension of the semiconductor element and the thickness dimension of the solder joining the semiconductor element,
The thickness of the semiconductor device can be kept constant without using semiconductor elements with high dimensional accuracy or spacer jigs as in the past, and sealing resin is attached to the outer surfaces of a pair of electrodes. It is possible to carry out transfer molding using a molding die without causing them. In addition, there is no concern that the reliability of the semiconductor device is reduced due to pressurization of the semiconductor element during molding.

また、請求項５記載のごとく、請求項２または請求項３に記載の半導体装置における、前記一対の電極および支持体にて囲まれた空間に、封止樹脂を直接注入することにより、該空間内に配置される半導体素子の樹脂封止を行う。
この場合、支持体により、注入した封止樹脂が流れ出ることを防止できるので、成形型を用いることなく半導体素子の樹脂封止を行うことができ、成形型を用いて樹脂封止を行う場合のように、半導体装置の厚み寸法を高精度に維持する必要がなく、封止樹脂の使用量も少量に抑えることも可能となる。
また、成形型を用いないので、半導体装置の組立工程でスペーサ治具の組み付け・取り外しを行う必要もなく、加圧により半導体素子の信頼性が低下する心配もない。 In addition, as described in claim 5, in the semiconductor device according to claim 2 or claim 3, by directly injecting a sealing resin into the space surrounded by the pair of electrodes and the support, Resin sealing of the semiconductor element disposed inside is performed.
In this case, since the injected sealing resin can be prevented from flowing out by the support, the resin sealing of the semiconductor element can be performed without using the mold, and the case of performing the resin sealing using the mold Thus, it is not necessary to maintain the thickness dimension of the semiconductor device with high accuracy, and the amount of the sealing resin used can be suppressed to a small amount.
Further, since no molding die is used, it is not necessary to assemble / remove the spacer jig in the assembling process of the semiconductor device, and there is no fear that the reliability of the semiconductor element is reduced by pressurization.

また、請求項６記載のごとく、前記半導体装置は、一方の電極上に支持体を貼着する工程、一方の電極上に半導体素子の一面を接合する工程、支持体上に他方の電極を貼着する工程、他方の電極と半導体素子の他面とを接合する工程を順に経た後に、半導体素子の樹脂封止工程が行われる。
これにより、厚み寸法を一定に維持するとともに、半導体素子の周囲に支持体および一対の電極により囲まれた空間を形成した半導体装置を構成した後に半導体素子の樹脂封止が行われることとなり、成形型を用いた樹脂封止を行う場合には両電極の外面に封止樹脂が付着することを防止でき、成形型を用いずに樹脂封止を行う場合には封止樹脂の流れを止めることができて、樹脂封止工程を簡素化することができる。 According to a sixth aspect of the present invention, the semiconductor device includes a step of attaching a support on one electrode, a step of bonding one surface of a semiconductor element on one electrode, and attaching the other electrode on the support. After the step of attaching and the step of joining the other electrode and the other surface of the semiconductor element in order, a resin sealing step of the semiconductor element is performed.
As a result, the thickness of the semiconductor element is kept constant, and after the semiconductor device is formed in which the space surrounded by the support and the pair of electrodes is formed around the semiconductor element, the resin sealing of the semiconductor element is performed. When performing resin sealing using a mold, it is possible to prevent the sealing resin from adhering to the outer surfaces of both electrodes, and when performing resin sealing without using a mold, stop the flow of the sealing resin. And the resin sealing process can be simplified.

本発明によれば、一対の電極の外面に封止樹脂を付着させることなく、また半導体素子に圧力をかけることなくトランスファーモールドを行うことが可能となり、信頼性の高い半導体装置を安価な加工費にて製造することができる。
また、成形型を用いることなく、支持体により囲まれる空間に封止樹脂を注入して樹脂封止を行うことが可能となる。従って、半導体装置の厚み寸法を高精度に維持する必要がなく、封止樹脂の使用量も少量に抑えることも可能となる。
さらに、成形型を用いないので、半導体装置の組立工程でスペーサ治具の組み付け・取り外しを行う必要もなく、加圧により半導体素子の信頼性が低下する心配もない。 According to the present invention, transfer molding can be performed without adhering sealing resin to the outer surfaces of a pair of electrodes and without applying pressure to a semiconductor element, and a highly reliable semiconductor device can be manufactured at low cost. Can be manufactured.
In addition, it is possible to perform resin sealing by injecting a sealing resin into a space surrounded by the support without using a mold. Therefore, it is not necessary to maintain the thickness dimension of the semiconductor device with high accuracy, and the amount of the sealing resin used can be suppressed to a small amount.
Further, since no molding die is used, it is not necessary to assemble / remove the spacer jig in the assembly process of the semiconductor device, and there is no fear that the reliability of the semiconductor element is reduced by the pressurization.

次に、本発明を実施するための形態を、添付の図面を用いて説明する。   Next, modes for carrying out the present invention will be described with reference to the accompanying drawings.

〔第一実施形態〕
図１に示す半導体装置１は、ＩＧＢＴやサイリスタ等のパワー素子に構成される半導体素子２と、該半導体素子２が実装される基板３と、半導体素子２の上面に接合される上部電極４とを備えている。 [First embodiment]
A semiconductor device 1 shown in FIG. 1 includes a semiconductor element 2 configured as a power element such as an IGBT or a thyristor, a substrate 3 on which the semiconductor element 2 is mounted, and an upper electrode 4 bonded to the upper surface of the semiconductor element 2. It has.

基板３は、銅板等の金属板３１にエポキシ系接着剤等の接着性を有する絶縁物３２を用いて銅箔等の金属箔３３ａ・３３ｂを貼設して構成されている。基板３の略中央部は、絶縁物３２および金属箔３３ａ・３３ｂが除去されて金属板３１が露出している素子実装部３５に形成されている。素子実装部３５は、半導体素子２の大きさよりも若干大きな面積に形成されている。
金属箔３３ａは半導体実装部３５の周囲を囲む導電パターンに形成されており、金属箔３３ｂは信号線取り出し用の直線パターンに形成されている。 The substrate 3 is configured by attaching metal foils 33a and 33b such as copper foil to a metal plate 31 such as a copper plate using an insulator 32 having adhesiveness such as an epoxy adhesive. A substantially central portion of the substrate 3 is formed in an element mounting portion 35 where the insulator 32 and the metal foils 33a and 33b are removed and the metal plate 31 is exposed. The element mounting portion 35 is formed in an area slightly larger than the size of the semiconductor element 2.
The metal foil 33a is formed in a conductive pattern surrounding the periphery of the semiconductor mounting portion 35, and the metal foil 33b is formed in a linear pattern for taking out signal lines.

このように構成される基板３に、以下のごとく半導体素子２を実装する等して、半導体装置１が構成される。
まず、図４（ａ）に示すように、半導体素子２を、基板３の素子実装部３５にはんだを用いて実装する。この場合、半導体素子２の下面と素子実装部３５における金属板３１とをはんだ６にて接合するが、接合部の信頼性を確保するために、はんだ６層にはある程度の厚みが必要とされる。 The semiconductor device 1 is configured by mounting the semiconductor element 2 on the substrate 3 thus configured as follows.
First, as shown in FIG. 4A, the semiconductor element 2 is mounted on the element mounting portion 35 of the substrate 3 using solder. In this case, the lower surface of the semiconductor element 2 and the metal plate 31 in the element mounting portion 35 are joined with the solder 6, but a certain amount of thickness is required for the solder 6 layer in order to ensure the reliability of the joined portion. The

従って、半導体素子２を素子実装部３５にはんだ接合する際には、例えば、必要とされるはんだ６層の厚みを確保できるだけの径を有した、はんだ６よりも高融点の金属球を含むはんだ６を用いて、はんだ接合が行われる。
また、はんだ接合を行う前に、予め必要とされるはんだ６層の厚み分だけ半導体素子２と金属板３１との間隔を空けた状態で、両者を接着剤にて接着しておき、その後はんだ接合を行ってもよい。 Therefore, when the semiconductor element 2 is solder-bonded to the element mounting portion 35, for example, a solder including a metal ball having a melting point higher than that of the solder 6 and having a diameter sufficient to ensure the required thickness of the solder 6 layer. 6 is used to perform solder bonding.
Further, before soldering, the semiconductor element 2 and the metal plate 31 are bonded with an adhesive in a state in which the semiconductor element 2 and the metal plate 31 are spaced in advance by the required thickness of the six layers of solder. Joining may be performed.

なお、はんだ接合を行う場合、素子実装部３５は半導体素子２の面積よりも若干大きめの面積に形成されており、はんだ６が流れる範囲は素子実装部３５の範囲内に規制されているため、従来の方法で半導体素子２を実装するときのように、治具を用いて半導体素子２の位置決めを行うことなく、半導体素子２を実装することが可能となっている。
また、半導体素子２に接合される金属板３１は半導体装置１の下部電極の役割を果たすものである。
半導体素子２を基板３に実装した後、図４（ｂ）に示すように、半導体素子２に形成される制御用信号を与えるためのパッドと前記金属箔３３ｂとをボンディングワイヤー７にて接続する。 When performing solder bonding, the element mounting portion 35 is formed to have a slightly larger area than the area of the semiconductor element 2, and the range in which the solder 6 flows is restricted within the range of the element mounting portion 35. The semiconductor element 2 can be mounted without positioning the semiconductor element 2 using a jig, as in the case of mounting the semiconductor element 2 by a conventional method.
The metal plate 31 joined to the semiconductor element 2 serves as a lower electrode of the semiconductor device 1.
After the semiconductor element 2 is mounted on the substrate 3, as shown in FIG. 4B, the pad for supplying a control signal formed on the semiconductor element 2 and the metal foil 33b are connected by the bonding wire 7. .

次に、図５（ａ）に示すように、前記金属箔３３ａおよび半導体素子２の上面にはんだ６を供給し、該金属箔３３ａおよび半導体素子２と前記上部電極４とをはんだ接合する。
図５（ｂ）に示すように、上部電極４のはんだ接合を行う際には、上部電極４上に錘部材を載せるなどして上部電極４へ上方からの圧力を加えて、金属箔３３ａと上部電極４との間のはんだ６の厚みが略０となるようにしている。 Next, as shown in FIG. 5A, the solder 6 is supplied to the upper surfaces of the metal foil 33a and the semiconductor element 2, and the metal foil 33a and the semiconductor element 2 and the upper electrode 4 are soldered.
As shown in FIG. 5B, when soldering the upper electrode 4, a pressure member is applied to the upper electrode 4 by placing a weight member on the upper electrode 4, and the metal foil 33 a The thickness of the solder 6 between the upper electrode 4 is set to be substantially zero.

ここで、絶縁物３２の厚みと金属箔３３ａとを合計した寸法が、半導体素子２の厚みと半導体素子２下方のはんだ６厚みとを合計した寸法よりも大きくなるように構成されている。そして、絶縁物３２および金属箔３３ａは、下部電極として用いられる金属板３１と上部電極４との間に介在される支持体となっている。
従って、金属箔３３ａと上部電極４との間のはんだ６の厚みが略０となるように上部電極４をはんだ接合する場合、半導体装置１全体の厚み寸法は、半導体素子２や半導体素子２下方のはんだ６の厚みには影響されず、基板３の厚み寸法によって決定されることになる。そして、絶縁物３２の厚みと金属箔３３ａの厚みとを合計した寸法が、半導体素子２の厚みと半導体素子２下方のはんだ６厚みと半導体素子２上方のはんだ６厚みとを合計した寸法と等しくなる。
また、絶縁物３２と金属箔３３ａとで構成される支持体における、上部電極４との接合面と、下部電極である金属板３１との接合面とは、絶縁されている。つまり、金属箔３３ａの上面と絶縁物３２の下面とは絶縁状態となっており、上部電極４と金属板３１との間に支持体を介装することで、上部電極４と金属板３１とが電気的に接続されることがないようにしている。 Here, the total dimension of the thickness of the insulator 32 and the metal foil 33 a is configured to be larger than the total dimension of the thickness of the semiconductor element 2 and the thickness of the solder 6 below the semiconductor element 2. The insulator 32 and the metal foil 33a serve as a support that is interposed between the metal plate 31 used as the lower electrode and the upper electrode 4.
Therefore, when the upper electrode 4 is soldered so that the thickness of the solder 6 between the metal foil 33a and the upper electrode 4 becomes substantially zero, the thickness dimension of the entire semiconductor device 1 is below the semiconductor element 2 and the semiconductor element 2. It is not affected by the thickness of the solder 6 and is determined by the thickness dimension of the substrate 3. The total dimension of the thickness of the insulator 32 and the thickness of the metal foil 33a is equal to the total dimension of the thickness of the semiconductor element 2, the thickness of the solder 6 below the semiconductor element 2, and the thickness of the solder 6 above the semiconductor element 2. Become.
In addition, the bonding surface with the upper electrode 4 and the bonding surface with the metal plate 31, which is the lower electrode, in the support configured by the insulator 32 and the metal foil 33 a are insulated. That is, the upper surface of the metal foil 33 a and the lower surface of the insulator 32 are in an insulated state, and the upper electrode 4 and the metal plate 31 are interposed by interposing a support between the upper electrode 4 and the metal plate 31. Are not electrically connected.

半導体素子２が実装される基板３の素子実装部３５は、上部電極４をはんだ接合することで、金属板３１、絶縁物３２、金属箔３３ａ・３３ｂ、および上部電極４に囲まれた空間となっているが、上部電極４は基板３全面にわたっては設けられておらず、素子実装部３５の一部は上部電極４に被覆されずに開口部３５ａが形成されている。   The element mounting portion 35 of the substrate 3 on which the semiconductor element 2 is mounted has a space surrounded by the metal plate 31, the insulator 32, the metal foils 33 a and 33 b, and the upper electrode 4 by soldering the upper electrode 4. However, the upper electrode 4 is not provided over the entire surface of the substrate 3, and a part of the element mounting portion 35 is not covered with the upper electrode 4 and an opening 35 a is formed.

上部電極４がはんだ接合された後に、開口部３５ａから素子実装部３５内へ、エポキシ系樹脂等の封止樹脂５を充填して硬化させ、半導体素子２を封止する。このように、半導体素子２の周囲を封止樹脂５（図１図示）にて封止することで、半導体素子２自身や半導体素子２のはんだ接合部の信頼性を確保している。
また、素子実装部３５内への封止樹脂５の充填は、液状の封止樹脂５をディスペンサー等により開口部３５ａから直接ポッティング注入すること等により行われる。 After the upper electrode 4 is soldered, the sealing resin 5 such as an epoxy resin is filled from the opening 35a into the element mounting portion 35 and cured, and the semiconductor element 2 is sealed. Thus, by sealing the periphery of the semiconductor element 2 with the sealing resin 5 (shown in FIG. 1), the reliability of the semiconductor element 2 itself and the solder joint portion of the semiconductor element 2 is ensured.
Further, the sealing resin 5 is filled into the element mounting portion 35 by potting and injecting the liquid sealing resin 5 directly from the opening 35a with a dispenser or the like.

このように、半導体装置１において、封止樹脂５により半導体素子２を封止する際には、半導体素子２の周囲は金属板３１、絶縁物３２、金属箔３３ａ・３３ｂ、および上部電極４に囲まれた空間となっているので、成形型を用いることなく該空間に封止樹脂を注入して樹脂封止を行うことが可能となっている。
従って、成形型を用いて樹脂封止を行う場合のように、半導体装置１の厚み寸法を高精度に維持する必要がなく、封止樹脂５の使用量も少量に抑えることも可能となる。
また、成形型を用いないので、半導体装置１の組立工程でスペーサ治具の組み付け・取り外しを行う必要もなく、加圧により半導体素子２の信頼性が低下する心配もない。 Thus, in the semiconductor device 1, when the semiconductor element 2 is sealed with the sealing resin 5, the periphery of the semiconductor element 2 is covered with the metal plate 31, the insulator 32, the metal foils 33 a and 33 b, and the upper electrode 4. Since it is an enclosed space, it is possible to perform resin sealing by injecting a sealing resin into the space without using a mold.
Therefore, it is not necessary to maintain the thickness dimension of the semiconductor device 1 with high accuracy as in the case where resin sealing is performed using a mold, and the amount of the sealing resin 5 used can be suppressed to a small amount.
Further, since no molding die is used, it is not necessary to assemble / remove the spacer jig in the assembly process of the semiconductor device 1, and there is no fear that the reliability of the semiconductor element 2 will be reduced by pressurization.

また、基板３の絶縁物３２および金属箔３３ａの厚み寸法は半導体素子２の厚み寸法よりも大きく構成されているので、半導体装置１において上部電極４をはんだ接合する際には、半導体素子２の厚み寸法や半導体素子２を接合するはんだ６の厚み寸法の精度にかかわらず、基板３の厚み寸法により半導体装置１の厚み寸法を規制することができる。
つまり、基板３の絶縁物３２および金属箔３３ａをスペーサとして用いているので、従来のように寸法精度が高い半導体素子２を用いたり、スペーサ治具を用いたりしなくても半導体装置１の厚み寸法を一定寸法に維持することができ、金属板３１および上部電極４の外面に封止樹脂５を付着させることなく、成形型を用いたトランスファーモールドを行うことも可能である。 Further, since the thickness dimension of the insulator 32 and the metal foil 33 a of the substrate 3 is configured to be larger than the thickness dimension of the semiconductor element 2, when the upper electrode 4 is soldered in the semiconductor device 1, Regardless of the thickness dimension or the accuracy of the thickness dimension of the solder 6 that joins the semiconductor element 2, the thickness dimension of the semiconductor device 1 can be regulated by the thickness dimension of the substrate 3.
That is, since the insulator 32 and the metal foil 33a of the substrate 3 are used as spacers, the thickness of the semiconductor device 1 can be obtained without using the semiconductor element 2 with high dimensional accuracy as in the prior art or using a spacer jig. The dimensions can be kept constant, and transfer molding using a molding die can be performed without attaching the sealing resin 5 to the outer surfaces of the metal plate 31 and the upper electrode 4.

〔第二実施形態〕
次に、本発明にかかる第二実施形態について説明する。
図６に示す半導体装置５１は、ＩＧＢＴやサイリスタ等のパワー素子に構成される半導体素子５２と、該半導体素子５２が実装される基板５３と、半導体素子５２の上面に接合される上部電極５４とを備えている。
図７（ａ）に示すように、基板５３は、銅板等の金属板５３ａにエポキシ系接着剤等の接着性を有するシート状の絶縁物５３ｂを用いて銅箔等の金属箔５３ｃを貼設して構成されている。 [Second Embodiment]
Next, a second embodiment according to the present invention will be described.
A semiconductor device 51 shown in FIG. 6 includes a semiconductor element 52 configured as a power element such as an IGBT or a thyristor, a substrate 53 on which the semiconductor element 52 is mounted, and an upper electrode 54 bonded to the upper surface of the semiconductor element 52. It has.
As shown in FIG. 7A, the substrate 53 has a metal foil 53c such as a copper foil pasted on a metal plate 53a such as a copper plate by using a sheet-like insulator 53b having adhesiveness such as an epoxy adhesive. Configured.

この基板５３に、以下のように半導体素子５２を実装する等して、半導体装置１が構成される。
まず、図７（ｂ）に示すように、半導体素子５２を、基板５３の金属板５３ａはんだ５６を用いて実装する。この場合、半導体素子５２の下面と金属板５３ａとを接合するはんだ６の厚さは、第一実施形態の場合と同様に、接合部の信頼性を確保するために必要な厚さとなっている。
また、半導体素子５２に接合される金属板５３ａは半導体装置５１の下部電極の役割を果たすものである。
半導体素子５２を基板５３に実装した後、図７（ｂ）に示すように、半導体素子２に形成される制御用信号を与えるためのパッドと前記金属箔５３ｃとをボンディングワイヤー５７にて接続する。なお、金属箔５３ｃは信号線取り出し用の直線パターンに形成されている。 The semiconductor device 1 is configured by mounting the semiconductor element 52 on the substrate 53 as follows.
First, as shown in FIG. 7B, the semiconductor element 52 is mounted using the metal plate 53 a solder 56 of the substrate 53. In this case, the thickness of the solder 6 that joins the lower surface of the semiconductor element 52 and the metal plate 53a is a thickness necessary to ensure the reliability of the joint, as in the first embodiment. .
Further, the metal plate 53 a bonded to the semiconductor element 52 serves as a lower electrode of the semiconductor device 51.
After mounting the semiconductor element 52 on the substrate 53, as shown in FIG. 7B, a pad for supplying a control signal formed on the semiconductor element 2 and the metal foil 53c are connected by a bonding wire 57. . The metal foil 53c is formed in a linear pattern for taking out signal lines.

次に、図８、図９に示すように、基板５３の金属板５３ａ上に、シート状の絶縁樹脂等にて構成される絶縁物５８を貼着する。
絶縁物５８は、実装された半導体素子５２の周囲を囲むように略環状に形成されており、本実施形態では、絶縁物５８は前記金属箔５３ｃが形成された部分以外の三方を囲む、平面視「コ」字状に形成されている。
また、前記絶縁物５８は熱硬化性樹脂にて構成されており、現時点では金属板５３ａ上への接着は仮接着状態である。 Next, as shown in FIGS. 8 and 9, an insulator 58 composed of a sheet-like insulating resin or the like is stuck on the metal plate 53 a of the substrate 53.
The insulator 58 is formed in a substantially annular shape so as to surround the periphery of the mounted semiconductor element 52. In this embodiment, the insulator 58 is a plane that surrounds three sides other than the portion where the metal foil 53 c is formed. It is formed in a “U” shape.
The insulator 58 is made of a thermosetting resin, and at this time, the adhesion on the metal plate 53a is in a temporarily adhered state.

図１０（ａ）に示すように、絶縁物５８を仮接着した後、該絶縁物５８上に上部電極５４を貼着し、絶縁物５８を加熱して硬化させる。これにより、金属板５３ａと絶縁物５８、および上部電極５４と絶縁物５８とが本接着される。
これにより、金属板５３ａ、絶縁物５８、および上部電極５４により囲まれた空間５９が形成されることとなり、実装された半導体素子５２がこの空間５９内に位置することとなる。空間５９における、金属箔５３ｃが配置されていて絶縁物５８が形成されていない箇所には開口部５９ａが形成されている。
また、絶縁物５８は、下部電極となる金属板５３ａと上部電極５４との間に介在される支持体となっている。 As shown in FIG. 10A, after the insulator 58 is temporarily bonded, the upper electrode 54 is stuck on the insulator 58, and the insulator 58 is heated and cured. Thereby, the metal plate 53a and the insulator 58, and the upper electrode 54 and the insulator 58 are permanently bonded.
Thus, a space 59 surrounded by the metal plate 53a, the insulator 58, and the upper electrode 54 is formed, and the mounted semiconductor element 52 is located in the space 59. An opening 59a is formed in the space 59 where the metal foil 53c is arranged and the insulator 58 is not formed.
The insulator 58 serves as a support body interposed between the metal plate 53a serving as the lower electrode and the upper electrode 54.

図１０（ｂ）に示すように、金属板５３ａおよび上部電極５４と絶縁物５８とを本接着した後、半導体素子５２の上面と上部電極５４とをはんだ６にて接合する。
さらに、該開口部５９ａから空間５９内へ、エポキシ系樹脂等の封止樹脂５５を充填して硬化させ、半導体素子５２を封止する（図６図示）。
この樹脂封止により半導体素子５２自身や半導体素子５２のはんだ接合部の信頼性を確保している。
また、空間５９内への封止樹脂５５の充填は、液状の封止樹脂５５をディスペンサー等により開口部５９ａから直接ポッティング注入すること等により行われる。
また、支持体としての絶縁物５８における、上部電極５４との接合面と、下部電極である金属板５３ａとの接合面とは絶縁されているため、上部電極５４と金属板５３ａとの間に支持体を介装することで、上部電極５４と金属板５３ａとが電気的に接続されることはない。 As shown in FIG. 10B, after the metal plate 53 a and the upper electrode 54 and the insulator 58 are bonded together, the upper surface of the semiconductor element 52 and the upper electrode 54 are joined with the solder 6.
Further, a sealing resin 55 such as an epoxy resin is filled into the space 59 from the opening 59a and cured to seal the semiconductor element 52 (shown in FIG. 6).
This resin sealing ensures the reliability of the semiconductor element 52 itself and the solder joints of the semiconductor element 52.
The space 59 is filled with the sealing resin 55 by directly injecting the liquid sealing resin 55 from the opening 59a with a dispenser or the like.
In addition, in the insulator 58 as a support, the bonding surface with the upper electrode 54 and the bonding surface with the metal plate 53a which is the lower electrode are insulated, so the gap between the upper electrode 54 and the metal plate 53a is insulated. By interposing the support, the upper electrode 54 and the metal plate 53a are not electrically connected.

このように、半導体装置５１においても、成形型を用いることなく前記空間５９内に封止樹脂５５を注入して樹脂封止を行うことが可能となっており、半導体装置５１の厚み寸法を高精度に維持する必要がなく、封止樹脂５５の使用量も少量に抑えることも可能となる。また、半導体装置５１の組立工程が煩雑になることがなく、半導体素子５２の信頼性が低下する心配もない。   Thus, also in the semiconductor device 51, it is possible to perform the resin sealing by injecting the sealing resin 55 into the space 59 without using a molding die. It is not necessary to maintain the accuracy, and the amount of the sealing resin 55 used can be reduced to a small amount. Further, the assembly process of the semiconductor device 51 is not complicated, and there is no fear that the reliability of the semiconductor element 52 is lowered.

また、半導体装置５１の厚み寸法は、半導体素子２の厚み寸法や半導体素子２を接合するはんだ６の厚み寸法の精度にかかわらず、絶縁物５８の厚み寸法により規制されているので、スペーサ治具を用いたりしなくても半導体装置５１の厚み寸法を一定寸法に維持することができ、金属板５３ａおよび上部電極５４の外面に封止樹脂５５を付着させることなく、成形型を用いたトランスファーモールドを行うことも可能である。   The thickness dimension of the semiconductor device 51 is regulated by the thickness dimension of the insulator 58 regardless of the thickness dimension of the semiconductor element 2 and the accuracy of the thickness dimension of the solder 6 that joins the semiconductor element 2. The thickness of the semiconductor device 51 can be kept constant without using a mold, and a transfer mold using a mold can be used without attaching the sealing resin 55 to the outer surfaces of the metal plate 53a and the upper electrode 54. It is also possible to perform.

なお、本実施形態では、予め金属箔５３ｃが金属板５３ａ上に貼設されていたが、半導体装置５１は封止樹脂５５による樹脂封止時に開口部５９ａを備えた空間５９が形成されていればいいので、金属箔５３ｃが貼設されていない状態の金属板５３ａに半導体素子５２をはんだ接合し、絶縁物５８を仮接着した後に、金属箔５３ｃの金属板５３ａ上への貼設および絶縁物５８への上部電極５４の貼設を行って空間５９を構成しても、同様の効果を奏することが可能である。   In the present embodiment, the metal foil 53c is pasted on the metal plate 53a in advance. However, the semiconductor device 51 has a space 59 provided with an opening 59a when the resin is sealed with the sealing resin 55. Therefore, after the semiconductor element 52 is soldered to the metal plate 53a without the metal foil 53c being pasted and the insulator 58 is temporarily bonded, the metal foil 53c is pasted and insulated on the metal plate 53a. Even if the upper electrode 54 is attached to the object 58 to form the space 59, the same effect can be obtained.

本発明にかかる半導体装置を示す側面断面図である。It is side surface sectional drawing which shows the semiconductor device concerning this invention. 半導体装置を構成する基板を示す側面断面図である。It is side surface sectional drawing which shows the board | substrate which comprises a semiconductor device. 半導体装置を構成する基板を示す平面図である。It is a top view which shows the board | substrate which comprises a semiconductor device. （ａ）は基板に半導体素子を実装した状態を示す側面断面図、（ｂ）は実装した半導体素子と基板の金属箔とをボンディングワイヤーにて接続した状態を示す側面断面図である。(A) is side surface sectional drawing which shows the state which mounted the semiconductor element on the board | substrate, (b) is side surface sectional drawing which shows the state which connected the mounted semiconductor element and the metal foil of the board | substrate with the bonding wire. （ａ）は実装した半導体素子上にはんだを供給した状態を示す側面断面図、（ｂ）は半導体素子上に上部電極を接合した状態を示す側面断面図である。(A) is side sectional drawing which shows the state which supplied the solder on the mounted semiconductor element, (b) is side sectional drawing which shows the state which joined the upper electrode on the semiconductor element. 半導体装置の第二の実施形態を示す側面断面図である。It is side surface sectional drawing which shows 2nd embodiment of a semiconductor device. （ａ）は図６における半導体装置を構成する基板を示す側面断面図、（ｂ）は図６における半導体装置の基板に半導体素子を実装してワイヤーボンディングを施した状態を示す側面断面図である。(A) is side surface sectional drawing which shows the board | substrate which comprises the semiconductor device in FIG. 6, (b) is side surface sectional drawing which shows the state which mounted the semiconductor element on the board | substrate of the semiconductor device in FIG. 6, and performed wire bonding. . 図６の半導体装置において、半導体素子が実装された基板に絶縁物を貼着した状態を示す側面断面図である。FIG. 7 is a side cross-sectional view illustrating a state where an insulator is attached to a substrate on which a semiconductor element is mounted in the semiconductor device of FIG. 6. 図６の半導体装置において、半導体素子が実装された基板に絶縁物を貼着した状態を示す平面図である。FIG. 7 is a plan view showing a state where an insulator is attached to a substrate on which a semiconductor element is mounted in the semiconductor device of FIG. 6. （ａ）は図６の半導体装置において、絶縁物上に上部電極を貼着した状態を示す側面断面図、（Ｂ）は図６の半導体装置において、半導体素子と上部電極とをはんだ接合した状態を示す側面断面図である。6A is a side cross-sectional view showing a state in which the upper electrode is attached on the insulator in the semiconductor device of FIG. 6, and FIG. 6B is a state in which the semiconductor element and the upper electrode are solder-bonded in the semiconductor device of FIG. FIG. 従来の半導体装置を示す側面断面図である。It is side surface sectional drawing which shows the conventional semiconductor device.

符号の説明Explanation of symbols

１ 半導体装置
２ 半導体素子
３ 基板
４ 上部電極
５ 封止樹脂
６ はんだ
３１ 金属板
３２ 絶縁物
３３ａ・３３ｂ 金属箔
３５ 素子実装部
３５ａ 開口部 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor element 3 Board | substrate 4 Upper electrode 5 Sealing resin 6 Solder 31 Metal plate 32 Insulator 33a * 33b Metal foil 35 Element mounting part 35a Opening part

Claims (6)

半導体素子の両面側に一対の電極が対向配置される半導体装置であって、
該一対の電極間に、半導体素子の厚みよりも大きな厚みを有する支持体が介在しており、
該支持体における一方の電極との接合面と、他方の電極との接合面とが絶縁されていることを特徴とする半導体装置。 A semiconductor device in which a pair of electrodes are arranged opposite to each other on both sides of a semiconductor element,
A support having a thickness larger than the thickness of the semiconductor element is interposed between the pair of electrodes,
A semiconductor device, wherein a bonding surface with one electrode of the support is insulated from a bonding surface with the other electrode. 前記支持体は、半導体素子の周囲を囲む略環形状に形成されることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the support is formed in a substantially ring shape surrounding the periphery of the semiconductor element. 前記半導体装置における、前記一対の電極および支持体にて囲まれた空間には、電極または支持体にて被覆されていない開口部が存在することを特徴とする請求項２に記載の半導体装置。   3. The semiconductor device according to claim 2, wherein an opening that is not covered with the electrodes or the support is present in a space surrounded by the pair of electrodes and the support in the semiconductor device. 請求項１〜請求項３の何れかに記載の半導体装置を、上型および下型からなる成形型のキャビティ内に封入し、該キャビテイ内に封止樹脂を充填することにより、半導体素子の樹脂封止を行うことを特徴とする半導体装置の製造方法。   The semiconductor device according to any one of claims 1 to 3 is sealed in a cavity of a molding die composed of an upper die and a lower die, and a sealing resin is filled in the cavity to thereby obtain a resin for a semiconductor element. A method for manufacturing a semiconductor device, wherein sealing is performed. 請求項２または請求項３に記載の半導体装置における、前記一対の電極および支持体にて囲まれた空間に、封止樹脂を直接注入することにより、該空間内に配置される半導体素子の樹脂封止を行うことを特徴とする半導体装置の製造方法。   The resin of the semiconductor element arrange | positioned in this space in the semiconductor device of Claim 2 or Claim 3 by inject | pouring sealing resin directly into the space enclosed by the said pair of electrode and support body A method for manufacturing a semiconductor device, wherein sealing is performed. 前記半導体装置は、一方の電極上に支持体を貼着する工程、一方の電極上に半導体素子の一面を接合する工程、支持体上に他方の電極を貼着する工程、他方の電極と半導体素子の他面とを接合する工程を順に経た後に、半導体素子の樹脂封止工程が行われることを特徴とする請求項４または請求項５に記載の半導体装置の製造方法。
The semiconductor device includes a step of attaching a support on one electrode, a step of bonding one surface of a semiconductor element on one electrode, a step of attaching the other electrode on the support, the other electrode and a semiconductor 6. The method of manufacturing a semiconductor device according to claim 4, wherein a resin sealing step of the semiconductor element is performed after sequentially performing a step of joining the other surface of the element.
JP2004228509A 2004-08-04 2004-08-04 Semiconductor device and manufacturing method therefor Pending JP2006049572A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007066401A1 (en) * 2005-12-08 2007-06-14 Fujitsu Limited Process for producing electronic part, process for producing heat conducting member, and method of mounting heat conducting member for electronic part

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007066401A1 (en) * 2005-12-08 2007-06-14 Fujitsu Limited Process for producing electronic part, process for producing heat conducting member, and method of mounting heat conducting member for electronic part
JPWO2007066401A1 (en) * 2005-12-08 2009-05-14 富士通株式会社 Method for manufacturing electronic component, method for manufacturing heat conductive member, and method for mounting heat conductive member for electronic component
JP4757880B2 (en) * 2005-12-08 2011-08-24 富士通株式会社 Method for manufacturing electronic component, method for manufacturing heat conductive member, and method for mounting heat conductive member for electronic component
US8709197B2 (en) 2005-12-08 2014-04-29 Fujitsu Limited Method of making electronic component and heat conductive member and method of mounting heat conductive member for electronic component

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