JP2006040976A - Photodetector - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a photodetector applicable to such communication as requiring a wide dynamic range at high speed. <P>SOLUTION: When photocurrent output from a photodiode 14 for detecting optical power lowers below a specified level, output from a comparator COMP1 is switched abruptly but since a low-pass filter SC removes harmonic components, its output, i.e. the voltage at a gain control terminal VG, lowers gradually. Since the amount of current flowing between the source-drain of an N type MOS transistor GCT for gain regulation being applied with that voltage decreases gradually, the amount of current flowing through a resistor R1 decreases and the resistance Rx of the combined resistor in a gain regulation amplifier AMP increases thus increasing the gain thereof up to a specified level. Although the time required for the output voltage to increase and saturate is within 3 μs, adverse effect on a PHY chip being connected with the post-stage can be suppressed by changing the gain of output voltage slowly. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a photodetector.

  In communication using POF (plastic optical fiber), a device having a high speed and a wide dynamic range is required.

  There is a need for photodetectors for such applications.

  Conventionally, in order to widen the dynamic range, it is widely known to use a feedback circuit for a current-voltage conversion amplifier that converts a current output of a light receiving element into a voltage. (See Patent Document 1).

  There is also known a receiving circuit of an optical coupling device in which a dummy photodiode is provided to shape a waveform so as to improve a common-mode noise removal ratio. Specifically, a receiving photodiode and a light-shielded photodiode are connected. It is known to perform light detection by taking the difference between these after adjusting the gain of the output (see Patent Document 2).

  A circuit having control means for changing the output of incident light of the second photodetecting element in accordance with the output from the first photodetecting element is also known (see Patent Document 3).

  The optical input is branched into two, one is delayed and given to the light receiving element, the other output light is given to another light receiving element, and the output voltage or the output voltage of the light receiving element built in the optical amplifier is the reference value. Device that reduces the bias voltage of the light receiving element when it exceeds the limit, or reduces the input light to the light receiving element by controlling the attenuator, or attenuates the output light of the optical amplifier and supplies it to the APD as the light receiving element Is known (see Patent Document 4).

In order to expand the dynamic range and save power, the current output from the light receiving element is monitored by a monitor circuit, and the monitored value is compared with a predetermined reference value to determine whether the received light level is larger or smaller than the appropriate value. A configuration is also known in which, based on the determination result, either a through circuit constituting a multistage amplifier connected to a light receiving element or a gain adjusting amplifier circuit is selected. In addition, a configuration is also shown in which the output of the monitor circuit is given to a variable gain type first stage amplifier circuit so that gain control according to the light reception level is possible (see Patent Document 5).
Japanese Patent Laid-Open No. 2-143731 JP 2002-353495 A JP 2000-200902 A JP-A-11-41180 Japanese Patent Laid-Open No. 10-107738

  However, when the conventional photodetector is used for the communication requiring a high speed and a wide dynamic range as described above, and when the gain is switched sharply, an error may occur on the subsequent circuit side. Specifically, in the case of a communication system that obtains synchronization by extracting a clock from a received signal, there is a problem that an error occurs on the PLL (phase locked loop) circuit side.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a photodetector that can be applied to communication that requires a wide dynamic range at high speed.

  In order to solve the above-described problem, the photodetector according to the present invention is a first detector to which a light receiving first photodiode, a light-shielded second photodiode, and outputs of the first and second photodiodes are input. 1 differential amplifier, a gain adjustment amplifier interposed between the first and second photodiodes and the first differential amplifier, an optical power detection unit for detecting optical power at a comparator output, and an optical power detection unit And a low-pass filter interposed between the output terminal of the amplifier and the gain adjustment terminal of the gain adjustment amplifier.

  According to this photodetector, since the outputs of the first and second photodiodes are input to the first differential amplifier, the dark current flowing through both is removed, and low noise is achieved. Since the gain adjustment amplifier can adjust the gain according to the input to the gain adjustment terminal, the saturation of the amplifier is suppressed and the dynamic range is expanded by inputting the output of the optical power detection unit to the gain adjustment terminal. be able to.

  Since the optical power detector uses the output of the comparator, the output can be changed at high speed with respect to the optical power exceeding the specified level. However, in high-speed communication, an error may occur in a conventional photodetector, particularly in the case of a reception system that obtains synchronization by extracting a clock from a reception signal on the rear stage side. This is because, for example, the output signal from the comparator exceeds the frequency (phase) that can be followed by a PLL (phase-locked loop) circuit that extracts the clock and obtains synchronization.

  In this photodetector, a low-pass filter is interposed between the optical power detector and the gain adjustment terminal, so the high-frequency component (harmonic component) contained in the square wave of the comparator output is cut and the comparator output By slowly changing the value, the rate of change of the input to the gain adjustment terminal can be limited, and errors in the subsequent circuit can be suppressed. Therefore, high-speed communication is possible. The low-pass filter can be configured using a charge / discharge function using a capacitor.

  The optical power detection unit includes a third photodiode for light reception, a shielded fourth photodiode, a second differential amplifier to which outputs of the third and fourth photodiodes are input, and a second differential. It is desirable to include the above-described comparator to which the output of the amplifier is input.

  In this case, since the outputs of the third and fourth photodiodes are input to the second differential amplifier, the dark current flowing through both of them is removed, and a low noise output can be obtained from the second differential amplifier. This is input to the comparator. When the optical power exceeding the reference level is input to the comparator, the output is switched.

  The gain adjustment amplifier includes a plurality of resistors interposed in parallel between the input and output terminals of the operational amplifier, and a transistor connected in series with the resistors, and the control terminal of the transistor may be the above-described gain adjustment terminal. preferable. In this case, since the resistance value of the resistor connecting between the input and output terminals of the operational amplifier changes according to the input to the gain adjustment terminal, gain adjustment can be performed.

  The photodetector of the present invention can be applied to communications that require a wide dynamic range at high speed.

  Hereinafter, the photodetector according to the embodiment will be described. The same code | symbol is used for the same element and the overlapping description is abbreviate | omitted.

  FIG. 1 is a perspective view of the photodetector. FIG. 2 is a cross-sectional view of the photodetector taken along arrows II-II.

  The photodetector 10 is configured by resin-sealing photodiodes 12 and 14 for receiving light, photodiodes 12 'and 14' shielded from light, and a monolithic circuit board 20. More specifically, the substrate 20 is resin-sealed with a transparent resin while being fixed on the lead frame 34, and the mold portion 36 for resin-sealing the substrate 20 has a substantially rectangular parallelepiped shape.

  The substrate 20 and the lead frame 34 are electrically connected by wires 38, and pins 40 electrically connected to the lead frame 34 are provided to protrude outside the mold portion 36. Therefore, the optical signal received by the photodetector 10 is read out via the pin 40. A hemispherical lens portion 36 a is formed on the surface of the mold portion 36 at a position facing the photodiode 12 so that the signal light is efficiently incident on the photodiode 12.

  FIG. 3 is a cross-sectional view of a light detection unit incorporating a light detector.

  The photodetector 10 is used by being arranged so that its lens portion 36a faces the emission end of the plastic optical fiber 100 that propagates signal light. Here, a ferrule 102 is provided at the tip of the plastic optical fiber 100 to protect the tip of the plastic optical fiber 100, and a fiber connector 104 is further provided.

  The optical detector 10 is positioned with respect to the output end of the plastic optical fiber 100 by inserting the fiber connector 104 and the optical detector 10 into the optical connector groove and the optical detector groove formed in the receptacle 106, respectively. . The photodetector 10 inserts the lead pin 40 on the circuit board CB and electrically connects it to the PHY (physical layer) chip 107.

  FIG. 4 is a block diagram of the light detection unit.

The photodetector 10 has six lead pins (terminals) 40. Each lead pin 40 has a power supply voltage application terminal Vcc, an LVDS output terminal V _OUT , an LVDS inversion output terminal V _OUT bar, and a signal detection terminal SD. The power management terminal PM and the ground terminal GND are configured. Printed wiring is provided on the circuit board CB, and the LVDS output terminal (inverted output terminal) of the photodetector 10 is connected to the PHY chip 107 via this wiring.

  In addition, LVDS (Low Voltage Differential Signaling) is a video image or 3-D from a camera to a PC or printer via a local area network (LAN), a telephone line, and a satellite line connected to a home digital video deck. A technology for transmitting graphics and image data, in which data communication is performed with a differential signal having a very small amplitude through a single balanced cable or two wiring patterns formed of a PCB (printed circuit board). This differential data transmission system has a characteristic that it is not easily affected by common-mode noise.

  LVDS can transmit data on a single channel at a speed of several hundred to several thousand Mbps, and since it outputs a small-amplitude signal in the current mode / drive circuit, ringing and switching spikes are unlikely to occur. It is possible to perform signal transmission with low power consumption and low noise over a frequency band.

  The PLL circuit inside the PHY chip 107 generates a timing for reading a signal in synchronization with the LVDS output signal of the photodetector 10. The photodetector 10 performs gain adjustment, but the phase changes simultaneously with the output signal amplitude when the gain is switched. Therefore, the output signal shifts on the time axis simultaneously with the gain switching. When gain switching is performed instantaneously, this phase change also occurs instantaneously, so that the PLL circuit in the PHY chip 107 cannot follow the instantaneous change and causes a communication error.

  FIG. 5 is a timing chart of the output signal of the photodetector 10 and the internal signal of the PLL circuit.

  The internal signal of the PLL circuit generates timing in synchronization with the output signal of the photodetector. The PLL circuit operates so that the timing of the arrow of the internal signal (b) of the PLL circuit coincides with the timing of the arrow shown in the output signal (a) of the photodetector 10. The value of the output signal is shown below the internal signal (b).

  When gain adjustment is performed in the photodetector 10, the phase of the output signal (c) is shifted as indicated by an arrow B. In this case, the internal signal (d) of the PLL circuit cannot follow the phase shift and a communication error occurs. Will be shown. Therefore, if gain switching is performed slowly over a period of time that the PLL circuit in the PHY chip 107 can sufficiently follow, a phase change also occurs slowly, and a communication error does not occur.

  The photodetector 10 includes an optical power detection unit that detects the power of the photodiode, and a gain adjustment amplifier that performs the above-described gain adjustment based on a signal from the optical power detection unit. When the gain switching by the gain adjustment amplifier is abrupt, the above-described problem occurs. Therefore, in the photodetector 10, a low-pass filter is provided between the optical power detector and the gain adjustment amplifier.

  FIG. 6 is a circuit diagram of a low-pass filter SC with a bias circuit.

  The output of the optical power detector is input to the determination output terminal JO. The judgment output terminal JO constitutes the control terminal of the transistor Q1. Between the power supply potential Vcc and the ground potential, a transistor Q2, a transistor Q1, and a transistor Q3 are sequentially interposed in series. A connection potential (terminal VG) between the transistor Q1 and the transistor Q3 is connected to the ground via the capacitor C1. It is connected to the. Here, the transistor Q3 and the capacitor C1 are connected in parallel to the connection potential.

  For example, when the transistor Q1 is turned on by inputting a high level signal to the determination output terminal JO, a current of 2 × I flows from the power supply potential Vcc. This 2 × I is branched, and the current I is supplied to the transistor Q3 and the current I is supplied to the capacitor C1. It can be considered that these currents are supplied from a current source composed of a current mirror circuit (bias circuit) IS connected as shown in the figure and transistors Q2 and Q3 connected to the current mirror circuit IS.

  FIG. 7 is a circuit diagram for explaining the function of the low-pass filter when the transistor is ON.

  When the optical power increases and, for example, a high-level signal is input to the determination output terminal JO, the transistor Q1 is turned on, and the accumulation of electric charge in the capacitor C1 is completed with the current I supplied from the current source I2. Until then, the potential of the gain adjustment terminal VG continues to rise gradually. The current I also flows through the current source I1. In other words, most of the harmonic components contained in the square wave input to the determination output terminal JO are removed, and a smoothly rising voltage curve is obtained.

  In this case, the gain may be controlled to decrease as the optical power increases.

  In order to increase the gain of the gain adjusting amplifier AMP, the resistance value of the feedback resistor of the operational amplifier OP may be increased. To decrease the gain, the resistance value of the feedback resistor of the operational amplifier OP may be decreased. The feedback resistor is a combined resistance of a plurality of resistors R1 and R2 interposed in parallel between the input and output terminals of the operational amplifier OP, and is given by a resistance value Rx = (R1 × R2) / (R1 + R2) of the combined resistance. It is done. Note that the sign of the resistance is indicated by the same sign as the resistance value. A gain adjusting transistor GCT is connected in series to the resistor R1, and when the transistor GCT is turned on (conductive), the resistor R1 is incorporated into the combined resistor Rx, and when the transistor GCT is turned off (disconnected), the resistance of the resistor R1 The value is equivalent to infinity. The resistor R1 is set to 750Ω, the resistor R2 is set to 10kΩ, and the resistance value Rx of the combined resistor when the transistor is ON is about 700Ω.

  When the transistor GCT is turned on, the resistance value Rx of the combined resistor is reduced, and when the transistor GCT is turned off, the resistance value Rx is increased.

  That is, when the optical power increases, the gain should be decreased. In this case, the resistance value Rx of the combined resistor must be decreased. Therefore, the transistor GCT must be turned on, and the potential of the control terminal VG is Since the power increases when the optical power increases, an N-type MOS transistor that is turned on as the control terminal voltage increases may be used as the transistor GCT. Incidentally, the transistor Q1 having the determination output terminal JO turned ON as the voltage level rises as a gate is composed of an N-type MOS transistor.

  As described above, the gain adjustment amplifier AMP includes a plurality of resistors R1 and R2 interposed in parallel between the input and output terminals of the operational amplifier OP, and a transistor GCT connected in series to the resistor R1. The control terminal of GCT is a gain adjustment terminal VG. Since the resistance value or the number of resistors connected between the input and output terminals of the operational amplifier OP changes according to the input to the gain control terminal, gain adjustment can be performed.

  FIG. 8 is a circuit diagram for explaining the function of the low-pass filter when the transistor is OFF.

  When the optical power is reduced and, for example, a low level signal is input to the determination output terminal JO, the transistor Q1 is turned OFF, and the charge accumulated in the capacitor C1 continues to flow to the ground via the current source I1. Meanwhile, the potential of the gain adjustment terminal VG continues to gradually decrease. In other words, most of the harmonic components included in the square wave input to the determination output terminal JO are removed, and a smoothly decreasing voltage curve is obtained.

  In this case, the gain may be controlled to increase as the optical power decreases.

  Since the potential of the gain adjustment terminal VG gradually decreases, the transistor GCT is turned off, the resistance value Rx of the combined resistance increases, and the gain of the gain adjustment amplifier AMP increases.

  FIG. 9 is a circuit diagram of the photodetector.

  The photodetector 10 includes a first photodiode 12 for light reception, a shielded second photodiode 12 ′, and a first differential amplifier to which outputs of the first and second photodiodes 12 and 12 ′ are input. It has DIF1. Since the outputs of the first and second photodiodes 12 and 12 'are input to the first differential amplifier, the dark current that flows through both of them is removed, and low noise is achieved.

  The photodetector 10 has a gain adjustment amplifier AMP interposed between the first and second photodiodes 12 and 12 'and the first differential amplifier DIF1. The function of the gain adjustment amplifier AMP is as described above. The gain adjustment amplifier AMP is a preamplifier. Since the gain adjustment amplifier AMP can adjust the gain according to the input to the gain adjustment terminal VG (in this example, the gate of the MOS transistor), the output of the optical power detection unit OPD is gained through the low-pass filter SC. By inputting to the adjustment terminal VG, saturation of the gain adjustment amplifier AMP can be suppressed and the dynamic range can be expanded. The optical power detector OPD detects the optical power with a comparator output (output of COMP1). Since the optical power detector OPD uses the comparator output, the output can be changed at high speed with respect to the optical power exceeding the specified level.

  However, in high-speed communication, particularly in the case where a PHY chip having a PLL circuit is arranged on the rear stage side, when phase synchronization is performed by this PLL circuit, a communication error occurs as described above. In this photodetector 10, a low-pass filter SC is interposed between the output terminal JO of the optical power detector OPD and the gain adjustment terminal VG of the gain adjustment amplifier AMP.

  Therefore, the low-pass filter SC can cut the high-frequency component (harmonic component) from the square wave that changes stepwise as the comparator COMP1 and slowly change the comparator output. Therefore, the rate of change of the input to the gain adjustment terminal VG can be limited, and accordingly, the resistance value of the gain adjustment transistor that finally performs the ON / OFF switching also changes smoothly, thereby increasing the gain. The combined resistance value Rx to be determined also changes smoothly, realizing a smooth gain change, and suppressing errors in the subsequent circuit. That is, high-speed communication is possible.

  The optical power detector OPD includes a third photodiode 14 for receiving light, a shielded fourth photodiode 14 ′, and a second differential amplifier to which outputs of the third and fourth photodiodes 14 and 14 ′ are input. DIF2 and a comparator COMP1 to which the output of the second differential amplifier DIF2 is input.

  In this case, since the outputs of the third and fourth photodiodes 14 and 14 'are input to the second differential amplifier DIF2, the dark current that flows through both is removed, and the low-noise output is supplied to the second differential amplifier. It can be obtained from DIF2. The output of the second differential amplifier DIF2 is input to the comparator COMP1. When a photocurrent (optical power to the photodiode) exceeding the reference level (reference current Iref1) is input to the comparator, the output is switched. Here, when the optical power is high, a high level signal is output.

  The outputs (complementary signal: output signal and inverted output signal) of the first differential amplifier DIF1 are both input to the differential amplifier circuit D, and the complementary signal output from the first differential amplifier DIF1 is input to the LVDS level adjustment circuit L and level-adjusted. After that, it is output.

  When the output of the second differential amplifier DIF2 is input to the signal detection determination circuit SDJ and a photocurrent (optical power to the photodiode) exceeding the reference level (reference current Iref2) is input, the output is switched. , Output high level. A part of the output of the differential amplifier circuit D is input to the peak detector PJ, and is input to the NAND circuit S together with the output of the signal detection determination circuit SDJ. The output of the NAND circuit S determines whether or not an optical signal is input to the photodiodes 12 and 14 having a specified value or more, and outputs a determination result to the signal detection terminal SD, and the LVDS level adjustment circuit L according to the determination result. Adjusts the level of the LVDS signal.

  The input from the power management terminal PM is input to the power management determination circuit PMJ, and when the high level voltage is not applied to the power management determination circuit PMJ, the bias circuit BIAS is cut off and the entire circuit is shut down. The bias circuit BIAS supplies the power supply voltage supplied from the power supply terminal Vcc or the adjusted voltage to the entire circuit in addition to the differential amplifier circuit D, the first differential amplifier DIF1, and the gain adjustment amplifier AMP.

  The light receiving photodiodes 12 and 14 are arranged close to each other, and the shielded dummy photodiodes 12 'and 14' are also arranged close to each other. More specifically, a photodiode 14 that detects leakage light is positioned around the light receiving photodiode 12, and a dummy photodiode 14 ′ is positioned around the dummy photodiode 12 ′. Note that the amount of leakage light is smaller than the amount of light incident on the light receiving photodiode 12.

  Further, a capacitor CC1 is interposed between the gain adjustment amplifier AMP and the first differential amplifier DIF1, and capacitively couples them, and removes a low frequency component of a signal passing between them ( Low-pass cutoff filter). As a result, the DC component of the input voltage to the first differential amplifier DIF1 is cut, so that the operation restriction of the first differential amplifier DIF1 due to the output voltage of the gain adjustment amplifier AMP can be lifted. That is, the dynamic range of the gain adjustment amplifier AMP can be expanded. For example, when the capacitance of the capacitor CC1 is set to 8.2 pF, and a 65Ω resistor (not shown) is connected in parallel, the cutoff frequency is 300 kHz.

  A capacitor CC2 is also interposed between the first differential amplifier DIF1 and the differential amplifier circuit D. This cuts the direct current component of the complementary signal output from the first differential amplifier DIF1, thereby improving the minimum reception level. Other conditions regarding the capacitor CC2 are the same as those of the capacitor CC1.

  FIG. 10 is a graph showing the time dependence of the photocurrent.

  The photocurrent is 90 μA from 0 to 11 μs, but the photocurrent rapidly decreases after 11 μs.

  FIG. 11 is a graph showing the time dependence of the voltage of the gain adjustment terminal VG.

  After 11 μs, the photocurrent output of the photodiode for detecting the optical power decreases, so that the voltage of the gain adjustment terminal VG gradually decreases. Between the source and drain of the N-type MOS transistor GCT for gain adjustment to which this voltage is applied. The current flowing through the resistor R1 gradually decreases, the current flowing through the resistor R1 decreases, the resistance value Rx of the combined resistor increases, and the gain of the gain adjustment amplifier AMP gradually increases to a specified gain after 11 μs ( (See FIG. 8).

  FIG. 12 is a graph showing the time dependence of the output voltage of the gain adjustment amplifier AMP.

  The output voltage of the gain adjustment amplifier AMP gradually increases from 13 μs after 11 μs, and reaches the specified voltage before reaching 16 μs. In this case, the time from the rise of the output voltage to saturation is within 3 μs. Thus, by slowly changing the gain of the output voltage, it is possible to suppress adverse effects on the PHY chip connected to the subsequent stage. Note that the delay time from when the comparator output is switched to when the output voltage of the gain adjustment amplifier AMP is saturated can be adjusted by the values of the current source I1 and the capacitor C1 in FIG. The low-pass filter also functions as a delay circuit.

  FIG. 13 is a plan view of the photodiode.

  The photodiode 14 surrounds the periphery of the photodiode 12, the shape of the photodiode 12 is circular, and the shape of the photodiode 14 is annular, and these are arranged concentrically. Either one or both of the outer edges of the photodiodes 12 and 14 may be a polygon such as a square or a hexagon.

  FIG. 14 is a plan view of the photodiode.

  The photodiode 14 may be composed of a plurality of (for example, four) separate detection units 14 a, and each detection unit 14 a may be arranged along the edge of the photosensitive region of the photodiode 12. In this case, each of the plurality of detection units 14 a is arranged at equal intervals along the edge of the photosensitive region of the photodiode 12, and each of the plurality of detection units 14 a is the center of the photosensitive region of the photodiode 12. It is preferable that they are arranged equidistant from each other.

  The shape of the photodiodes 12 ′ and 14 ′ can be set to be the same as that of the photodiodes 12 and 14.

  FIG. 15 is a diagram illustrating an arrangement example of the internal circuit of the photodetector.

  In the above example, the photodiodes 12 and 14 and the internal circuits of the photodiodes 12 ′ and 14 ′ and the photodetector 10 are formed in the same semiconductor substrate 20. However, in this example, the photodiodes 12 and 14 and the photodiodes 12 ′ and 14 ′ are formed in the same semiconductor substrate SM, and a separate integrated circuit chip 20 ′ is provided via the wires W. These are embedded in the resin mold portion 36.

  That is, the circuit inside the photodetector 10 is monolithically formed in the integrated circuit chip 20 '. Note that the internal circuit of the PHY chip may be formed in the integrated circuit chip 20 ', and the photodiode may be formed in the same semiconductor substrate.

  FIG. 16 is a circuit diagram showing a circuit for gain adjustment amplifier AMP and comparator output.

  In the above example, the comparator output has changed in one step, but this can be set in two steps. In this example, a comparator COMP1 ′ and a low-pass filter SC ′ further connected to the output terminal Y of the second differential amplifier DIF2 in FIG. 9 are provided, and in parallel with the resistor R1 on the gain adjustment amplifier AMP side. A resistor R1 ′ and a transistor GCT ′ are connected. The functions of the comparator COMP1 ′, the low-pass filter SC ′, the gain adjustment terminal VG ′, the resistor R1 ′, and the transistor GCT ′ are the functions of the comparator COMP1, the low-pass filter SC, the gain adjustment terminal VG, the resistor R1, and the transistor GCT, respectively. Although the same, the current value of the reference current Iref1 ′ and the resistance value of the resistor R1 ′ are different.

  In the above example, the resistance values of the resistors R2 and R1 are R2> R1. In this example, R2> R1> R1 ′ is set. These resistance values may be the same, but the reference current Iref1 'is set to be larger than Iref1. Note that the comparator output may change in three or more steps, and a voltage input configuration may be employed as the input to the comparator.

  FIG. 17 is a circuit diagram of an actual optical power detection circuit.

An optical power detection photodiode 14 and a light-shielded photodiode 14 'are connected in parallel between the specified potential and the ground potential, and the photodiode 14 includes a plurality of N-type MOSs constituting an input side line. Transistors are connected in series, and a plurality of N-type MOS transistors constituting the output side line are connected in series to the photodiode 14 ', and these input side line and output side line transistors constitute the current mirror circuit CM1. . Equal current I _B flowing current I _A flowing to the input side line of the current mirror circuit CM1 on the output side line, also, the shape of the photodiodes 14, 14 'are also the same.

Since shaded dark current I _C in the photodiode 14 'is flowing, current I _D dark current IC from the current I _A is subtracted for optical power detection, the output side line of the current mirror circuit CM1 Power It flows in a P-type MOS transistor connected in series on the side. These P-type MOS transistors constitute the input side line of the current mirror circuit CM2, and are multiplied by a P-type MOS transistor connected in series to the output side line so that a current _IE flows therethrough. by the current mirror circuit CM3 to input lines comprising the output side line of a plurality of N-type MOS transistor, current flows I _F on the output side line of the current mirror circuit CM3.

A plurality of N-type MOS transistors are also connected in series to the output side line of the current mirror circuit CM3. The above current mirror circuits CM1 to CM3 constitute a second differential amplifier DIF2. That is, the current I _F is dark current is multiplied is subtracted optical power detection current.

The power supply side of the output side line of the current mirror circuit CM3 is interposed the P-type MOS transistor QC, a predetermined potential V _BB is applied to the gate of the bias circuit BIAS. A plurality of P-type MOS transistors QA and QB through which a reference current Iref1 flows are connected in series between the drain of the P-type MOS transistor QC and the power supply potential. A bias is applied to the gate of the upstream P-type MOS transistor QA. given a potential _{V BB} from circuits BIAS, the gate of the downstream side of the P-type MOS transistors QB, given the output potential VO of the CMOS connection type.

  The CMOS connection type output potential VO is a potential at the connection point of the P-type MOS transistor QP and the N-type MOS transistor QN connected in series between the power supply potential and the ground potential. The gates of these transistors QP and QN are connected to the drain of the transistor QB, and this connection point becomes the above-described determination output terminal JO.

The determination output terminal JO is input to the gate of the N-type MOS transistor Q1, and when the potential of the determination output terminal JO is high, the P-type MOS transistor Q2 to the N-type MOS transistor on the power supply potential side of the N-type MOS transistor Q1. A current is supplied to Q1. The potential of the judgment output terminal JO, because when the optical power detected current _{I F} exceeds the reference current Iref1 to the high level, the transistors QA, QB, QC, QP, the QN constitute a comparator COMP1. When the potential of the determination output terminal JO becomes high level, electric charge is supplied from the P-type MOS transistor Q2 to the capacitor C1, and the potential of the gain adjustment terminal VG gradually increases.

  Further, when the potential of the determination output terminal JO becomes low level, the charge accumulated in the capacitor C1 flows to the ground potential via the N-type MOS transistor Q3. Note that the gate potential of the N-type MOS transistor Q3 is the potential VN in the bias circuit BIAS.

  FIG. 18 is a circuit diagram of an actual gain adjustment amplifier.

  In this circuit diagram, the dummy photodiode 12 'is omitted. A reverse bias voltage is applied to the photodiode 12 that receives the optical signal, and the anode side potential is a node between the P-type MOS transistor Q10 and the N-type MOS transistor Q20. This potential is applied to the input terminal IN of the operational amplifier OP composed of a P-type MOS transistor and an N-type MOS transistor, and is multiplied in proportion to the combined resistance of the resistors R1 and R2. When the voltage at the gain adjustment terminal VG that is the gate of the N-type MOS transistor GCT for gain adjustment decreases, the resistance value Rx of the combined resistance increases and the gain increases.

  A capacitor C10 and an N-type MOS transistor SWT are connected between the input terminal IN and the drain of the first-stage NMOS transistor Q21, and the potential of the gain adjustment terminal VG is given to the gate of the N-type MOS transistor SWT. It has been. When the optical power is high and the gain of the amplifier is small, that is, when the level of the gain adjustment terminal VG is high, the N-type MOS transistor SWT is connected and a high-frequency component is applied to the drain of the N-type MOS transistor Q21 of the amplifier. A specified potential SW is applied to a terminal connected to the gate of the P-type MOS transistor of the operational amplifier OP.

  Although a MOS field effect transistor is used as the above-mentioned transistor, it can be a bipolar transistor.

  The present invention can be used for a photodetector applicable to communication that requires a high speed and a wide dynamic range.

It is a perspective view of a photodetector. It is II-II arrow sectional drawing of a photodetector. It is sectional drawing of the photon detection unit incorporating the photon detector. It is a block diagram of a photon detection unit. It is a timing chart of an output signal and an internal signal of a PLL circuit. It is a circuit diagram of a low-pass filter. It is a circuit diagram for demonstrating the function of a low-pass filter. It is a circuit diagram for demonstrating the function of a low-pass filter. It is a circuit diagram of a photodetector. It is a graph which shows the time dependence of a photocurrent. It is a graph which shows the time dependence of the voltage of a gain adjustment terminal. It is a graph which shows the time dependence of the output voltage of a gain adjustment amplifier. It is a top view of a photodiode. It is a top view of a photodiode. It is explanatory drawing which shows the example of arrangement | positioning of the internal circuit of a photodetector. FIG. 4 is a circuit diagram of a gain adjustment amplifier AMP and a comparator output circuit. It is a circuit diagram of an actual optical power detection circuit. It is a circuit diagram of an actual gain adjustment amplifier.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Photodetector 12, 14 ... Photodiode, 14a ... Detection part, 20 ... Monolithic circuit board, 34 ... Lead frame, 36 ... Mold part, 36a ... Lens part, 38 ... wire, 40 ... lead pin, 100 ... plastic optical fiber, 102 ... ferrule, 104 ... fiber connector, 106 ... receptacle, 107 ... PHY chip, AMP ... Gain adjustment amplifier, BIAS ... Bias circuit, C1 ... Capacitor, C10 ... Capacitor, CB ... Circuit board, CC1 ... Capacitor, CC2 ... Capacitor, CM1 ... Current Mirror circuit, CM1 ... current mirror circuit, CM2 ... current mirror circuit, CM3 ... current mirror circuit, COMP1 ..Comparator, D ... Differential amplifier circuit, DIF1 ... Differential amplifier, DIF2 ... Differential amplifier, GCT ... Gain adjustment transistor, IS ... Current mirror circuit, JO -Judgment output terminal, L ... Level adjustment circuit, OP ... Operational amplifier, OPD ... Optical power detector, PJ ... Peak detector, PM ... Power management terminal, PMJ ... Power management Judgment circuit, Q1 ... transistor, Q2 ... transistor, Q3 ... transistor, Q21 ... transistor, QA, QB, QC, QP, QN ... transistor, R1, R2 ... resistor, S ... NAND circuit, SC ... Low pass filter, SD ... Signal detection terminal, SDJ ... Signal detection judgment circuit, SM ... Semiconductor substrate, SWT ... Transitions .

Claims (3)

In the photodetector
A first photodiode for light reception;
A light-shielded second photodiode;
A first differential amplifier to which outputs of the first and second photodiodes are input;
A gain adjustment amplifier interposed between the first and second photodiodes and the first differential amplifier;
An optical power detector that detects optical power at the comparator output;
A low-pass filter interposed between the output terminal of the optical power detector and the gain adjustment terminal of the gain adjustment amplifier;
A photodetector comprising: The optical power detector is
A third photodiode for light reception;
A light-shielded fourth photodiode;
A second differential amplifier to which the outputs of the third and fourth photodiodes are input;
The comparator to which the output of the second differential amplifier is input;
The photodetector according to claim 1, further comprising: The gain adjusting amplifier is
A plurality of resistors interposed in parallel between the input and output terminals of the operational amplifier;
A transistor connected in series with the resistor;
With
The control terminal of the transistor is the gain adjustment terminal.
The photodetector according to claim 1 or 2.

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