JP5045370B2 - Semiconductor circuit device - Google Patents

Description

  The present invention relates to a semiconductor device including a conversion circuit that converts a current signal into a voltage signal.

  An amplifier circuit that converts a current signal into a voltage signal is used, for example, in an opto-electric interface. A compound device or a bipolar device has been used as a device constituting the amplifier circuit. This is because compound devices or bipolar devices are advantageous over CMOS devices in terms of low noise and high speed. However, the subsequent improvement in the high-speed performance of the CMOS device has made it possible to configure an amplifier circuit also with the CMOS device.

  An advantage of configuring an amplifier circuit with a CMOS device is that a CMOS device that constitutes an opto-electric interface can be mounted on a single chip semiconductor chip together with a CMOS device that constitutes a circuit other than the opto-electric interface. As a result, the total area of the semiconductor chip on which the opto-electric interface and related circuits are mounted can be reduced. Further, since the process for manufacturing the semiconductor chip can be integrated into one, the manufacturing cost is greatly reduced. Furthermore, the power consumption of the semiconductor chip is reduced.

  An amplifier circuit that converts a current signal into a voltage signal is required to avoid saturation of the amplitude of the output signal of the amplifier circuit when an input signal with a large current is input. That is, in a high-sensitivity amplifier circuit that can correctly receive an input signal with a minute current, when an input signal with a large current is received, the amplitude of the output signal is saturated, and the amplifier circuit malfunctions. . On the other hand, when an amplifier circuit is designed so that an input signal with a large current can be received, the noise of the element cannot be reduced, and the amplifier circuit cannot receive an input signal with a minute current.

  For example, when an input signal with a large current is input so as to bypass the amplifier circuit for a part of the signal current from a photodiode that is used in an opto-electric interface and converts an optical signal into an electrical signal A proposal has been made to avoid saturation of the amplitude of the output signal of the amplifier circuit (for example, Patent Document 1).

However, even in the amplifier circuit proposed in Patent Document 1, the noise of the element itself cannot be reduced, and the amplifier circuit cannot receive an input signal with a minute current. That is, the upper limit of the magnitude of the signal current accompanying the input signal that can be received can be increased, but it is difficult to lower the lower limit. Then, in the above amplifier circuit, it is impossible to output a reliable output signal within a range of a signal current accompanied by a desired input signal.
JP 11-340745 A

  It is an object of the present invention to provide an amplifier circuit that can output a reliable output signal in a wide range of signal amplitude of an input signal.

  In order to solve the above problems, a semiconductor circuit device provided by the present invention includes a first current-voltage conversion circuit that has a first current path and detects an input signal by a current flowing into the first current path. A second current-voltage conversion circuit that has a second current path and detects the input signal by a current flowing into the second current path; and when the current value of the input signal is smaller than the first current value, The input signal is detected by a first current-voltage conversion circuit, and when the current value of the input signal is larger than the first current value, the input signal is detected by the second current-voltage conversion circuit. And a control circuit for controlling operations of the first current-voltage conversion circuit and the second current-voltage conversion circuit.

  The lower limit of the current range of the input signal that the semiconductor circuit device can output a reliable output signal is the lower limit of the current range of the input signal that the first current-voltage conversion circuit can output the reliable output signal. Lower limit. On the other hand, the upper limit is the upper limit of the current range of the input signal that allows the second current / voltage circuit to output a reliable output signal. As a result, the semiconductor circuit device has a current range of input signals that can output a wide and reliable output signal.

Hereinafter, the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, the fifth embodiment, the sixth embodiment, and the seventh embodiment of the present invention will be described. In addition, this invention is not limited to said Example.

  The first embodiment relates to a TIA circuit composed of a CMOS circuit and configured by combining first and second TIA (trance impedance amplifier) circuits corresponding to input sensitivity and having different current ranges of input signals. Then, the first and second TIA circuits are selected according to the current of the input signal. However, the present invention is not limited to an amplifier circuit formed of MOS transistors, but can be applied to a compound device or a bipolar device.

  The TIA circuit is also a conversion circuit that converts current into voltage.

  FIG. 1 shows a TIA circuit 100 according to the first embodiment. The TIA circuit 100 according to the first embodiment includes a bias circuit 10, a bias circuit 20, a bias circuit 30, a bias circuit 40, a switching circuit 50, a capacitor 56, a TIA circuit 60, a TIA circuit 70, an output terminal 90, a high potential power supply 91, and A low potential power source 92 (for example, a ground power source) is used. The TIA circuit 100 amplifies the input signal from the light receiving element unit 80 and outputs the signal to the output terminal 90.

  The bias circuits 10 and 20 are circuits for supplying a bias voltage to gate terminals of N-type MOS transistors 63 and 73 described later. The bias circuits 10 and 20 will be described in detail later with reference to FIGS. 2A and 2B.

  The bias circuits 30 and 40 are circuits for supplying a bias voltage to gate terminals of N-type MOS transistors 64 and 74 described later. The bias circuits 30 and 40 will be described in detail later with reference to FIGS. 2C and 2D.

  The switching circuit 50 includes a differential amplifier 51 and an inverting amplifier 52. One input terminal of the differential amplifier 51 is connected to an intermediate node to which the photodiode 81 and the resistor 82 are connected. The other input terminal of the differential amplifier 51 is connected to an intermediate node to which the resistor 82, the capacitor 84, and the inductance 83 are connected. The differential amplifier 51 outputs a logic “L” signal 53 when the voltage difference across the resistor 82 is greater than a predetermined value. The differential amplifier 51 outputs a logic “H” signal 53 when the voltage difference across the resistor 82 is smaller than a predetermined value. The inverting amplifier 52 receives the signal 54 at the input terminal and outputs a signal 53 in which the logic is inverted. Therefore, the switching circuit 50 outputs a logic “H” signal 53 to the gate terminal of the P-type transistor 61 when outputting a logic “L” signal 54 to the gate terminal of the P-type transistor 71. The switching circuit 50 outputs a logic “L” signal 53 to the gate terminal of the P-type transistor 61 when the logic “H” signal 54 is output to the gate terminal of the P-type transistor 71. Then, when the P-type transistor 71 is turned on, the P-type transistor 61 is turned off. Further, when the P-type transistor 71 is turned off, the P-type transistor 61 is turned on.

  The TIA circuit 60 includes a P-type MOS transistor 61, a resistor 62, an N-type MOS transistor 63, and an N-type MOS transistor 64. The source of the P-type MOS transistor 61 is connected to the high potential power supply 91, and the drain is connected to one end of the resistor 62. The other end of the resistor 62 is connected to the terminal 90 and the drain of the N-type MOS transistor 63. The source of the N-type MOS transistor 63 is connected to the drain of the N-type MOS transistor 64 and the intermediate node 55. The source of the N-type MOS transistor 64 is connected to the low potential power source 92. Therefore, when a current accompanying an input signal from the light receiving element section 80 is injected into the intermediate node where the N-type MOS transistor 63 and the N-type MOS transistor 64 are connected via the intermediate node 55, the current flowing through the resistor 62 Therefore, the voltage appearing at the intermediate node where the resistor 62 and the N-type MOS transistor 63 are connected rises and falls. Since the current flowing through the N-type MOS transistor 64 is controlled to be constant by the bias circuit 30, the sum of the current flowing through the resistor 62 and the current from the light receiving element unit 80 is controlled to be constant. Because. As described above, the current flowing through the N-type MOS transistor 64 is constant because the bias circuit 30 is connected to the gate of the N-type MOS transistor 64 so that the current driving capability of the N-type MOS transistor 64 is constant. This is because the voltage to be applied is controlled as described later.

  The intermediate node connecting the resistor 62 and the N-type MOS transistor 63 is connected to the terminal 90. That is, an intermediate node where a resistor 72 of the TIA circuit 70 described later and an N-type MOS transistor 73 are connected and the above intermediate node are wired-ORed to the terminal 90.

  The TIA circuit 70 includes a P-type MOS transistor 71, a resistor 72, an N-type MOS transistor 73, and an N-type MOS transistor 74. The source of the P-type MOS transistor 71 is connected to the high potential power supply 91, and the drain is connected to one end of the resistor 72. The other end of the resistor 72 is connected to the terminal 90 and the drain of the N-type MOS transistor 73. The source of the N-type MOS transistor 73 is connected to the drain of the N-type MOS transistor 74 and the intermediate node 55. The source of the N-type MOS transistor 74 is connected to the low potential power source 92. For the same reason as the TIA circuit 60, the voltage appearing at the intermediate node where the resistor 72 and the N-type MOS transistor 73 are connected rises and falls.

  The on-resistance (current driving) of the N-type MOS transistor 74 is set so that the current flowing between the source and drain of the N-type MOS transistor 74 is about twice the current flowing between the source and drain of the N-type MOS transistor 64. Ability) is set. This is because the bias circuit 40 controls the voltage applied to the gate of the N-type MOS transistor 74 as described later. Note that the resistance value or on-resistance of the P-type MOS transistor 61, the resistor 62, the N-type MOS transistor 63 in the TIA circuit 60, and the P-type MOS transistor 71, the resistor 72, and the N-type MOS transistor 73 in the TIA circuit 70. Is set to maintain the above relationship.

  Here, for example, it is desirable that the current flowing between the source and the drain of the N-type MOS transistor 64 is 1.6 mA, and the current flowing between the source and the drain of the N-type MOS transistor 74 is about 3.2 mA.

  The intermediate node 55 is further connected to one end of the capacitor 56 and one end of the inductance 83. The other end of the capacitor 56 is connected to a low potential power source 92.

  The light receiving element unit 80 includes a photodiode 81, a resistor 82, a capacitor 84, and an inductance 83.

  One end of the photodiode 81 is connected to the high potential power supply 91, and the other end is connected to one end of the resistor 82. The other end of the resistor 82 is connected to one end of the inductance 83 and one end of the capacitor 84. The other end of the capacitor 84 is connected to the low potential power source 92.

  The other end of the inductance 83 is connected to one end of the intermediate node 55 and the capacitor 56. The other end of the capacitor 56 is connected to a low potential power source 92. The inductance 83 equivalently represents the inductance of the wiring or lead frame connecting the light receiving element portion 80 and the TIA circuits 60 and 70. The capacitor 56 equivalently represents the capacitance of the wiring or lead frame connecting the light receiving element unit 80 and the TIA circuits 60 and 70.

  In the light receiving element portion 80, when light strikes the photodiode 81, current flows from the high potential power supply 91 to the intermediate node 55 through the resistor 82 and the inductance 83.

  As a result, the switching circuit 50 selects the TIA circuit 60 when the current is smaller than the predetermined value, and selects the TIA circuit 70 when the current is larger than the predetermined value. The selected TIA circuit 60 or TIA circuit 70 outputs a voltage corresponding to the current value to the terminal 90.

  FIG. 2 shows examples of the bias circuits 10, 20, 30 and 40. 2A and 2B show the bias circuit 10 or 20. The bias circuit 10 or 20 is a circuit that generates a constant bias voltage. The circuit for generating a constant bias voltage shown in FIG. 2A is the high potential power supply 91 itself connected to the gate of the N-type transistor. The circuit for generating a constant bias voltage shown in FIG. 2B includes a resistor 11 and a resistor 12 connected in series between a high potential power supply 91 and a low potential power supply 92. This is a circuit that outputs a voltage from an intermediate node sandwiched between the resistor 11 and the resistor 12 to the gate of the N-type transistor. The N-type transistors other than the bias circuit 10 or 20 shown in FIGS. 2A and 2B are the N-type transistor 63 of the TIA circuit 60 or the N-type transistor 73 of the TIA circuit 70.

  The bias circuit 30 or 40 is shown by FIGS. 2C and 2D. The bias circuit 30 or 40 is a circuit that generates a bias voltage such that an N-type transistor that receives a bias voltage applied by the bias circuit 30 or 40 at its gate flows a constant current.

  2C includes a high potential power source 91, a low potential power source 92, a resistor 31, a resistor 32, a differential amplifier 33, a resistor 34, N-type MOS transistors 35, 36, 46a, 46b, a P-type MOS transistor 37, 38 and an N-type MOS transistor 39. The resistor 31 and the resistor 32 are connected in series, with one end connected to the high potential power source 91 and the other end connected to the low potential power source 92. The source of the N-type MOS transistor 35 is connected to the low potential power source 92, and the drain of the N-type MOS transistor 35 is connected to one end of the resistor 34. The other end of the resistor 34 is connected to the high potential power supply 91. The gate of the N-type MOS transistor 35 is connected to the gate of the N-type MOS transistor 36 and the differential amplifier 33. One input terminal of the differential amplifier 33 is connected to an intermediate node sandwiched between the resistors 31 and 32. The other input terminal of the differential amplifier 33 is connected to an intermediate node connecting one end of the resistor 34 and the drain of the N-type MOS transistor 35.

  The source of the N-type MOS transistor 36 is connected to the low potential power source 92, and the drain of the N-type MOS transistor 36 is connected to the drain and gate of the P-type MOS transistor 37 and the gate of the P-type MOS transistor 38. The source of the P-type MOS transistor 37 is connected to the high potential power supply 91. The source of the P-type MOS transistor 38 is connected to the high potential power supply 91. The drain of the P-type MOS transistor 38 is connected to the drain of the N-type MOS transistor 39, and is connected to the drain of the N-type MOS transistor 46a. The gate of the N-type MOS transistor 46a is connected to the signal B. The source of the N-type MOS transistor 46a is connected to an intermediate node connected to the gate electrode of the N-type MOS transistor 39 and the drain electrode of the N-type MOS transistor 46b. The source electrode of the N-type MOS transistor 46 b is connected to the low potential power source 92. The gate electrode of the N-type MOS transistor 46b is connected to the signal / B. The bias circuit shown in FIG. 2C outputs a bias voltage from the intermediate node to the gate of the N-type MOS transistor to be controlled.

  Signal B and signal / B are complementary signals. When the bias circuit of FIG. 2C is adopted for the bias circuit 30 and the bias circuit 40, the signal 54 of FIG. 1 is adopted as the signal B of the bias circuit 30, and the signal 53 of FIG. On the other hand, the signal 53 of FIG. 1 is adopted as the signal B of the bias circuit 40, and the signal 54 of FIG. 1 is adopted as the signal / B of the bias circuit 40.

  That is, when the P-type MOS transistor 61 in FIG. 1 is turned off, the N-type MOS transistor 64 is also turned off. Similarly, when the P-type MOS transistor 71 of FIG. 1 is turned off, the N-type MOS transistor 74 is also turned off.

  When a bias voltage of an intermediate node sandwiched between the resistor 31 and the resistor 32 is applied to the N-type MOS transistor 36, the N-type MOS transistor 36 operates as a constant current circuit that flows a constant current. Then, a similar constant current flows through the N-type MOS transistor 39 by the current mirror circuit composed of the P-type MOS transistor 37 and the P-type MOS transistor 38. Then, a similar constant current flows through the N-type MOS transistor to be controlled by the current mirror circuit including the N-type MOS transistor 39 and the N-type MOS transistor to be controlled.

  The bias circuit shown in FIG. 2D includes a high potential power supply 91, a low potential power supply 92, a resistor 41, and N-type MOS transistors 42 and 43. The high potential power supply 91 and one end of the resistor 41 are connected. The drain of the N-type MOS transistor 42 is connected to the other end of the resistor 41. The gate of the N-type MOS transistor 42 is connected to the bias circuit 44. The bias circuit 44 is a circuit similar to the bias circuits 10 and 20.

  The source of the N-type MOS transistor 42 is connected to the drain of the N-type MOS transistor 43, and is connected to the drain of the N-type MOS transistor 45a. The gate of N-type MOS transistor 45a is connected to signal B. The source of the N-type MOS transistor 45a is connected to an intermediate node connected to the gate of the N-type MOS transistor 43 and the drain of the N-type MOS transistor 45b. The drain of the N-type MOS transistor 43 is connected to the low potential power source 92. The gate electrode of N-type MOS transistor 45b is connected to signal / B. The source of the N-type MOS transistor 45 b is connected to the low potential power source 92. The bias circuit shown in FIG. 2D outputs a bias voltage from the above intermediate node to the gate of the N-type MOS transistor to be controlled. A current similar to the constant current flowing through the resistor 41 and the N-type MOS transistors 42 and 43 connected in series is the current mirror circuit composed of the N-type MOS transistor 43 and the N-type MOS transistor to be controlled. Due to the action, it flows between the source and drain of the N-type MOS transistor to be controlled.

  Signal B and signal / B are complementary signals. When the bias circuit of FIG. 2D is employed in the bias circuit 30 and the bias circuit 40, the signal 54 of FIG. 1 is employed as the signal B of the bias circuit 30, and the signal 53 of FIG. On the other hand, the signal 53 of FIG. 1 is adopted as the signal B of the bias circuit 40, and the signal 54 of FIG. 1 is adopted as the signal / B of the bias circuit 40.

  That is, the P-type MOS transistor 61 and the N-type MOS transistor 64 of FIG. 1 are turned on / off simultaneously. Similarly, the P-type MOS transistor 71 and the N-type MOS transistor 74 of FIG. 1 are turned on / off simultaneously.

  Further, the N-type MOS transistor to be controlled shown in FIGS. 2C and 2D is the N-type transistor 64 of the TIA circuit 60 or the N-type MOS transistor 74 of the TIA circuit 70.

  FIG. 3 shows a table representing the characteristics of the TIA circuit 60 and the TIA circuit 70.

  The current column indicates that the current flowing through the N-type MOS transistor 64 constituting the TIA circuit 60 is smaller than the current flowing through the N-type MOS transistor 74 constituting the TIA circuit 70. The resistance column indicates that the value of the resistor 62 constituting the TIA circuit 60 is larger than the value of the resistor 72 constituting the TIA circuit 70.

  As the resistance value increases, the noise level of each TIA circuit decreases. Therefore, the noise column indicates that the noise level in the TIA circuit 60 is smaller than the noise level in the TIA circuit 70.

  Here, in general, the relationship between the input signal power P required to achieve a bit error rate of 1E-12 or less and the input equivalent noise current spectral density In is expressed by the following equation.

P = K × Sq (In ² · f)
K represents a constant, and Sq (X) represents a root function. F indicates a noise band. The input equivalent noise current spectrum density In is obtained by dividing the TIA output noise power spectral density by the square of the TIA transimpedance and taking the square root thereof.

  From the above equation, when the input conversion noise current spectral density In is small, that is, when the magnitude of noise is small at each frequency, the input signal power to the TIA circuit may be small. Then, a TIA circuit with low noise has a high input sensitivity. Therefore, the input sensitivity column indicates that the input sensitivity of the TIA circuit 60 is larger than the input sensitivity of the TIA circuit 70.

  On the other hand, generally, when an input signal with an input current exceeding the current flowing through the TIA circuits 60 and 70 is input to the TIA circuits 60 and 70, the TIA circuits 60 and 70 cannot react. Therefore, the input current column indicates that the input current that can be handled by the TIA circuit 60 is smaller than the input current that can be handled by the TIA circuit 70.

  FIG. 4 shows a graph regarding the input sensitivity of the TIA circuit 60 and the TIA circuit 70. The vertical axis of the above graph represents input sensitivity (dbm). Further, the horizontal axis shows another TIA circuit.

  Here, the input sensitivity X of the interface composed of the photodiode and the TIA circuit is given by the following equation.

X = ₁₀ log ₁₀ (Pin / 1 mW)
Here, Pin represents the power of the optical signal input to the photodiode. For example, when an optical signal having a power of 1 μW is input to a photodiode and an output signal that achieves a bit error rate of 1E-12 or less is output from the TIA circuit, the interface of the photodiode and the TIA circuit The input sensitivity is −20 dBm.

  In the above case, the current of the input signal received by the TIA circuit is 1 μA when the conversion efficiency between the power and current of the photodiode is 1 A / W.

  According to the graph of FIG. 4, the input sensitivity range of the interface including the photodiode and the TIA circuit 60 is a range from −6 dbm to −17 dbm. That is, the upper limit of the current of the input signal that can be received by the TIA circuit 60 is a current with a current value corresponding to −6 dbm. Here, the current with the above current value is a signal current generated from the photodiode corresponding to the power of the input optical signal due to the conversion efficiency of the photodiode. The lower limit current value of the input signal necessary for the TIA circuit 60 to achieve a bit error rate of 1E-12 or less indicates that the input sensitivity is a current value corresponding to −17 dbm.

Further, the input sensitivity range of the interface composed of the photodiode and the TIA circuit 70 is a range from 0 dbm to −15 dbm. That is, the upper limit of the current of the input signal received by the TIA circuit 70 is a current with a current value corresponding to 0 dbm. On the other hand, the adjustment of the current of the input signal necessary for the TIA circuit 70 to achieve a bit error rate of 1E-12 or less is a current with a current value corresponding to −15 dbm.

  In the graph, the range indicated by W (the range of the input signal current) indicates a range where both the TIA circuit 60 and the TIA circuit 70 can react.

  From the above, the switching circuit 50 selects the TIA circuit 60 when the current value of the current is smaller than the predetermined value, and selects the TIA circuit 70 when the current value of the current is larger than the predetermined value. The selected TIA circuit 60 or TIA circuit 70 outputs a voltage corresponding to the current value of the input signal to the terminal 90. There are overlapping ranges in the current range of the input signal in which the TIA circuit 60 can output a reliable output signal and the current range of the input signal in which the TIA circuit 70 can output a reliable output signal. To do. Therefore, the current range of the input signal in which the TIA circuit 100 including the TIA circuit 60 and the TIA circuit 70 can output a reliable output signal is continuous, and the current range of the input signal included in the TIA circuit 60 is the same. It becomes the lower limit and the upper limit of the current range of the input signal of the TIA circuit 70. Therefore, the TIA circuit 100 has a current range of the input signal that can output a reliable output signal similar to that of the TIA circuit configured by the bipolar device. The TIA circuit 100 can output an output signal corresponding to the current range of the input signal corresponding to the input sensitivity range.

  The MOS transistors, capacitors, and resistors that constitute the TIA circuit 100 can be manufactured by a technique for manufacturing MOS transistors. Therefore, the TIA circuit 100 can be formed on the same semiconductor chip together with circuits constituting other LSIs.

  The second embodiment relates to a TIA circuit that includes a CMOS circuit and is configured by combining first and second TIA circuits having different input sensitivities. Then, the first and second TIA circuits are selected according to the amplitude of the output signal of the TIA circuit of the second embodiment.

  FIG. 5 shows the TIA circuit 200 and the light receiving element portion 210 of the second embodiment. The TIA circuit 200 according to the second embodiment includes a bias circuit 10, a bias circuit 20, a bias circuit 30, a bias circuit 40, a switching circuit 220, a capacitor 56, a TIA circuit 60, a TIA circuit 70, an output terminal 90, a high potential power source 91, and A low potential power source 92 (for example, a ground power source) is used. The bias circuit 10, the bias circuit 20, the bias circuit 30, the bias circuit 40, the TIA circuit 60, the TIA circuit 70, the output terminal 90, the high potential power source 91, and the low potential power source 92 (for example, a ground power source) are as follows. This is the same as that constituting the TIA circuit 100. Therefore, the description thereof is omitted.

  The switching circuit 220 includes an amplitude detection circuit 221, an inverting amplifier 222, and an inverting amplifier 223. The input terminal of the inverter 222 is connected to an intermediate node where the resistor 62 and the N-type MOS transistor 63 are connected, and an intermediate node where the resistor 72 and the N-type MOS transistor 73 are connected. The output terminal of the inverting amplifier 222 is connected to the input terminal of the inverting amplifier 223. The output terminal of the inverter 223 is connected to the amplitude detection circuit 221 and the terminal 90. The amplitude detection circuit 221 detects the amplitude of the signal output from the inverter 223. The switching circuit 220 is a circuit that outputs a logic “L” signal X and a logic “H” signal / X when the amplitude of the output signal from the inverter 223 is smaller than a predetermined value. On the other hand, the switching circuit 220 outputs a logic “H” signal X and a logic “L” signal / X when the amplitude of the output signal from the inverter 223 is greater than a predetermined value. The inverting amplifiers 222 and 223 output the inverted signal of the signal received at the input terminal from the output terminal.

  The amplitude detection circuit 221 can be configured by, for example, a combination of a comparator that compares an output amplitude with a reference voltage, a set-reset latch circuit (SR latch circuit), and an AND circuit (Patent Document: Japanese Patent Application Laid-Open No. 2006-2006). -Known example shown in -50145). Moreover, it can implement | achieve by utilizing a hysteresis comparator (refer patent document: Unexamined-Japanese-Patent No. 2006-50145).

  The signal line through which the signal X propagates is connected to the gate of the P-type MOS transistor 71. The signal line through which the signal / X propagates is connected to the gate of the P-type MOS transistor 61. Accordingly, when the P-type MOS transistor 71 is driven to turn on, the P-type MOS transistor 61 is driven to turn off. When the P-type MOS transistor 71 is driven to be turned off, the P-type MOS transistor 61 is driven to be turned on.

  The light receiving element unit 210 includes a photodiode 81, a capacitor 84, and an inductance 83.

  One end of the photo diode 81 is connected to the high potential power supply 91, and the other end is connected to one end of the inductance 83 and one end of the capacitor 84. The other end of the capacitor 84 is connected to the low potential power source 92.

  The other end of the inductance 83 is connected to one end of the intermediate node 55 and the capacitor 56. The other end of the capacitor 56 is connected to a low potential power source 92. The photodiode 81, the inductance 83, and the capacitor 84 are the same as those constituting the light receiving element unit 80. Therefore, description of these elements is omitted.

  From the above, the switching circuit 220 selects the TIA circuit 60 when the amplitude of the output signal of the TIA circuit 200 is smaller than the predetermined value, and selects the TIA circuit 70 when the current value of the current is larger than the predetermined value. The selected TIA circuit 60 or TIA circuit 70 outputs a voltage corresponding to the current value of the input signal to the terminal 90. There are overlapping ranges in the current range of the input signal in which the TIA circuit 60 can output a reliable output signal and the current range of the input signal in which the TIA circuit 70 can output a reliable output signal. To do. Therefore, the current range of the input signal in which the TIA circuit 200 including the TIA circuit 60 and the TIA circuit 70 can output a reliable output signal is continuous. The lower limit of the current range of the input signal included in the TIA circuit 200 is the lower limit of the current range of the input signal at which the TIA circuit 60 can output a reliable output signal. Further, the upper limit of the current range of the input signal of the TIA circuit 200 is the upper limit of the current range of the input signal of the TIA circuit 70. Therefore, the TIA circuit 200 has a current range of an input signal that can output a reliable output signal similar to that of a TIA circuit configured by a bipolar device. The TIA circuit 200 can output an output signal corresponding to the current range of the input signal corresponding to the input sensitivity range.

  The MOS transistors, capacitors, and resistors that make up the TIA circuit 200 can be manufactured by a technique for manufacturing MOS transistors. Therefore, the TIA circuit 200 can be formed on the same semiconductor chip together with circuits constituting other LSIs.

  The TIA circuit 300 or 400 according to the third embodiment is a TIA circuit in which an inductance is incorporated in the TIA circuit according to the first embodiment or the TIA circuit according to the second embodiment. As a result, the input sensitivity of the TIA circuit 300 or 400 of the third embodiment is greater than that of the TIA circuit 100 of the first embodiment or the TIA circuit 200 of the second embodiment.

  FIG. 6 shows a TIA circuit 300 and a TIA circuit 400 according to the third embodiment.

  A TIA circuit 300 is shown in FIG. 6A. The TIA circuit 300 includes a bias circuit 10, a bias circuit 20, a bias circuit 30, a bias circuit 40, a switching circuit 320, a capacitor 56, an inductance 57, a TIA circuit 310, a TIA circuit 70, an output terminal 90, a high potential power supply 91, and A low potential power source 92 (for example, a ground power source) is used. For the bias circuit 10, the bias circuit 20, the bias circuit 30, the bias circuit 40, the TIA circuit 70, the output terminal 90, the high potential power supply 91, and the low potential power supply 92 (for example, a ground power supply), the TIA circuit 100 is used. It is the same as what constitutes. Therefore, the description thereof is omitted.

  The TIA circuit 310 includes a P-type MOS transistor 61, a resistor 62, an N-type MOS transistor 63, an N-type MOS transistor 64, and an inductance 65. The P-type MOS transistor 61, the resistor 62, the N-type MOS transistor 63, and the N-type MOS transistor 64 are the same as those constituting the TIA circuit 60.

  The source of the P-type MOS transistor 61 is connected to the high potential power supply 91, and the drain is connected to one terminal of the inductance 65. One end of the resistor 62 is connected to the other terminal of the inductance 65. The other end of the resistor 62 is connected to the terminal 90 and the drain of the N-type MOS transistor 63. The source of the N-type MOS transistor 63 is connected to the drain of the N-type MOS transistor 64 and the intermediate node 55. The source of the N-type MOS transistor 64 is connected to the low potential power source 92. An intermediate node connecting the resistor 62 and the N-type MOS transistor 63 is connected to the terminal 90. Further, the intermediate node 55 is connected to an intermediate node to which the N-type MOS transistor 63 and the N-type MOS transistor 64 are connected. When the inductance 65 is inserted between the P-type MOS transistor 65 and the resistor 62, a peaking phenomenon occurs with respect to an AC signal appearing at an intermediate node where the resistor 62 and the N-type MOS transistor 63 are connected. As a result, the input sensitivity of the TIA circuit 310 is improved.

  One end of the inductance 57 is connected to the intermediate node 55, and the other end of the inductance 57 is connected to an intermediate node to which the N-type MOS transistor 73 and the N-type MOS transistor 74 constituting the TIA circuit 70 are connected. The inductance 57 is connected between the intermediate node 55 and the intermediate node to which the N-type MOS transistor 73 and the N-type MOS transistor 74 are connected, so that the N-type MOS transistor 73 and the N-type MOS transistor 73 are connected. The peaking phenomenon occurs with respect to the AC signal appearing at the intermediate node. As a result, the input sensitivity of the TIA circuit 70 is improved.

  FIG. 6B shows the TIA circuit 400. The TIA circuit 400 includes a bias circuit 10, a bias circuit 20, a bias circuit 30, a bias circuit 40, a switching circuit 320, a capacitor 56, an inductance 58, a TIA circuit 310, a TIA circuit 70, an output terminal 90, a high potential power supply 91, and A low potential power source 92 (for example, a ground power source) is used. For the bias circuit 10, the bias circuit 20, the bias circuit 30, the bias circuit 40, the TIA circuit 70, the output terminal 90, the high potential power supply 91, and the low potential power supply 92 (for example, a ground power supply), the TIA circuit 100 is used. It is the same as what constitutes. Therefore, the description thereof is omitted.

  The TIA circuit 310 is the same as that constituting the TIA circuit 300. Therefore, the description of the TIA circuit 310 is omitted.

  One end of the inductance 58 is connected to the terminal 90 and an intermediate node connected to the resistor 62 and the N-type MOS transistor 63. The other end of the inductance 58 is connected to an intermediate node to which the resistor 72 constituting the TIA circuit 70 and the N-type MOS transistor 73 are connected. By connecting the inductance 58 as described above, a peaking phenomenon occurs with respect to an AC signal appearing at an intermediate node where the resistor 72 and the N-type MOS transistor 73 are connected. As a result, the amplitude of the output signal from the TIA circuit 70 increases. As a result, the input sensitivity of the TIA circuit 70 increases.

  From the above, the input sensitivity of the TIA circuit 310 is increased by the inductance 65. Further, the input sensitivity of the TIA circuit 70 is increased by the inductance 57 or the inductance 58. The TIA circuit 310 and the TIA circuit 70 are switched according to the current value of the current of the input signal from the light receiving element unit 80 or according to the amplitude of the output signal appearing at the terminal 90. Then, the TIA circuit 300 or the TIA circuit 400 can react in a wide range of the input current accompanying the input signal.

  The MOS transistors, capacitors, and resistors constituting the TIA circuit 300 and the TIA circuit 400 can be manufactured by a technique for manufacturing MOS transistors. Therefore, the TIA circuit 300 or 400 can be formed on the same semiconductor chip together with circuits constituting other LSIs.

  The TIA circuit 60 and the TIA circuit 70 constituting the TIA circuit 100 of the first embodiment or the TIA circuit 200 of the second embodiment receive a switching signal from the switching circuit and turn on / off the current path of the TIA circuit 60 or 70. It has a P-type MOS transistor to perform.

  This may cause the P-type MOS transistor to pick up noise and reduce the input sensitivity of the TIA circuit 60 or 70.

Here, the TIA circuit 500 of the fourth embodiment is configured by combining a low-noise TIA circuit and a high-noise TIA circuit in the same manner as the TIA circuit 100 of the first embodiment or the TIA circuit 200 of the second embodiment. is there. However, the TIA circuit 500 employs a circuit that switches the output signal of the combined TIA circuit by the switching circuit 220. As a result, since the P-type MOS transistor is not included in the current path of the TIA circuit used in combination, the input sensitivity of each TIA circuit is increased.

  FIG. 7 shows a TIA circuit 500 and a light receiving element unit 210 according to the fourth embodiment. The TIA circuit 500 includes a low noise TIA circuit 530, a high noise TIA circuit 540, an amplifier 510, an amplifier 520, a switching circuit 220, a capacitor 56, and a terminal 90.

  The low noise TIA circuit 530 includes a resistor 62, an N-type MOS transistor 63, a bias circuit 10, an N-type MOS transistor 64, and the bias circuit 30.

  The high noise TIA circuit 540 includes a resistor 72, an N-type MOS transistor 73, a bias circuit 20, an N-type MOS transistor 74, and the bias circuit 40.

  Among the above components, the same components as those described in the first embodiment or the second embodiment are denoted by the same reference numerals, and the description thereof is omitted.

Amplification unit, a small amplifier 511 fans out, and a high fan-out amplifier 512, N-type MOS transistor 513. The input terminal of the amplifier 511 receives the output signal from the TIA circuit 530 and outputs the amplified signal. The input terminal of the amplifier 512 receives the output signal from the amplifier 511 and is connected to the input terminal of the switching circuit 220. The drain of the N-type MOS transistor 513 is connected to a power supply terminal that receives the low potential (ground potential) of the amplifier 512. The source of the N-type MOS transistor 513 is connected to the low potential power source 92. The gate of the N-type MOS transistor 523 is connected to a signal line that propagates the X signal from the switching circuit.

Amplification unit is less amplifier 521 fanout, and a high fan-out amplifier 522, N-type MOS transistor 523. The input terminal of the amplifier 521 receives the output signal from the TIA circuit 540 and outputs the amplified signal. The input terminal of the amplifier 522 receives the output signal from the amplifier 521 and is connected to the input terminal of the switching circuit 220. The drain of the N-type MOS transistor 523 is connected to a power supply terminal that receives the low potential (ground potential) of the amplifier 522. The source of the N-type MOS transistor 523 is connected to the low potential power source 92. The gate of the N-type MOS transistor 523 is connected to a signal line that propagates the / X signal from the switching circuit. Here, the logic of the / X signal is obtained by inverting the logic of the X signal. Therefore, when the N-type MOS transistor 513 is turned on, the N-type MOS transistor is turned off. When the N-type MOS transistor 513 is turned off, the N-type MOS transistor is turned on.

  The light receiving element unit 210 outputs a signal with a current corresponding to the optical signal received by the photodiode 81 to the intermediate node 55 and the capacitor 56.

  The intermediate node 55 is connected to the input terminal of the low noise TIA circuit 530 and the input terminal of the high noise circuit 540. The output terminal of the low noise TIA circuit 530 is connected to the switching circuit 220 via the amplifier 510. The output terminal of the high noise TIA circuit 540 is connected to the switching circuit 220 via the amplifier 520.

  From the above, the switching circuit 220 selects the low noise TIA circuit 530 when the amplitude of the output signal of the TIA circuit 500 is smaller than the predetermined value, and selects the TIA circuit 540 when the current value of the current is larger than the predetermined value. To do. The selected TIA circuit 530 or TIA circuit 540 outputs a voltage corresponding to the current value of the input signal to the terminal 90. In addition, there are overlapping ranges in the current range of the input signal in which the TIA circuit 530 can output a reliable output signal and the current range of the input signal in which the TIA circuit 540 can output a reliable output signal. To do. Therefore, the current range of the input signal in which the TIA circuit 500 including the TIA circuit 530 and the TIA circuit 540 can output a reliable output signal is continuous. The lower limit of the current range of the input signal included in the TIA circuit 500 is the lower limit of the current range of the input signal at which the TIA circuit 530 can output a reliable output signal. The upper limit of the current range of the input signal included in the TIA circuit 500 is the upper limit of the current range of the input signal of the TIA circuit 540. Therefore, the TIA circuit 500 has a current range of the input signal that can output a reliable output signal similar to that of the TIA circuit configured by the bipolar device. The TIA circuit 500 can output an output signal corresponding to the current range of the input signal corresponding to the input sensitivity range.

  The MOS transistors, capacitors, and resistors that make up the TIA circuit 500 can be manufactured by a technique for manufacturing MOS transistors. Accordingly, the TIA circuit 500 can be formed on the same semiconductor chip together with circuits constituting other LSIs.

  Further, the TIA circuit 500 employs a circuit that switches the output signal of the combined TIA circuit by the switching circuit 220. As a result, since the P-type MOS transistor is not included in the current path of the TIA circuit used in combination, the range of input sensitivity of the respective TIA circuits 530 and 540 is expanded. Then, in the TIA circuit 500, the current range of the input signal that can output a reliable output signal can be expanded.

  The TIA circuit 100 according to the first embodiment or the TIA circuit 200 according to the second embodiment includes a TIA circuit 60 and a TIA circuit 70 having independent current paths. Then, the number of parts constituting the TIA circuit 100 or the TIA circuit 200 circuit is large. Therefore, the TIA circuit 500 according to the fourth embodiment has a common part in the current paths of the TIA circuit 60 and the TIA circuit 70 to reduce the number of components constituting the TIA circuit 60 and the TIA circuit 70.

FIG. 8 shows a TIA circuit 600 and a light receiving element unit 210 according to the fifth embodiment. The TIA circuit 600 includes a bias circuit 10, bias circuits 30 and 40, a signal X and a signal / X output from the switching circuit 220 shown in FIG. 7, a capacitor 56, resistors 611 and 613, a P-type MOS transistor 612, and an N-type MOS. Transistors 614, 615, and 616, switches 617, 618, and 619, a terminal 90, a high-potential power supply 91, and a low-potential power supply 92 are included. The light receiving element portion 210, the switching circuit 220, the bias circuits 10, 30, 40, and the capacitor 56 are the same as those given the same reference numerals in FIG.

One end of the resistor 611 is connected to the high potential power supply 91, and the other end of the resistor 611 is connected to the drains of the N-type MOS transistors 614 and 615, the other end of the resistor 613, and the switching circuit 220. One end of the resistor 613 is connected to the drain of the P-type MOS transistor 612. The source of the P-type MOS transistor 612 is connected to the high potential power supply 91. The gate of P-type MOS transistor 612 is connected to the output terminal of switching circuit 220 shown in FIG .

  Then, when the signal / X is “L”, the P-type MOS transistor 612 is turned on, and the load resistance value of the TIA 600 is a value in which the resistor 611 and the resistor 613 are connected in parallel. On the other hand, when the signal / X is “H”, the P-type MOS transistor 612 is turned off, and the load resistance value of the TIA 600 becomes the resistance value of the resistor 611.

The sources of the N-type MOS transistors 614 and 615 are connected to the intermediate node 620. The drain of the N-type MOS transistor 616 is connected to the intermediate node 620, and the source of the N-type MOS transistor 616 is connected to the low potential power source 92. The gate of the N-type MOS transistor 614 is connected to one end of the bias circuit 10 and the switch 619. The other end of the switch 619 is connected to the gate of the N-type MOS transistor 615. The switch 619 connects and disconnects both ends of the switch 619 according to the logic of the signal / X from the switching circuit 220 shown in FIG .

The gate of the N-type MOS transistor 616 is connected to one end of the switch 617 and one end of the switch 618. The other end of the switch 617 is connected to the bias circuit 30. The other end of the switch 618 is connected to the bias circuit 40. The switch 617 connects and disconnects both ends of the switch 617 according to the logic of the signal X from the switching circuit 220. The switch 618 connects and disconnects both ends of the switch 618 in accordance with the logic of the signal / X from the switching circuit 220 shown in FIG .

  The intermediate node 620 is connected to the capacitor 56 and to the light receiving element unit 210.

The output terminal of the switching circuit 220 shown in FIG .

As described above, the TIA circuit 600 includes the first TIA circuit including the resistor 611, the N-type MOS transistors 614, and 616, the P-type MOS transistor 612, the resistor 613, the N-type MOS transistor 615, and the N-type MOS transistor 615. A second TIA circuit comprising a type MOS transistor 616 is included. The signal X and the signal / X from the switching circuit 220 shown in FIG. 7 are in a complementary relationship in signal logic. That is, if one logic is “H”, the other logic is “L”, and if the other logic is “L”, the other logic is “H”.

Then, the first TIA circuit and the second TIA circuit are switched according to the magnitude of the amplitude. This is because the logic of the signal X and the signal / X from the switching circuit 220 shown in FIG. 7 switches according to the magnitude of the amplitude. That is, the TIA circuit 200 of the second embodiment and the TIA circuit 600 of the fifth embodiment operate in the same manner. Then, the TIA circuit 600 can output a reliable output signal. The input signal current range is such that the first TIA circuit can output a reliable output signal. The input signal current range and the second TIA circuit. Is the sum of the current range of the input signal that can output a reliable output signal. That is, the current range of the input signal in which the TIA circuit 600 can output a reliable output signal is a wide range.

  The MOS transistors, capacitors, and resistors that constitute the first TIA circuit and the second TIA circuit can be manufactured by a technique for manufacturing a MOS transistor. Accordingly, the TIA circuit 600 can be formed on the same semiconductor chip together with circuits constituting other LSIs.

  Further, since the first TIA circuit and the second TIA circuit share a current path, the circuit layout area occupied by the first TIA circuit and the second TIA circuit is the first TIA circuit and the second TIA circuit. Compared to the case where the TIA circuit is independent, the size is reduced. Then, the circuit layout area of the TIA circuit 600 can be reduced as compared with the TIA circuit 200 of the second embodiment.

The sixth embodiment relates to a TIA circuit that is configured by combining first, second, and third TIA circuits that include CMOS circuits and that can output a reliable output signal and that have different current ranges of input signals. Then, the first , second and third TIA circuits are selected according to the current of the input signal.

  FIG. 9 shows a TIA circuit 700 and a light receiving element unit 80 according to the sixth embodiment. The TIA circuit 700 includes a TIA circuit 710, a TIA circuit 60, a TIA circuit 70, a switching circuit 720, a capacitor 56, and a terminal 90.

  The TIA circuit 60, the TIA circuit 70, the light receiving element unit 80, the bias circuit 10, the bias circuit 20, the bias circuit 30, the bias circuit 40, the terminal 90, and the capacitor 56 are denoted by the same reference numerals in FIG. Since it is the same thing, description is abbreviate | omitted.

  The TIA circuit 710 includes a P-type MOS transistor 711, an inductance 715, a resistor 712, an N-type MOS transistor 713, and an N-type MOS transistor 714. The source of the P-type MOS transistor 711 is connected to the high potential power supply 91, and the drain of the P-type MOS transistor 711 is connected to one end of the inductance 715. The gate of the P-type MOS transistor is connected to the output terminal 724 from the switching circuit 720.

  The other end of the inductance 715 is connected to one end of the resistor 712. The other end of the resistor 712 is connected to the drain of the N-type MOS transistor 713 and the terminal 90. The source of the N-type MOS transistor 713 is connected to the drain of the N-type MOS transistor 714 and the intermediate node 55. The gate of the N-type MOS transistor 713 is connected to the bias circuit 716. The source of the N-type MOS transistor 714 is connected to the low potential power source 92. The gate of the N-type MOS transistor 714 is connected to the bias circuit 717.

  The bias circuit 716 is a circuit similar to the bias circuit 10 or the bias circuit 20. The bias circuit 717 is a circuit similar to the bias circuit 30 or the bias circuit 40.

  The current flowing in the current path of the TIA circuit 710 (current path formed by connecting the P-type MOS transistor 711, the inductance 715, the resistor 712, the N-type MOS transistor 713, and the N-type MOS transistor 714 in series) The current is smaller than the current flowing through the current path of the TIA circuit 60, for example, about 0.8 mA. Then, since the resistance value of the resistor 712 can be increased, noise generated in the TIA circuit 710 can be reduced. Therefore, the lower limit of the current range of the input signal that allows the TIA circuit 710 to output a reliable output signal can be made lower than that of the TIA circuit 60. On the other hand, the upper limit of the current range of the input signal at which the TIA circuit 710 can output a reliable output signal is higher than that of the TIA circuit 60. This is because the signal current received by the TIA circuit 710 is reduced because the current flowing through the current path of the TIA circuit 710 is reduced.

  The switching circuit 720 includes a differential amplifier 721, a differential amplifier 722, and a logic circuit 723. The first input terminal and the third input terminal of the differential amplifier 721 are connected to an intermediate node where the diode element 81 and the resistor 82 are connected. The second input terminal of the differential amplifier 721 is connected to an intermediate node where the resistor 82 and the capacitor 84 are connected. The first reference potential 727 is input to the fourth input terminal of the differential amplifier 721. The output terminal of the differential amplifier 721 is connected to the first input terminal of the logic circuit 723.

  The first input terminal and the third input terminal of the differential amplifier 722 are connected to an intermediate node where the diode element 81 and the resistor 82 are connected. A second input terminal of the differential amplifier 722 is connected to an intermediate node where the resistor 82 and the capacitor 84 are connected. The second reference potential 728 is input to the fourth input terminal of the differential amplifier 722. The output terminal of the differential amplifier 722 is connected to the second input terminal of the logic circuit 723.

  The differential amplifier 721 and the differential amplifier 722 have a logic “L” when the voltage between the third input terminal and the fourth input terminal is larger than the voltage between the first input terminal and the second input terminal, and vice versa. In this case, a logic "H" signal is output. The first reference voltage 727 is higher than the second reference voltage 728.

  When the differential amplifier 721 outputs a logic “L” signal and the differential amplifier 722 outputs a logic “L” signal, the logic circuit 723 outputs a logic “H” signal to the output terminal 724. A logic “H” signal is output to the terminal 725, and a logic “L” signal is output to the output terminal 726.

  Further, when the differential amplifier 721 outputs a logic “L” signal and the differential amplifier 722 outputs a logic “H” signal, the logic circuit 723 outputs a logic “H” signal to the output terminal 724. A logic “L” signal is output to the output terminal 725, and a logic “H” signal is output to the output terminal 726.

  Further, when the differential amplifier 721 outputs a logic “H” signal and the differential amplifier 722 outputs a logic “H” signal, the logic circuit 723 outputs a logic “L” signal to the output terminal 724. , A logic “H” signal is output to the output terminal 725, and a logic “H” signal is output to the output terminal 726.

Output terminal 724, output terminal 725, output terminal 726, N-type MOS transistor 71 1 of the gate of each TIA circuit 710, N-type MOS transistor 61 of the gate of the TIA circuit 60, N-type MOS transistor 71 of the TIA circuit 70 Connected to the gate. Then, when the voltage across the resistor 82 is lower than the second reference voltage 727, that is, when a large current flows through the resistor 82, only the TIA circuit 70 operates. Next, when the voltage across the resistor 82 is a voltage between the first reference voltage 727 and the second reference voltage 728, that is, when a moderate current flows through the resistor 82, only the TIA circuit 60 operates. Next, when the voltage across the resistor 82 is higher than the first reference voltage 727, that is, when a small current flows through the resistor 82, only the TIA circuit 710 operates.

  An output terminal connected to the inductance 83 of the light receiving element unit 80 is connected to the intermediate node 55 and the capacitor 56. The intermediate node 55 includes an intermediate node where the N-type MOS transistor 713 and the N-type MOS transistor 714 are connected, an intermediate node where the N-type MOS transistor 63 and the N-type MOS transistor 64 are connected, and the N-type MOS transistor 73 and the N-type MOS transistor. Connect to the intermediate node to which transistor 74 is connected. The terminal 90 is connected to an intermediate node connecting the resistor 712 and the N-type MOS transistor 713, an intermediate node connecting the resistor 62 and the N-type MOS transistor 63, and an intermediate node connecting the resistor 72 and the N-type MOS transistor 73. .

  The input signal current range in which the semiconductor device 700 can output a reliable output signal is the input signal current range in which the TIA circuit 710 can output the reliable output signal, and the TIA circuit 60 has a reliable output. This is the sum of the current range of the input signal in which the signal can be output and the current range of the input signal in which the TIA circuit 70 can output a reliable output signal. That is, the current range of the input signal in which the semiconductor device 700 can output a reliable output signal is a wide range.

  The MOS transistors, capacitors, and resistors that constitute the TIA circuit 710, the TIA circuit 60, the TIA circuit 70, and the switching circuit 720 can be manufactured by a technique for manufacturing MOS transistors. Accordingly, the TIA circuit 700 can be formed on the same semiconductor chip together with circuits constituting other LSIs.

  The TIA circuit 700 according to the sixth embodiment includes a TIA circuit 710, a TIA circuit 60, and a TIA circuit 70 having independent current paths. As a result, the number of parts constituting the TIA circuit 700 is large. Therefore, the TIA circuit 800 according to the eighth embodiment includes components common to the current paths of the TIA circuit 710, the TIA circuit 60, and the TIA circuit 70, and the components constituting the TIA circuit 710, the TIA circuit 60, and the TIA circuit 70. The number is reduced.

  FIG. 10 illustrates a TIA circuit 800 and a light receiving element unit 80 according to the seventh embodiment.

  The TIA circuit 800 includes a switching circuit 720, a capacitor 56, a terminal 90, P-type MOS transistors 811, 812, 813, resistors 814, 815, 816, N-type MOS transistors 817, 818, switches 819, 820, 821, 822, 823. 824, bias circuits 717, 30, 40, a terminal 90, and bias circuits 716, 10, 20.

  The light receiving element unit 80, the switching circuit, the capacitor 56, and the terminal 90 are the same as those described in the TIA circuit 700 of the sixth embodiment.

The high potential power supply 91 and the source of the P-type MOS transistor 811 are connected. The drain of the P-type MOS transistor 811 is connected to one end of the resistor 814. The gate of the P-type MOS transistor 811 is connected to the output terminal 724.

The high potential power supply 91 and the source of the P-type MOS transistor 812 are connected. The drain of the P-type MOS transistor 812 is connected to one end of the resistor 815. The gate of the P-type MOS transistor 812 is connected to the output terminal 725.

The high potential power supply 91 and the source of the P-type MOS transistor 813 are connected. The drain of the P-type MOS transistor 813 is connected to one end of the resistor 816. The gate of the P-type MOS transistor 813 is connected to the output terminal 726.

  The other ends of the resistors 814, 815, and 816 are connected to the terminal 90 and the drain of the N-type MOS transistor 817. The source of the N-type MOS transistor 817 is connected to the intermediate node 55, the capacitor 56, and the drain of the N-type MOS transistor 818. The gate of the N-type MOS transistor 817 is connected to one end of the switches 822, 823, and 824. The other end of the switch 822 is connected to the bias circuit 716, the other end of the switch 823 is connected to the bias circuit 10, and the other end of the switch 824 is connected to the bias circuit 20. The switches 822, 823, and 824 are turned on / off according to the logic of the signals from the output terminals 724, 725, and 726, respectively.

  The source of the N-type MOS transistor 818 is connected to the low potential power source 92. The gate of the N-type MOS transistor 818 is connected to one end of the switches 819, 820, and 821. The other end of the switch 819 is connected to the bias circuit 717, the other end of the switch 820 is connected to the bias circuit 30, and the other end of the switch 821 is connected to the bias circuit 40. The switches 819, 820, and 821 are turned on / off according to the logic of signals from the output terminals 724, 725, and 726, respectively.

  Note that the P-type MOS transistor 811, the resistor 814, the N-type MOS transistor 817, and the N-type MOS transistor 818 are connected in series when the logic of the signal from the output terminal 724 is “L”. The current value of the current flowing in the current path formed by the element is the same as the current value of the current flowing in the TIA circuit 710.

  The P-type MOS transistor 812, the resistor 815, the N-type MOS transistor 817, and the N-type MOS transistor 818 are connected in series when the logic of the signal from the output terminal 725 is “L”. The current value of the current flowing in the current path formed by the above-described element is the same as the current value of the current flowing in the TIA circuit 60.

  The P-type MOS transistor 813, the resistor 816, the N-type MOS transistor 817, and the N-type MOS transistor 818 are connected in series when the logic of the signal from the output terminal 726 is "L". The current value of the current flowing through the current path formed by the element is the same as the current value of the current flowing through the TIA circuit 70.

  The switching circuit 720 receives the voltage at one end of the resistor 82 of the light receiving element unit 80 and the voltage at the other end, and outputs the same logic signal to the output terminals 724, 725, and 726 as the switching circuit 720 of the sixth embodiment. To do. An output terminal connected to the inductance 83 of the light receiving element unit 80 is connected to the intermediate node and the capacitor 56.

  As described above, the TIA circuit 800 can output a reliable output signal, the current range of the input signal can be the TIA circuit 710 can output the reliable output signal, the input signal current range, and the TIA circuit 60 can be reliable. This is the sum of the current range of the input signal in which a certain output signal can be output and the current range of the input signal in which the TIA circuit 70 can output a reliable output signal. That is, the current range of the input signal in which the TIA circuit 800 can output a reliable output signal is a wide range.

Further, the MOS transistor, the capacitor, and the resistor that constitute the TIA circuit 800 can be manufactured by a technique for manufacturing a MOS transistor. Accordingly, the TIA circuit 800 can be formed on the same semiconductor chip together with circuits constituting other LSIs.
The features of the present invention are described below.
(Appendix 1)
A first current-voltage conversion circuit that has a first current path and detects an input signal by a current flowing into the first current path;
A second current-voltage conversion circuit that has a second current path and detects the input signal by a current flowing into the second current path;
When the current value of the input signal is smaller than the first current value, the input signal is detected by the first current-voltage conversion circuit, and when the current value of the input signal is larger than the first current value, A semiconductor circuit device comprising: a control circuit that controls operations of the first current-voltage conversion circuit and the second current-voltage conversion circuit so that the input signal is detected by a two-current-voltage conversion circuit.
(Appendix 2)
A first resistor included in the first current path; and a second resistor included in the second current path. The resistance value of the first resistor is greater than the resistance value of the second resistor. The semiconductor circuit device according to appendix 1.
(Appendix 3)
The semiconductor circuit device according to appendix 1, wherein a first output terminal of the first current-voltage conversion circuit and a second output terminal of the second current-voltage conversion circuit are connected by a connection node.
(Appendix 4)
A first P-type MOS transistor included in the first current path and a second P-type MOS transistor included in the second current path; and the control circuit includes the first P-type MOS transistor and the second P-type MOS transistor. 2. The semiconductor circuit device according to appendix 1, wherein switching between a conductive state and a non-conductive state of the MOS transistor is controlled.
(Appendix 5)
The control circuit detects a voltage across a resistor connected in series with a signal source of the input signal, and when the voltage across the both ends is smaller than a first voltage value, the current value of the input signal is Supplementary note 1 wherein the current value of the input signal is judged to be larger than the first current value when it is judged that the current is smaller than the first current and the voltage across the both ends is larger than the first voltage value. The semiconductor circuit device described.
(Appendix 6)
A first MOS transistor included in the first current path;
A second MOS transistor included in the second current path;
A first bias circuit connected to the gate of the first MOS transistor;
A second bias circuit connected to the gate of the second MOS transistor;
Further comprising
The semiconductor circuit device according to claim 1, wherein a current flowing through the first MOS transistor is smaller than a current flowing through the second MOS transistor.
(Appendix 7)
The control circuit detects an amplitude voltage of an output signal line to which the first output terminal and the second output terminal are connected, and when the amplitude voltage is smaller than a second voltage value, the current of the input signal The value is determined to be smaller than the first current value, and when the amplitude voltage is larger than the second voltage value, the current value of the input signal is determined to be larger than the first current value. The semiconductor circuit device according to appendix 1.
(Appendix 8)
The semiconductor circuit device according to appendix 1, wherein an inductance is included in the first current path.
(Appendix 9)
The second input line from the branch node to which the first input line of the first current-voltage conversion circuit and the second input line of the second current-voltage conversion circuit are connected to the second current-voltage conversion circuit includes an inductance. 8. The semiconductor circuit device according to appendix 7, wherein: (Fig. 1, Fig. 6A)
(Appendix 10)
9. The semiconductor circuit device according to appendix 8, wherein an inductance is included between the second output terminal and the connection node.
(Appendix 11)
A first amplifier disposed between the first output terminal and a connection node;
A second amplifier disposed between the second output terminal and a connection node, wherein the control circuit controls switching between activation and deactivation of the first amplifier and the second amplifier. The semiconductor circuit device according to Supplementary Note 1, wherein
(Appendix 12)
The first current-voltage conversion circuit includes the third MOS transistor, the third resistor, and the third MOS transistor having a gate connected to a third bias circuit in the first current path, and the second current-voltage conversion 2. The semiconductor circuit device according to claim 1, wherein the circuit includes, in the second current path, the fourth MOS transistor, the fourth resistor, and the third MOS transistor having a gate connected to a fourth bias circuit.
(Appendix 13)
A third current-voltage conversion circuit that has a third current path and detects an input signal by a current flowing into the third current path;
A fourth current-voltage conversion circuit having a fourth current path and detecting the input signal by a current flowing into the fourth current path;
A fifth current-voltage conversion circuit that has a fifth current path and detects the input signal by a current flowing into the fifth current path;
When the current value of the input signal is smaller than the first value, the input signal is detected by the third current-voltage conversion circuit, and the current value of the input signal is larger than the first value and the second value When the value is smaller, the input signal is detected by the fourth current-voltage conversion circuit, and when the current value of the input signal is larger than the second value, the input signal is detected by the fifth current-voltage conversion circuit. A semiconductor circuit device comprising: a control circuit that controls operations of the third current-voltage conversion circuit, the fourth current-voltage conversion circuit, and the fifth current-voltage conversion circuit.
(Appendix 14)
14. The semiconductor circuit device according to appendix 13, wherein an inductance is included in the third current path.
(Appendix 15)
The control circuit detects a voltage across a resistor connected in series with a signal source of the input signal, and when the voltage across the resistor is a voltage smaller than a third value, the current value of the input signal is When it is determined that the voltage at both ends is larger than the third value and smaller than the fourth value, the current value of the input signal is larger than the first value, Supplementary note 13 wherein the current value of the input signal is judged to be greater than the second value when it is determined that the voltage is smaller than the second value and the voltage across the both ends is greater than the fourth value. The semiconductor circuit device described.
(Appendix 16)
The third current / voltage converter circuit includes the fifth MOS transistor, the fifth resistor, and the fifth MOS transistor having a gate connected to a fifth bias circuit in the third current path, and the fourth current / voltage converter. The circuit includes the sixth MOS transistor, the sixth resistor, and the sixth MOS transistor having a gate connected to the sixth bias circuit in the fourth current path, and the fifth current-voltage conversion circuit includes the fifth current-voltage conversion circuit, 14. The semiconductor circuit device according to appendix 13, wherein the current path includes the seventh MOS transistor, the seventh resistor, and the seventh MOS transistor having a gate connected to the seventh bias circuit. (Fig. 8)

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor circuit device which has the electric current range of the input signal which can maintain a wide input sensitivity can be provided.

FIG. 1 shows a TIA circuit 100 according to the first embodiment. FIG. 2 shows examples of the bias circuits 10, 20, 30 and 40. FIG. 3 shows a table representing the characteristics of the TIA circuit 60 and the TIA circuit 70. FIG. 4 shows a graph regarding the input sensitivity of the TIA circuit 60 and the TIA circuit 70. FIG. 5 shows the TIA circuit 200 and the light receiving element portion 210 of the second embodiment. FIG. 6 shows a TIA circuit 300 and a TIA circuit 400 according to the third embodiment. FIG. 7 shows a TIA circuit 500 and a light receiving element unit 210 according to the fourth embodiment. FIG. 8 shows a TIA circuit 600 and a light receiving element unit 210 according to the fifth embodiment. FIG. 9 shows a TIA circuit 700 and a light receiving element unit 80 according to the sixth embodiment. FIG. 10 illustrates a TIA circuit 800 and a light receiving element unit 80 according to the seventh embodiment.

Explanation of symbols

100, 200, 300, 400, 500, 600, 700, 800 TIA circuit 10, 20, 30, 40, 716, 717 Bias circuit 60, 70, 310, 530, 540, 710 TIA circuit 80, 220, 720 switching circuit 90 Terminals 61, 71, 85, 612, 711, 811, 812, 813 P-type MOS transistors 11, 12, 31, 32, 34, 62, 72, 82, 611, 613, 712, 814, 815, 816 Resistor 33 , 51, 721, 722 Differential amplifier 53, 54 Signal 57, 58, 65, 83, 715 Inductance 55, 620 Intermediate node 84, 56 Capacity 91 High potential power source 92 Low potential power source 52, 222, 223 Inverting amplifier 510, 511 512, 520, 521, 522 Amplifier 81 Photodiode 22 Amplitude detection circuits 617, 618, 619, 819, 820, 821, 822, 823, 824 switches 63, 73, 64, 74, 35, 36, 39, 42, 43, 513, 523, 614, 615, 616, 713 , 714, 817, 818 N-type MOS transistor

Claims (10)

In accordance with an input signal that is input to the source of the first MOS transistor having the first current path, including the first current path, and having the gate connected to the first bias circuit via the wiring having inductance. A first current-voltage conversion circuit that detects the input signal by flowing current;
The input signal is input to the source of a second MOS transistor having a second current path, included in the second current path, and having a gate connected to a second bias circuit via the wiring having the inductance. A second current-voltage conversion circuit for detecting the input signal by a current flowing therewith;
When the current value of the input signal is smaller than the first current value, the input signal is detected by the first current-voltage conversion circuit, and when the current value of the input signal is larger than the first current value, A semiconductor circuit device comprising: a control circuit that controls operations of the first current-voltage conversion circuit and the second current-voltage conversion circuit so that the input signal is detected by a two-current-voltage conversion circuit.   A first resistor included in the first current path and a second resistor included in the second current path are further included, and a resistance value of the first resistor is larger than a resistance value of the second resistor. The semiconductor circuit device according to claim 1.   A first P-type MOS transistor included in the first current path and a second P-type MOS transistor included in the second current path; and the control circuit includes the first P-type MOS transistor and the second P-type MOS transistor. 2. The semiconductor circuit device according to claim 1, wherein switching between a conductive state and a non-conductive state of the MOS transistor is controlled.   The control circuit detects a voltage across a resistor connected in series with a signal source of the input signal, and when the voltage across the both ends is smaller than a first voltage value, the current value of the input signal is It is determined that the current value is smaller than the first current value, and when the voltage across the both ends is larger than the first voltage value, it is determined that the current value of the input signal is larger than the first current value. Item 14. A semiconductor circuit device according to Item 1. Before SL current flowing through the first 1MOS transistor, the small Kunar so on than the 2MOS current flowing through the transistor, the first bias voltage and the second bias output from the first bias circuit to the gate of the first 1MOS transistor 2. The semiconductor circuit device according to claim 1, wherein a second bias voltage output from the circuit to the gate of the second MOS transistor is set .   The control circuit detects an amplitude voltage of an output signal line to which a first output terminal connected to the first current path and a second output terminal connected to the second current path are connected, and the amplitude voltage is a second value. When the voltage is smaller than the voltage value, it is determined that the current value of the input signal is smaller than the first current value. When the amplitude voltage is larger than the second voltage value, the current value of the input signal is 2. The semiconductor circuit device according to claim 1, wherein the semiconductor circuit device is determined to be larger than the first current value.   The semiconductor circuit device according to claim 1, wherein an inductance is included in the first current path.   The first current-voltage conversion circuit includes a third MOS transistor having a gate connected to a first resistor and a third bias circuit in series with the first MOS transistor and the first P-type MOS transistor in the first current path. The second current-voltage conversion circuit includes a gate connected to the second resistor and the fourth bias circuit in series with the second MOS transistor and the second P-type MOS transistor in the second current path. 2. The semiconductor circuit device according to claim 1, further comprising a fourth MOS transistor. Due to the current flowing along with the input signal, which is input via the inductance to the drain of the third MOS transistor which has the third current path, is included in the third current path, and is connected to the gate of the third bias circuit. A third current-voltage conversion circuit for detecting an input signal;
A current that flows along with an input signal that is input via an inductance to the drain of a fourth MOS transistor that has a fourth current path, is included in the fourth current path, and has a gate connected to a fourth bias circuit. A fourth current-voltage conversion circuit for detecting the input signal,
Due to the current flowing along with the input signal, which is input via the inductance to the drain of the third MOS transistor which has the fifth current path, is included in the fifth current path, and is connected to the gate of the third bias circuit. A fifth current-voltage conversion circuit for detecting the input signal;
When the current value of the input signal is smaller than the first value, the input signal is detected by the third current-voltage conversion circuit, and the current value of the input signal is larger than the first value and the second value When the value is smaller, the input signal is detected by the fourth current-voltage conversion circuit, and when the current value of the input signal is larger than the second value, the input signal is detected by the fifth current-voltage conversion circuit. A semiconductor circuit device comprising: a control circuit that controls operations of the third current-voltage conversion circuit, the fourth current-voltage conversion circuit, and the fifth current-voltage conversion circuit.   The control circuit detects a voltage across a resistor connected in series with a signal source of the input signal, and when the voltage across the resistor is a voltage smaller than a third value, the current value of the input signal is When it is determined that the voltage at both ends is larger than the third value and smaller than the fourth value, the current value of the input signal is larger than the first value, The current value of the input signal is determined to be greater than the second value when the voltage across the both ends is determined to be smaller than a second value and the voltage across the both ends is greater than a fourth value. 9. The semiconductor circuit device according to 9.