JP2006032748A - Substrate with built-in component and manufacturing method thereof - Google Patents

Substrate with built-in component and manufacturing method thereof Download PDF

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JP2006032748A
JP2006032748A JP2004210988A JP2004210988A JP2006032748A JP 2006032748 A JP2006032748 A JP 2006032748A JP 2004210988 A JP2004210988 A JP 2004210988A JP 2004210988 A JP2004210988 A JP 2004210988A JP 2006032748 A JP2006032748 A JP 2006032748A
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wiring board
conductive
recess
insulating layer
component
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JP4451238B2 (en
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Satoshi Shibazaki
聡 柴崎
Kenji Sasaoka
賢司 笹岡
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Dai Nippon Printing Co Ltd
DT Circuit Technology Co Ltd
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Dai Nippon Printing Co Ltd
DT Circuit Technology Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide the manufacturing method of a wiring board with built-in component which can reduce cost, and to provide a wiring board with built-in components of high reliability. <P>SOLUTION: At first, a recess 2a is formed in the upper surface of an insulating layer 2, and conductive layers 5, 6, 9 are formed, at least in both the upper and lower surfaces of the insulating layer 2 and the inner surface of the recess 2a. The conductive layers 5, 6 of both the upper and lower surfaces of the insulating layer 2 are subjected to patterning, and a core wiring board is manufactured. A component 12 is positioned inside the recess 2a, and thereafter, the terminal of the component 12 and the conductive layer 9 formed in the inner surface of the recess 2a are connected by a solder 13. Lamination is formed, by laminating insulating layers 3, 4 each in both the upper and lower surfaces of the core wiring board, whereto the component 12 is connected by the solder 13 so as to fill the periphery of the component. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、電気/電子部品を内蔵した部品内蔵基板を製造する部品内蔵基板の製造方法及び電気/電子部品を内蔵した部品内蔵基板に関する。   The present invention relates to a method for manufacturing a component-embedded substrate for manufacturing a component-embedded substrate with a built-in electric / electronic component, and a component-embedded substrate with a built-in electric / electronic component.

近年、エレクトロニクス技術が進展し電子機器や通信機器が高機能化され、かつ小型化も進んでいる。このような状況で配線板への例えば半導体の実装では、実装密度を向上するためパッケージ実装によらないベアチップ実装法が実用化されてきている。また、コンデンサや抵抗などの受動部品では、チップ実装型のものが、0.6mm×0.3mm(0603)のサイズまで小型化している。   In recent years, electronic technology has advanced, electronic devices and communication devices have become highly functional, and miniaturization has also progressed. In such a situation, for example, semiconductor mounting on a wiring board, a bare chip mounting method not using package mounting has been put into practical use in order to improve mounting density. In addition, passive components such as capacitors and resistors are downsized to a size of 0.6 mm × 0.3 mm (0603).

配線板自体としては、配線層間の電気的接続(層間接続)が、スルーホールの内表面に形成された導電層によるものから、COレーザやUV−YAGレーザにより各層ごとにホールを形成しその内側にめっきを形成するものや導電性ペーストを充填するものなど(いわゆるブラインドビア)に移行している。また、配線パターン形成には、その微細化のため、エッチングによる方法(サブトラクティブ工法)に代えてめっきにより配線をメタライズ形成する方法(アディティブ工法)も使用されつつある。これにより、L/S(ライン/スペース)=20μm/20μm程度まで微細形成可能となっている。 As the wiring board itself, the electrical connection between the wiring layers (interlayer connection) is based on the conductive layer formed on the inner surface of the through hole, and a hole is formed for each layer by a CO 2 laser or a UV-YAG laser. There is a shift to those that form plating on the inside and those that are filled with conductive paste (so-called blind vias). For wiring pattern formation, a method (additive method) of forming a metallized wiring by plating instead of a method by etching (subtractive method) is being used for miniaturization. Thereby, it is possible to form finely up to about L / S (line / space) = about 20 μm / 20 μm.

このような状況でさらに部品実装密度を向上し機器の小型化に資するには、例えば、配線板内に部品を内蔵する部品内蔵配線板を用いることができる。部品内蔵配線板には、例えば、特開2004−134424号公報に開示されたものがある。
特開2004−134424号公報
In such a situation, in order to further improve the component mounting density and contribute to downsizing of the device, for example, a component built-in wiring board in which components are built in the wiring board can be used. An example of the component built-in wiring board is disclosed in Japanese Patent Application Laid-Open No. 2004-134424.
JP 2004-134424 A

上記公報においては、部品の端子と導電層との間に半田ペーストを塗布するとともにリフロー炉内で半田ペーストをリフローさせて、部品の端子と導電層とを電気的・機械的に接続させている。ここで、上記公報においては、コア配線板には貫通孔が形成されているため、貫通孔内に部品を位置させるための支持部材が必要となる。この支持部材は、コア配線板や部品とともにリフロー炉内に収容されるために、高耐熱性の材料で形成する必要がある。   In the above publication, a solder paste is applied between a component terminal and a conductive layer, and the solder paste is reflowed in a reflow furnace to electrically and mechanically connect the component terminal and the conductive layer. . Here, in the above publication, since a through hole is formed in the core wiring board, a support member for positioning a component in the through hole is required. Since this support member is housed in the reflow furnace together with the core wiring board and components, it is necessary to form the support member from a high heat resistant material.

本発明は、上記した事情を考慮してなされたもので、コストの低減を図ることができる部品内蔵配線板の製造方法及び信頼性の高い部品内蔵配線板を提供することを目的とする。   The present invention has been made in consideration of the above-described circumstances, and an object thereof is to provide a method for manufacturing a component built-in wiring board and a highly reliable component built-in wiring board capable of reducing cost.

本発明の部品内蔵配線板の製造方法は、第1の絶縁層の上面に凹部を形成し、少なくとも前記第1の絶縁層の上下両面及び前記凹部の内表面に導電層を形成し、前記絶縁層の上下両面の導電層の部分をパターニングして、コア配線板を製造する工程と、前記凹部内に電気/電子部品を位置させる工程と、前記位置させられた電気/電子部品の端子と前記凹部の内表面に形成された導電層の部分を導電部材で接続する工程と、前記導電部材により前記電気/電子部品が接続された前記コア配線板の上下両面それぞれに重ねてかつ前記電気/電子部品の周りを充填するように第2の絶縁層を積層形成する工程とを具備することを特徴とする。   In the method for manufacturing a wiring board with a built-in component according to the present invention, a recess is formed on the upper surface of the first insulating layer, and a conductive layer is formed on at least the upper and lower surfaces of the first insulating layer and the inner surface of the recess. Patterning portions of the conductive layers on the upper and lower surfaces of the layer to manufacture a core wiring board; positioning the electrical / electronic component in the recess; and the terminals of the positioned electrical / electronic component; A step of connecting a portion of the conductive layer formed on the inner surface of the recess with a conductive member, and the electric / electronic overlaid on both upper and lower surfaces of the core wiring board to which the electric / electronic component is connected by the conductive member. And a step of laminating and forming a second insulating layer so as to fill the periphery of the component.

本発明の部品内蔵配線板の製造方法によれば、上面に凹部が形成された絶縁層を備えたコア配線板を製造しているので、電気/電子部品を凹部の内側底面で支持することができる。これにより、支持部材が不要となるので、コストの低減を図ることができる。   According to the method of manufacturing a wiring board with a built-in component of the present invention, since the core wiring board having the insulating layer with the recess formed on the upper surface is manufactured, the electrical / electronic component can be supported on the inner bottom surface of the recess. it can. Thereby, since a support member becomes unnecessary, cost reduction can be aimed at.

本発明の部品内蔵配線板は、上面に凹部が形成された第1の絶縁層と、少なくとも前記第1の絶縁層の上下両面及び前記凹部の内表面に形成された導電層と、端子を有し、前記凹部の内表面に形成された導電層の部分に前記端子が対向するように前記凹部内に埋設された電気/電子部品と、前記凹部内に埋設された電気/電子部品の前記端子と前記凹部の内表面に形成された導電層の部分との間隔に設けられて前記端子と前記導電層の部分とを電気的・機械的に接続する接続部材と、前記凹部内に埋設された電気/電子部品の外表面のうち前記接続部材に接続される部分以外を覆いかつ前記電気/電子部品の上下両面に密着するように設けられた上下2つの第2の絶縁層とを具備することを特徴とする。   The component built-in wiring board of the present invention includes a first insulating layer having a recess formed on the upper surface, a conductive layer formed on at least the upper and lower surfaces of the first insulating layer and the inner surface of the recess, and a terminal. And the electrical / electronic component embedded in the recess so that the terminal faces the portion of the conductive layer formed on the inner surface of the recess, and the terminal of the electrical / electronic component embedded in the recess Embedded in the recess, and a connecting member that is electrically and mechanically connected between the terminal and the conductive layer portion provided at a distance between the conductive layer formed on the inner surface of the recess and the conductive layer portion. The upper / lower two second insulating layers are provided so as to cover the outer surface of the electric / electronic component other than the portion connected to the connection member and to be in close contact with the upper and lower surfaces of the electric / electronic component. It is characterized by.

本発明の部品内蔵配線板の製造方法によれば、コストの低減を図ることができる。本発明の部品内蔵配線板によれば、信頼性の高い部品内蔵配線板を提供することができる。   According to the method of manufacturing a component built-in wiring board of the present invention, the cost can be reduced. According to the component built-in wiring board of the present invention, a highly reliable component built-in wiring board can be provided.

(第1の実施の形態)
以下では本発明の第1の実施の形態を図面を参照しながら説明する。図1は、本実施の形態に係る部品内蔵配線板の模式的な垂直断面図である。
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic vertical sectional view of a component built-in wiring board according to the present embodiment.

図1に示されるように、部品内蔵配線板1は、絶縁層2〜4を有し、絶縁層2,3の境界付近、絶縁層2,4の境界付近、絶縁層3の上面、及び絶縁層4の下面に導電層5〜8をそれぞれ有する4層配線板である。導電層5,6間の電気的接続(層間接続)は、縦方向の導電層9によりなされている。また、導電層5,7間及び導電層6,8間の電気的接続は導電性バンプ10,11によりそれぞれなされている。このような導電性バンプ10,11により、配線板主面の利用効率が向上し高密度実装に適する。   As shown in FIG. 1, the component built-in wiring board 1 includes insulating layers 2 to 4, near the boundary between the insulating layers 2 and 3, near the boundary between the insulating layers 2 and 4, the upper surface of the insulating layer 3, and the insulating layer. A four-layer wiring board having conductive layers 5 to 8 on the lower surface of the layer 4. Electrical connection (interlayer connection) between the conductive layers 5 and 6 is made by the conductive layer 9 in the vertical direction. Electrical connection between the conductive layers 5 and 7 and between the conductive layers 6 and 8 is made by the conductive bumps 10 and 11, respectively. Such conductive bumps 10 and 11 improve the utilization efficiency of the main surface of the wiring board and are suitable for high-density mounting.

絶縁層2の上面側には凹部2aが形成されており、また絶縁層2の下面側には凹部2aに連通した孔2bが形成されている。凹部2a内には、上面が導電層5の上面より上方に位置しないように電気/電子部品12(以下、「電気/電子部品」を単に「部品」という。)が内蔵されている。部品12は、その両端子が接続部材としての半田13を介して、板厚み方向に形成された導電層9に向かい合いかつ電気的、機械的に接続されている。導電層9は、図示するように、凹部2aの内表面及び孔2bの内表面に形成されており、導電層5,6と直接的な電気的接続が可能となっている。凹部2aは、部品12及び半田13ならびに上下両面の絶縁層3,4の内側へのはみ出し部により占められている。   A recess 2 a is formed on the upper surface side of the insulating layer 2, and a hole 2 b communicating with the recess 2 a is formed on the lower surface side of the insulating layer 2. An electrical / electronic component 12 (hereinafter, “electrical / electronic component” is simply referred to as “component”) is incorporated in the recess 2 a so that the upper surface is not positioned above the upper surface of the conductive layer 5. Both terminals of the component 12 face the conductive layer 9 formed in the plate thickness direction and are electrically and mechanically connected via solder 13 as a connecting member. As shown in the figure, the conductive layer 9 is formed on the inner surface of the recess 2a and the inner surface of the hole 2b, and can be directly electrically connected to the conductive layers 5 and 6. The concave portion 2a is occupied by the protruding portion to the inside of the component 12, the solder 13, and the upper and lower insulating layers 3 and 4.

具体的な寸法(厚さ)は、絶縁層2の厚さが0.5mm〜1.5mm程度であることが好ましい。絶縁層2の厚さを0.5mm〜1.5mmとしたのは、絶縁層2の厚さが0.5mm未満になると、部品12を支持するために必要な剛性を維持できないからであり、また絶縁層2の厚さが1.5mmを超えると、絶縁層2の厚さが厚くなり過ぎてしまい、絶縁層2内に部品12を内蔵させた意味が無くなるからである。絶縁層2は、単一の層を用いているが、2以上の層を積層したものであってもよい。   The specific dimension (thickness) is preferably such that the thickness of the insulating layer 2 is about 0.5 mm to 1.5 mm. The reason why the thickness of the insulating layer 2 is set to 0.5 mm to 1.5 mm is that when the thickness of the insulating layer 2 is less than 0.5 mm, the rigidity necessary to support the component 12 cannot be maintained. Moreover, if the thickness of the insulating layer 2 exceeds 1.5 mm, the thickness of the insulating layer 2 becomes too thick, and the meaning of incorporating the component 12 in the insulating layer 2 is lost. The insulating layer 2 uses a single layer, but may be a laminate of two or more layers.

なお、各部材材料は、絶縁層2〜4には例えばエポキシ樹脂、ポリイミド樹脂、ビスマレイミドトリアジン樹脂など、導電層5〜9には例えば銅など、導電性バンプ10,11には例えば微細な金属粒(Ag、Cu、Au、半田など)を樹脂中に分散させた導電性樹脂などを用いることができる。また、半田13については、これに代えて導電性樹脂を用いることができる。   In addition, each member material is, for example, epoxy resin, polyimide resin, bismaleimide triazine resin, etc. for the insulating layers 2-4, copper, for example, for the conductive layers 5-9, and fine metal, for example, for the conductive bumps 10, 11. A conductive resin in which grains (Ag, Cu, Au, solder, etc.) are dispersed in a resin can be used. For the solder 13, a conductive resin can be used instead.

部品12としては、例えば、チップ抵抗、チップコンデンサ、チップインダクタ、チップダイオード等の受動部品及び能動部品が挙げられる。また、部品12のサイズとしては、例えば0.6mm×0.3mm(0603)や0.4mm×0.2mm(0402)等が好ましい。   Examples of the component 12 include passive components and active components such as a chip resistor, a chip capacitor, a chip inductor, and a chip diode. The size of the component 12 is preferably, for example, 0.6 mm × 0.3 mm (0603), 0.4 mm × 0.2 mm (0402), or the like.

次に、上記のような構造の部品内蔵配線板1を製造するプロセスの例を図2(a)〜図6(b)を参照して説明する。図2(a)〜図5(c)は、本実施の形態に係る部品内蔵配線板を製造するプロセスを模式的に示した図であり、図6(a)及び図6(b)は、本実施の形態に係る配線板素材を製造するプロセスを模式的に示した図である。これらの図において、同一相当の部分には同一符号を付してある。また、図1に示す部品内蔵配線板と対応する部分にも同一符号を付してある。   Next, an example of a process for manufacturing the component built-in wiring board 1 having the above structure will be described with reference to FIGS. 2 (a) to 6 (b). 2 (a) to 5 (c) are diagrams schematically showing a process for manufacturing the component built-in wiring board according to the present embodiment, and FIGS. 6 (a) and 6 (b) It is the figure which showed typically the process which manufactures the wiring board raw material which concerns on this Embodiment. In these drawings, the same reference numerals are assigned to the same equivalent parts. Moreover, the same code | symbol is attached | subjected also to the part corresponding to the component built-in wiring board shown in FIG.

まず、絶縁層2及び導電層5,6,9から構成されたコア配線板を作成する。このコア配線板は、例えば次のようにして作成することができる。例えば厚さ0.15mm程度の平板状のCu板21を用意し、図2(a)に示されるようにこのCu板21に例えばフォトリソグラフィ技術を利用してエッチングにより凸部21aを形成する。具体的には、例えば、Cu板21の表面を化学研磨してレジスト用のドライフィルムとの密着性を向上したうえで、レジスト用ドライフィルムをCu板21に積層する。そして、フォトマスクを介して例えば超高圧水銀灯を有するアライメント露光機でドライフィルムを露光し、さらに炭酸ナトリウムによってスプレー現像する。この現像パターンのドライフィルムをCu板21上に残すことにより、パターニングされたレジストがCu板21上に形成される。レジストがCu層21上に形成されたら、これをマスクにエッチャントとして塩化第2鉄をベースとする薬液を用い、レジストパターンとして抜けた位置のCu板21をスプレーエッチングする。これにより、Cu板21に凸部21aが形成される。   First, a core wiring board composed of the insulating layer 2 and the conductive layers 5, 6, 9 is prepared. This core wiring board can be produced, for example, as follows. For example, a flat Cu plate 21 having a thickness of about 0.15 mm is prepared, and as shown in FIG. 2A, a convex portion 21a is formed on the Cu plate 21 by etching using, for example, a photolithography technique. Specifically, for example, the surface of the Cu plate 21 is chemically polished to improve the adhesion to the resist dry film, and then the resist dry film is laminated on the Cu plate 21. Then, the dry film is exposed with an alignment exposure machine having, for example, an ultrahigh pressure mercury lamp through a photomask, and further spray-developed with sodium carbonate. By leaving the dry film of this development pattern on the Cu plate 21, a patterned resist is formed on the Cu plate 21. When the resist is formed on the Cu layer 21, using this as a mask, a chemical solution based on ferric chloride is used as an etchant, and the Cu plate 21 at a position removed as a resist pattern is spray-etched. Thereby, the convex portion 21 a is formed on the Cu plate 21.

Cu板21に凸部21aを形成した後、図2(b)に示されるように例えば電解めっき法によりCu板21上に例えば厚さ約0.5μmのNi層22を形成するとともにNi層22上に例えば厚さ約0.5μmのCu層23を形成する。   After forming the convex portions 21a on the Cu plate 21, as shown in FIG. 2B, for example, an Ni layer 22 having a thickness of about 0.5 μm is formed on the Cu plate 21 by, for example, electrolytic plating, and the Ni layer 22 is formed. For example, a Cu layer 23 having a thickness of about 0.5 μm is formed.

Cu板21上にNi層22及びCu層23を形成した後、図2(c)に示されるようにCu層22上に厚さ約0.5mm〜1.5mmの絶縁層2を積層するとともに絶縁層2上にCu箔24を積層し、加熱しながら加圧する。これにより、これらのものが一体化されるとともに、凸部21a及び凸部21a上のNi層22及びCu層23が絶縁層2に入り込み、絶縁層2に凹部2aが形成される。なお、この製造プロセスにおいては、松下電工社製の「R−1551」(商品名)を用いて形成された絶縁層2を使用した。   After forming the Ni layer 22 and the Cu layer 23 on the Cu plate 21, the insulating layer 2 having a thickness of about 0.5 mm to 1.5 mm is laminated on the Cu layer 22 as shown in FIG. A Cu foil 24 is laminated on the insulating layer 2 and pressed while heating. Thereby, these components are integrated, and the convex portion 21 a and the Ni layer 22 and the Cu layer 23 on the convex portion 21 a enter the insulating layer 2, and the concave portion 2 a is formed in the insulating layer 2. In this manufacturing process, the insulating layer 2 formed using “R-1551” (trade name) manufactured by Matsushita Electric Works, Ltd. was used.

絶縁層2に凹部2aを形成した後、例えばエッチングにより凸部21a上に位置するCu箔24の部分を除去して、図2(d)に示されるようにCu箔24に開口24aを形成する。このエッチングはCu板21のエッチングと同様の手法により行うことができる。   After the concave portion 2a is formed in the insulating layer 2, the portion of the Cu foil 24 located on the convex portion 21a is removed by etching, for example, and an opening 24a is formed in the Cu foil 24 as shown in FIG. . This etching can be performed by the same method as the etching of the Cu plate 21.

Cu箔24に開口24aを形成した後、例えばCOレーザやYAGレーザのようなレーザを開口24aから露出している絶縁層2の部分に照射し、図3(a)に示されるように絶縁層2及びCu層23に孔2bを形成する。これにより、凹部2aに連通した孔2bが形成される。なお、Ni層22がストッパ層として機能するので、Ni層22には孔が形成されない。 After the opening 24a is formed in the Cu foil 24, a portion of the insulating layer 2 exposed from the opening 24a is irradiated with a laser such as a CO 2 laser or a YAG laser, for example, so as to insulate as shown in FIG. Holes 2 b are formed in the layer 2 and the Cu layer 23. Thereby, the hole 2b connected to the recessed part 2a is formed. Since the Ni layer 22 functions as a stopper layer, no hole is formed in the Ni layer 22.

絶縁層2等に孔2bを形成した後、図3(b)に示されるように次に説明するエッチングによりCu箔24がエッチングされないようにCu箔24に保護フィルム25を貼着する。なお、この製造プロセスにおいては、保護フィルム25として日立化成社製の「ヒタレックス」(商品名)を使用した。そして、これらのものを例えばアルカリ系のエッチング液に浸漬させて、図3(c)に示されるようにCu板21を選択的に除去する。   After the holes 2b are formed in the insulating layer 2 and the like, a protective film 25 is attached to the Cu foil 24 so that the Cu foil 24 is not etched by the etching described below as shown in FIG. In this manufacturing process, “Hitalex” (trade name) manufactured by Hitachi Chemical Co., Ltd. was used as the protective film 25. And these things are immersed in an alkaline etching solution, for example, and the Cu plate 21 is selectively removed as shown in FIG.

Cu板21を除去した後、保護フィルム25をCu箔24から引き剥がす。その後、例えばエッチングによりNi層22を選択的に除去する。これにより、図3(d)に示されるように絶縁層2の上面側にCu層23が露出する。   After removing the Cu plate 21, the protective film 25 is peeled off from the Cu foil 24. Thereafter, the Ni layer 22 is selectively removed by etching, for example. As a result, the Cu layer 23 is exposed on the upper surface side of the insulating layer 2 as shown in FIG.

絶縁層2の上面側にCu層23を露出させた後、例えば無電解めっき法により孔2bの内表面にCuめっきを施し、Cu層23及びCu箔24を電気的に接続させる。その後、電解めっき法によりCu層23等上にCuめっきを施し、厚付けする。これにより、図4(a)に示されるように導電層5,6,9が一体的に形成される。   After the Cu layer 23 is exposed on the upper surface side of the insulating layer 2, Cu plating is performed on the inner surface of the hole 2b by, for example, an electroless plating method, and the Cu layer 23 and the Cu foil 24 are electrically connected. Thereafter, Cu plating is performed on the Cu layer 23 and the like by an electrolytic plating method and thickened. Thereby, the conductive layers 5, 6, and 9 are integrally formed as shown in FIG.

導電層5,6,9が形成された後、例えばエッチングにより導電層5,6にパターニングを施し、図4(b)に示されるように回路を形成する。これにより、コア配線板が作成される。このエッチングはCu板21のエッチングと同様の手法により行うことができる。なお、導電層5,6には、このあと積層される絶縁層3,4との密着性を向上するために黒化還元処理を施してもよい。   After the conductive layers 5, 6, and 9 are formed, the conductive layers 5 and 6 are patterned by etching, for example, to form a circuit as shown in FIG. Thereby, a core wiring board is created. This etching can be performed by the same method as the etching of the Cu plate 21. The conductive layers 5 and 6 may be subjected to blackening reduction treatment in order to improve the adhesion with the insulating layers 3 and 4 to be laminated thereafter.

コア配線板を作成した後、図4(c)に示されるようにマウンタなどの実装機器により凹部2a内に部品12を位置させる。次に、図4(b)に示されるように部品12の両端子付近の所定位置に半田ペースト26(半田ペーストは、例えばSn−3.0Ag−0.5Cuの鉛フリーのもの)を塗布する。このような塗布は、例えばスクリーン印刷またはディスペンサにより行なうことができる。ここでは、0.5mm径のピットを有するスクリーン版によるスクリーン印刷を用いた。   After creating the core wiring board, the component 12 is positioned in the recess 2a by a mounting device such as a mounter as shown in FIG. Next, as shown in FIG. 4B, solder paste 26 (the solder paste is, for example, Sn-3.0Ag-0.5Cu lead-free solder) is applied to a predetermined position near both terminals of the component 12. . Such application can be performed, for example, by screen printing or a dispenser. Here, screen printing using a screen plate having 0.5 mm diameter pits was used.

半田ペースト26を塗布した後、これらのものを支持部材を用いずに、リフロー炉に収容し、半田ペースト26をリフローさせる。これにより、図5(a)に示されるように導電層9と部品12との間に半田ペースト26が入り込む。その後、放置することにより、半田ペースト26が硬化し、半田13となる。なお、半田ペースト26の代わりに導電性ペーストを用いることも可能であり、この場合には、例えばオーブンで乾燥させ硬化させて電気的・機械的接続を確立する。   After the solder paste 26 is applied, these are accommodated in a reflow furnace without using a support member, and the solder paste 26 is reflowed. As a result, the solder paste 26 enters between the conductive layer 9 and the component 12 as shown in FIG. After that, the solder paste 26 is hardened and becomes the solder 13 by leaving it to stand. In addition, it is also possible to use an electrically conductive paste instead of the solder paste 26. In this case, for example, an electrical and mechanical connection is established by drying and curing in an oven.

次に、コア配線板の両面に配線板素材27を積層して、加熱しながら加圧して、図5(b)に示されるようにコア配線板と配線板素材27とを一体化させる。ここで、配線板素材27は、絶縁層3,4とすべきプリプレグ28,29、導電層7,8、及び導電性バンプ10,11から構成されており、例えば以下のようにして、作成することができる。   Next, the wiring board material 27 is laminated on both surfaces of the core wiring board and pressed while heating to integrate the core wiring board and the wiring board material 27 as shown in FIG. Here, the wiring board material 27 is composed of the prepregs 28 and 29 to be the insulating layers 3 and 4, the conductive layers 7 and 8, and the conductive bumps 10 and 11. For example, the wiring board material 27 is formed as follows. be able to.

まず、例えばCu箔のような導電層7(8)(厚さは例えば18μm)を用意し、図6(a)に示されるようにこの導電層7(8)上の必要な位置(特定の配線板のレイアウトに従う位置)にほぼ円錐形の導電性バンプ10(11)を形成する。これには、例えばスクリーン印刷を用いて導電性ペーストを導電層7(8)上に印刷してなすことができる。   First, a conductive layer 7 (8) such as a Cu foil (thickness is 18 μm, for example) is prepared, and a necessary position (a specific position) on the conductive layer 7 (8) is prepared as shown in FIG. A substantially conical conductive bump 10 (11) is formed at a position according to the layout of the wiring board. This can be done, for example, by printing a conductive paste on the conductive layer 7 (8) using screen printing.

この場合のスクリーン版には、例えば0.2mmの貫通孔(ピット)が穿設されたものを用いることができる。これにより、例えば底面径として0.15mm程度以上の導電性バンプ10(11)を形成することができる。導電性ペーストとしては、例えばエポキシ樹脂のようなペースト状樹脂の中に金属粒(Ag、Au、Cu、半田など)を分散させ、加えて揮発性の溶剤を混合させたもの用いることができる。印刷されたあと、例えばオーブンで乾燥し導電性ペーストを硬化させる。   As the screen plate in this case, for example, a screen plate having 0.2 mm through holes (pits) can be used. Thereby, for example, the conductive bump 10 (11) having a bottom diameter of about 0.15 mm or more can be formed. As the conductive paste, for example, metal particles (Ag, Au, Cu, solder, etc.) dispersed in a paste-like resin such as an epoxy resin, and a volatile solvent mixed can be used. After printing, the conductive paste is cured by drying in an oven, for example.

次に、専用機を用い、導電層7(8)に絶縁層3(4)とすべきプリプレグ28(29)(厚さは例えば0.06mm)に対向させて、図6(b)に示されるように導電性バンプ10(11)を半硬化状態のプリプレグ28(29)に貫通させる。これにより、配線板素材27が作成される。プリプレグ28(29)は、例えば、エポキシ樹脂のような硬化性樹脂をガラス繊維のような補強材に含浸させたものである。また、硬化する前には半硬化状態にあり、熱可塑性(熱による流動性)および熱硬化性を有する。   Next, using a dedicated machine, the conductive layer 7 (8) is opposed to the prepreg 28 (29) (thickness is, for example, 0.06 mm) to be the insulating layer 3 (4), and is shown in FIG. 6B. As shown, the conductive bump 10 (11) is passed through the semi-cured prepreg 28 (29). Thereby, the wiring board material 27 is created. The prepreg 28 (29) is obtained by impregnating a reinforcing material such as glass fiber with a curable resin such as an epoxy resin. Moreover, it is in a semi-cured state before curing, and has thermoplasticity (fluidity due to heat) and thermosetting.

コア配線板と配線板素材27の積層・一体化には、例えばレイアップ装置で位置合わせを行いコア配線板と配線板素材27とを重ねて配置し、かつ真空積層熱プレス機を用いこれを所定の温度および圧力プロファイルに設定する。この積層・一体化により導電性バンプ10,11は、頭部がつぶされて塑性変形し、導電層5,6との電気的接続が確立する。また、プリプレグ28(29)が硬化して、絶縁層3,4が形成される。   For the lamination / integration of the core wiring board and the wiring board material 27, for example, alignment is performed with a lay-up device, the core wiring board and the wiring board material 27 are arranged in an overlapping manner, and this is performed using a vacuum lamination heat press. Set to a predetermined temperature and pressure profile. As a result of this lamination and integration, the conductive bumps 10 and 11 are plastically deformed by crushing their heads, and electrical connection with the conductive layers 5 and 6 is established. Further, the prepreg 28 (29) is cured, and the insulating layers 3 and 4 are formed.

ここで、導電層5,6は、プリプレグ28(29)の熱可塑性(熱による流動性)により絶縁層2側へ沈み込んで位置し、導電層5,6は、プリプレグ28(29)の熱可塑性により絶縁層側へ沈み込んで位置するようになる。さらに、プリプレグ28(29)の熱可塑性により、内蔵された部品12を覆いかつ密着するようにその周辺にも絶縁層2が絶縁層3,4と一体的に形成される。これにより部品12周りの穴埋め工程は不要であり工程の簡素化が実現するともに、間隙(ボイド)の発生を防止して信頼性を向上できる。   Here, the conductive layers 5 and 6 are positioned by sinking to the insulating layer 2 side due to the thermoplasticity (fluidity due to heat) of the prepreg 28 (29), and the conductive layers 5 and 6 are the heat of the prepreg 28 (29). Due to plasticity, it sinks into the insulating layer side and comes to a position. Further, due to the thermoplasticity of the prepreg 28 (29), the insulating layer 2 is integrally formed with the insulating layers 3 and 4 on the periphery thereof so as to cover and closely contact the built-in component 12. This eliminates the need for a hole filling process around the part 12 and simplifies the process, and also prevents the generation of voids and improves the reliability.

なお、外側に積層する配線板素材27は図6(b)に示す形態のものに代えて、さらに導電層数が多いものでもよい(例えば、図6(a)に示すもの代わりにプリプレグ28(29)の両面にパターニング後の導電層を貼り付けたものを用いれば、図6(b)の段階では導電層数は2つになる。)。また、外側に積層する配線板素材27は、必ずしも、図6(b)に示すように導電性バンプ10(11)を伴っていなくてもよい。この場合、導電性バンプ10(11)がないので、導電層5(6)と導電層7(8)との層間接続は、導電性バンプ10(11)によって行なうことはできないが、積層後の配線板にスルーホールを設けこのスルーホールによる層間接続構造を形成することはできる。   The wiring board material 27 laminated on the outside may be one having a larger number of conductive layers instead of the one shown in FIG. 6B (for example, a prepreg 28 (in place of the one shown in FIG. 6A). If the conductive layer after patterning is pasted on both sides of (29), the number of conductive layers will be two at the stage of FIG. 6 (b). Further, the wiring board material 27 laminated on the outside does not necessarily need to be accompanied by the conductive bumps 10 (11) as shown in FIG. In this case, since there is no conductive bump 10 (11), the interlayer connection between the conductive layer 5 (6) and the conductive layer 7 (8) cannot be made by the conductive bump 10 (11). By providing a through hole in the wiring board, an interlayer connection structure by this through hole can be formed.

コア配線板と配線板素材27とを積層・一体化した後、例えばエッチングにより導電層7,8にパターニングを施し、図5(c)に示されるように回路を形成する。このパターニングは、導電層5,6のパターニングと同様な手法により行なうことができる。以上により本実施形態に係る部品内蔵配線板1を得ることができる。なお、以上の積層・一体化の後、さらにこの外側に同様の要領により絶縁層と導電層とを積層・一体化(ビルドアップ)してもよい。   After the core wiring board and the wiring board material 27 are laminated and integrated, the conductive layers 7 and 8 are patterned by etching, for example, to form a circuit as shown in FIG. This patterning can be performed by the same method as the patterning of the conductive layers 5 and 6. Thus, the component built-in wiring board 1 according to the present embodiment can be obtained. In addition, after the above lamination / integration, an insulating layer and a conductive layer may be further laminated / integrated (build-up) on the outside in the same manner.

本実施の形態では、絶縁層2の上面に凹部2aを形成しているので、凹部2aの内側底面で部品12を支持することができる。これにより、部品12を支持する支持部材が不要となるので、コストの低減を図ることができる。   In the present embodiment, since the recess 2a is formed on the upper surface of the insulating layer 2, the component 12 can be supported by the inner bottom surface of the recess 2a. This eliminates the need for a support member that supports the component 12, thereby reducing the cost.

本実施の形態では、絶縁層2の下面に凹部2aに連通した孔2bを形成し、かつ導電層9を凹部2aの内表面のみならず孔2bの内表面にも形成しているので、導電層5,6間の電気的接続をすることができる。   In this embodiment, the hole 2b communicating with the recess 2a is formed on the lower surface of the insulating layer 2, and the conductive layer 9 is formed not only on the inner surface of the recess 2a but also on the inner surface of the hole 2b. Electrical connections between layers 5 and 6 can be made.

(第2の実施の形態)
次に、本発明の第2の実施形態に係る部品内蔵配線板について図7を参照して説明する。図7は、本実施の形態に係る部品内蔵配線板の模式的な垂直断面図である。図7において、すでに図1〜図6(c)において説明したものと同一の部分には同一の符合を付してある。以下重複を避けて説明する。
(Second Embodiment)
Next, a component built-in wiring board according to a second embodiment of the present invention will be described with reference to FIG. FIG. 7 is a schematic vertical sectional view of the component built-in wiring board according to the present embodiment. In FIG. 7, the same parts as those already described with reference to FIGS. 1 to 6C are denoted by the same reference numerals. The following explanation will be made avoiding duplication.

図7に示されるように、この実施形態では、絶縁層2に代えて絶縁層31〜33を用い、それらの境界付近には導電層34,35が設けられている。また、導電層5,34間等の層間接続には導電性バンプ36〜38が用いられている。導電層9は、導電層34,35とも直接的な電気的接続が可能となっている。なお、導電性バンプ36〜38は、その製造工程として例えば図6(a)で説明したようなスクリーン印刷を用いて形成することができる。   As shown in FIG. 7, in this embodiment, insulating layers 31 to 33 are used instead of the insulating layer 2, and conductive layers 34 and 35 are provided in the vicinity of the boundary between them. Conductive bumps 36 to 38 are used for interlayer connection between the conductive layers 5 and 34. The conductive layer 9 can be directly electrically connected to the conductive layers 34 and 35. The conductive bumps 36 to 38 can be formed by using screen printing as described in FIG.

この実施形態の利点は、コア配線板の総厚に対して、3つの導電性バンプ36〜38で層間接続を行うことにより、すべての層間接続を導電性バンプ10,11,36〜38によりなすようにしたことである。ここで、コア配線板を3つの導電性バンプ36〜38により層間接続したのは、これより数が少ない場合には高いバンプ形成が必要となり効率的な導電性バンプの形成が難しいからである。このように3つ程度とすれば、総厚に対して必要な形成高さにはさほどの困難さは生じない。この結果、コア配線板は4層の導電層となり、全体として6層の導電層となっている。   The advantage of this embodiment is that all the interlayer connections are made by the conductive bumps 10, 11, 36 to 38 by making the interlayer connection by the three conductive bumps 36 to 38 with respect to the total thickness of the core wiring board. This is what I did. Here, the reason why the core wiring board is connected between the three conductive bumps 36 to 38 is that if the number is smaller than this, it is necessary to form a high bump and it is difficult to efficiently form the conductive bump. If there are about three in this way, there will be no difficulty in the formation height necessary for the total thickness. As a result, the core wiring board has four conductive layers, and has six conductive layers as a whole.

ただし、導電性バンプ36〜38の形成高さをより高くすればより厚いプリプレグを貫通させることが可能であり、この結果、同じ部品を内蔵するとしてもコア配線板の導電層の数を少なくすることができる。逆に、導電性バンプ36〜38の形成高さをより低くすればより薄いプリプレグを用いることになり、この結果コア配線板の導電層の数を多くすることができる。   However, if the formation height of the conductive bumps 36 to 38 is increased, a thicker prepreg can be penetrated. As a result, the number of conductive layers of the core wiring board is reduced even if the same component is incorporated. be able to. On the contrary, if the formation height of the conductive bumps 36 to 38 is lowered, a thinner prepreg is used. As a result, the number of conductive layers of the core wiring board can be increased.

図7に示す部品内蔵配線板1を製造するには、図2(c)に示した絶縁層2に代えて絶縁層31〜33、導電層34,35、及び導電性バンプ36〜38を構成要素とする4層板を用いればよい。その後のプロセスは図2(d)から図5(c)に示したものと本質的に同様である。4層板を得るには、導電性バンプの印刷・形成、形成された導電性バンプにプリプレグを貫通(以上は図6(a)及び図6(b)を参照できる。)、貫通後に対向する側に銅箔(または配線層付きの絶縁層)を積層、というプロセスを繰り返せばよい。   In order to manufacture the component built-in wiring board 1 shown in FIG. 7, instead of the insulating layer 2 shown in FIG. 2C, insulating layers 31 to 33, conductive layers 34 and 35, and conductive bumps 36 to 38 are configured. A four-layer plate as an element may be used. The subsequent processes are essentially the same as those shown in FIGS. 2 (d) to 5 (c). In order to obtain a four-layer plate, conductive bumps are printed and formed, and the formed conductive bumps are penetrated through the prepreg (see FIG. 6A and FIG. 6B for the above). What is necessary is just to repeat the process of laminating | stacking copper foil (or insulating layer with a wiring layer) on the side.

この実施形態では、先の実施形態と同様に製造設備として既存のものをほとんどそのまま使用することができ、配線板の製造コストの抑制につながる。また、部品12をマウント・内蔵するための工程では部品マウントでの不良発生が極めて小さく歩留まりのよい製造が可能であることも同様である。さらに、コア配線板における導電層を4つとすることにより、コア配線板の厚さを部品内蔵空間が確保しやすい寸法とし、導電層34,35等の導電層同士の層間接続をすべて導電性バンプ10,11,36〜38で行うことにより一層の高密度実装を実現することが可能である。   In this embodiment, as in the previous embodiment, the existing manufacturing equipment can be used almost as it is, leading to a reduction in the manufacturing cost of the wiring board. Similarly, in the process for mounting and incorporating the component 12, the occurrence of defects in component mounting is extremely small, and manufacturing with a high yield is possible. Furthermore, by using four conductive layers in the core wiring board, the thickness of the core wiring board is set to a dimension that facilitates securing the component built-in space, and all the interlayer connections between the conductive layers such as the conductive layers 34 and 35 are made of conductive bumps. It is possible to realize further high-density mounting by performing 10, 11, 36 to 38.

なお、本発明は上記実施の形態の記載内容に限定されるものではなく、構造や材質、各部材の配置等は、本発明の要旨を逸脱しない範囲で適宜変更可能である。   The present invention is not limited to the description of the above embodiment, and the structure, material, arrangement of each member, and the like can be appropriately changed without departing from the gist of the present invention.

図1は、第1の実施の形態に係る部品内蔵配線板の模式的な垂直断面図である。FIG. 1 is a schematic vertical sectional view of the component built-in wiring board according to the first embodiment. 図2(a)〜図2(d)は、第1の実施の形態に係る部品内蔵配線板を製造するプロセスを模式的に示した図である。FIG. 2A to FIG. 2D are diagrams schematically showing a process for manufacturing the component built-in wiring board according to the first embodiment. 図3(a)〜図3(d)は、第1の実施の形態に係る部品内蔵配線板を製造するプロセスを模式的に示した図である。FIG. 3A to FIG. 3D are diagrams schematically showing a process for manufacturing the component built-in wiring board according to the first embodiment. 図4(a)〜図4(d)は、第1の実施の形態に係る部品内蔵配線板を製造するプロセスを模式的に示した図である。FIG. 4A to FIG. 4D are diagrams schematically showing a process for manufacturing the component built-in wiring board according to the first embodiment. 図5(a)〜図5(c)は、第1の実施の形態に係る部品内蔵配線板を製造するプロセスを模式的に示した図である。FIG. 5A to FIG. 5C are diagrams schematically showing a process for manufacturing the component built-in wiring board according to the first embodiment. 図6(a)及び図6(b)は、第1の実施の形態に係る配線板素材を製造するプロセスを模式的に示した図である。FIGS. 6A and 6B are diagrams schematically showing a process for manufacturing the wiring board material according to the first embodiment. 図7は、第2の実施の形態に係る部品内蔵配線板の模式的な垂直断面図である。FIG. 7 is a schematic vertical sectional view of the component built-in wiring board according to the second embodiment.

符号の説明Explanation of symbols

1…部品内蔵配線板、2〜4,31〜33…絶縁層、5〜9,34,35…導電層、10,11,36〜38…導電性バンプ、12…部品、13…半田。   DESCRIPTION OF SYMBOLS 1 ... Component built-in wiring board, 2-4, 31-33 ... Insulating layer, 5-9, 34, 35 ... Conductive layer 10, 11, 36-38 ... Conductive bump, 12 ... Component, 13 ... Solder.

Claims (7)

第1の絶縁層の上面に凹部を形成し、少なくとも前記第1の絶縁層の上下両面及び前記凹部の内表面に導電層を形成し、前記絶縁層の上下両面の導電層の部分をパターニングして、コア配線板を製造する工程と、
前記凹部内に電気/電子部品を位置させる工程と、
前記位置させられた電気/電子部品の端子と前記凹部の内表面に形成された導電層の部分を導電部材で接続する工程と、
前記導電部材により前記電気/電子部品が接続された前記コア配線板の上下両面それぞれに重ねてかつ前記電気/電子部品の周りを充填するように第2の絶縁層を積層形成する工程と
を具備することを特徴とする部品内蔵配線板の製造方法。
A recess is formed on the upper surface of the first insulating layer, a conductive layer is formed on at least the upper and lower surfaces of the first insulating layer and the inner surface of the recess, and portions of the conductive layers on the upper and lower surfaces of the insulating layer are patterned. The process of manufacturing the core wiring board,
Positioning an electrical / electronic component within the recess;
Connecting the terminal of the positioned electrical / electronic component and the portion of the conductive layer formed on the inner surface of the recess with a conductive member;
Stacking and forming a second insulating layer so as to overlap each of the upper and lower surfaces of the core wiring board to which the electrical / electronic component is connected by the conductive member and to fill the periphery of the electrical / electronic component. A method for manufacturing a component built-in wiring board.
前記凹部は、前記凹部に対応する凸部を有する金属体と前記第1の絶縁層とを積層し、前記金属体と前記第1の絶縁層とを加熱しながら加圧することにより形成されることを特徴とする請求項1記載の部品内蔵配線板の製造方法。   The concave portion is formed by laminating a metal body having a convex portion corresponding to the concave portion and the first insulating layer, and pressurizing the metal body and the first insulating layer while heating. The method of manufacturing a component built-in wiring board according to claim 1. 前記コア配線板を形成する工程において、前記第1の絶縁層の下面側に前記凹部に連通した貫通孔をさらに形成し、かつ前記導電層は前記貫通孔の内表面にも形成されることを特徴とする請求項1又は2記載の部品内蔵配線板の製造方法。   In the step of forming the core wiring board, a through hole communicating with the recess is further formed on the lower surface side of the first insulating layer, and the conductive layer is also formed on the inner surface of the through hole. 3. A method of manufacturing a component built-in wiring board according to claim 1 or 2. 前記導電部材は、半田又は導電性樹脂であることを特徴とする請求項1乃至3のいずれか1項に記載の部品内蔵配線板の製造方法。   The method for manufacturing a component built-in wiring board according to any one of claims 1 to 3, wherein the conductive member is solder or conductive resin. 前記コア配線板を製造する工程は、導電層を4つ有するコア配線板を製造するものであり、かつ、これらの導電層同士の電気的接続が導電性バンプでなされるように製造されることを特徴とする請求項1乃至4のいずれか1項に記載の部品内蔵配線板の製造方法。   The step of manufacturing the core wiring board is to manufacture a core wiring board having four conductive layers, and to be manufactured so that electrical connection between these conductive layers is made with conductive bumps. The method of manufacturing a component built-in wiring board according to any one of claims 1 to 4. 上面に凹部が形成された第1の絶縁層と、
少なくとも前記第1の絶縁層の上下両面及び前記凹部の内表面に形成された導電層と、
端子を有し、前記凹部の内表面に形成された導電層の部分に前記端子が対向するように前記凹部内に埋設された電気/電子部品と、
前記凹部内に埋設された電気/電子部品の前記端子と前記凹部の内表面に形成された導電層の部分との間隔に設けられて前記端子と前記導電層の部分とを電気的・機械的に接続する接続部材と、
前記凹部内に埋設された電気/電子部品の外表面のうち前記接続部材に接続される部分以外を覆いかつ前記電気/電子部品の上下両面に密着するように設けられた上下2つの第2の絶縁層と
を具備することを特徴とする部品内蔵配線板。
A first insulating layer having a recess formed on the upper surface;
A conductive layer formed on at least the upper and lower surfaces of the first insulating layer and the inner surface of the recess;
An electrical / electronic component embedded in the recess so that the terminal faces a portion of a conductive layer formed on the inner surface of the recess;
The terminal of the electrical / electronic component embedded in the recess and the portion of the conductive layer formed on the inner surface of the recess are electrically and mechanically connected to the terminal and the portion of the conductive layer. A connecting member to be connected to,
Two second upper and lower second electrodes are provided so as to cover the outer surface of the electric / electronic component embedded in the recess except for the portion connected to the connecting member and to be in close contact with the upper and lower surfaces of the electric / electronic component. A wiring board with a built-in component, comprising: an insulating layer.
前記導電層に電気的に接続可能な複数の板方向導電層と、
前記複数の板方向導電層を層間接続する導電性バンプによる層間接続体と
をさらに具備することを特徴とする請求項6記載の部品内蔵配線板。
A plurality of plate direction conductive layers electrically connectable to the conductive layer;
The component built-in wiring board according to claim 6, further comprising: an interlayer connection body formed of conductive bumps for interlayer connection of the plurality of plate direction conductive layers.
JP2004210988A 2004-07-20 2004-07-20 Manufacturing method of component-embedded substrate and component-embedded substrate Expired - Fee Related JP4451238B2 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150107348A (en) * 2014-03-14 2015-09-23 삼성전자주식회사 Method for manufacturing circuit board and semiconductor package
KR20200106062A (en) * 2018-01-30 2020-09-10 비보 모바일 커뮤니케이션 컴퍼니 리미티드 Printed circuit board, printed circuit board manufacturing method and mobile terminal

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150107348A (en) * 2014-03-14 2015-09-23 삼성전자주식회사 Method for manufacturing circuit board and semiconductor package
KR102171021B1 (en) * 2014-03-14 2020-10-28 삼성전자주식회사 Method for manufacturing circuit board and semiconductor package
KR20200106062A (en) * 2018-01-30 2020-09-10 비보 모바일 커뮤니케이션 컴퍼니 리미티드 Printed circuit board, printed circuit board manufacturing method and mobile terminal
JP2021511675A (en) * 2018-01-30 2021-05-06 維沃移動通信有限公司Vivo Mobile Communication Co., Ltd. Printed circuit board, manufacturing method of printed circuit board and mobile terminal
US11490520B2 (en) 2018-01-30 2022-11-01 Vivo Mobile Communication Co., Ltd. Printed circuit board, method of manufacturing the same, and mobile terminal
KR102488402B1 (en) * 2018-01-30 2023-01-12 비보 모바일 커뮤니케이션 컴퍼니 리미티드 Printed circuit board, manufacturing method of printed circuit board and mobile terminal

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