JP2006032682A - Horizontal short channel dmos - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a horizontal type short channel DMOS, low in gate resistance and on resistance while being excellent in high-speed switching characteristics and current driving characteristics. <P>SOLUTION: An n<SP>-</SP>-type epitaxial layer 110 is formed in the vicinity of surface of a p-type semiconductor substrate 106, and a p-type well 114 as well as n<SP>+</SP>-type source region 116 are formed in the vicinity of the surface. An on resistance reducing n-type well 134 is formed in the vicinity of surface of the n<SP>-</SP>-type epitaxial layer 110 while n<SP>+</SP>-type drain region 118 is formed in the vicinity of the surface. An n-type buried layer 108 is formed at a part of a boundary between the p-type semiconductor substrate 106 and the n<SP>-</SP>-epitaxial layer 110 whereat at least the p-type well 114 is superposed when it is seen from the upper surface thereof. Further, the p-type buried layer 109 is formed so as to cover the upper surface of the n-type buried layer 108 so that at least a part of the n-type buried layer 108 is contacted with the n<SP>-</SP>-type epitaxial layer 110. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a lateral short-channel DMOS suitably used as a power MOSFET.

FIG. 9 is a cross-sectional view of a conventional lateral short-channel DMOS. As shown in FIG. 9, the lateral short channel DMOS 90 includes an N ⁻ type epitaxial layer 910 formed in the vicinity of the surface of the P ⁻ type semiconductor substrate 908 and a channel formed in the vicinity of the surface of the N ⁻ type epitaxial layer 910. A P-type well 914 including a region C, an N ⁺ -type source region 916 formed near the surface of the P-type well 914, an N ⁺ -type drain region 918 formed near the surface of the N ⁻ -type epitaxial layer 910, And a polysilicon gate electrode 922 formed through a gate insulating film 920 above the channel forming region C. (For example, see Patent Document 1 and Non-Patent Document 1)

In the lateral short-channel DMOS 90, the N ⁺ type source region 916 is connected to a source terminal (not shown) via a source electrode 926, and the N ⁺ type drain region 918 is connected to a drain terminal (not shown) via a drain electrode 928. The polysilicon gate electrode 922 is connected to a gate terminal (not shown). The P ⁻ type semiconductor substrate 908 is connected to a ground 932 fixed at 0V. However, the lateral short-channel DMOS 90 has a problem that high-speed switching is not easy because the resistance of the polysilicon gate electrode 922 is high.

  FIG. 10 is a sectional view of another conventional lateral short-channel DMOS. As shown in FIG. 10, the lateral short channel DMOS 92 has a structure in which a gate resistance reducing metal layer 930 formed on an interlayer insulating film 924 is connected to a polysilicon gate electrode 922. For this reason, according to the lateral short-channel DMOS 92, the gate resistance reducing metal layer 930 is connected to the polysilicon gate electrode 922. Therefore, the resistance of the gate electrode layer is lowered as a whole, and high-speed switching is possible. Yes.

However, in this lateral short-channel DMOS 92, the contact hole (A) of the interlayer insulating film 924 provided for connecting the polysilicon gate electrode 922 and the gate resistance reducing metal layer 930, and the gate resistance reducing metal layer 930 are provided. Since a separation region (B) for electrically separating the source electrode 926 and the drain electrode 928 from each other is necessary, the gate length of the polysilicon gate electrode 922 is increased, resulting in an increase in on-resistance. There was a problem.
Japanese Patent Application Laid-Open No. 8-213617 Hiroshi Yamazaki, “Applied Technology of Power MOSFET”, Nikkan Kogyo Shimbun (first edition, 8th edition), October 23, 1998, FIG. 2.1 and pages 9-12

  Accordingly, the present invention has been made in view of the above problems, and an object thereof is to provide a lateral short-channel DMOS having a low gate resistance and low on-resistance, and excellent in high-speed switching characteristics and current drive characteristics. To do.

  The present invention has been made to solve the above-described problems. The invention according to claim 1 is directed to a second conductivity type epitaxial layer formed near the surface of a first conductivity type semiconductor substrate, and the epitaxial layer. A first well of a first conductivity type including a channel formation region formed in the vicinity of the surface of the layer; a high concentration source region of a second conductivity type formed in the vicinity of the surface of the first well; and the epitaxial layer A second well of a second conductivity type for reducing on-resistance formed near the surface of the layer so as not to contact the first well, and a second conductivity formed near the surface of the second well. A high-concentration drain region of the mold, a gate electrode formed at least above the channel formation region of the region extending from the source region to the drain region via a gate insulating film, the semiconductor substrate, and the epitaxy Formed at least in a portion overlapping the first well when viewed from above, and includes a second conductivity type impurity at a higher concentration than the epitaxial layer so as not to contact the second well. A first conductivity type formed so as to cover an upper surface of the first buried layer so that at least a part of the first buried layer is in contact with the epitaxial layer. A lateral short-channel DMOS comprising the second buried layer.

  According to a second aspect of the present invention, in the lateral short-channel DMOS according to the first aspect, the first buried layer is formed so as not to overlap the second well when viewed from above. Features.

  According to a third aspect of the present invention, in the lateral short-channel DMOS according to the first or second aspect, the first well and the drain region are not in contact with each other between the first well and the drain region. A diffusion layer of one conductivity type is formed.

  According to a fourth aspect of the present invention, in the lateral short-channel DMOS according to the third aspect, the diffusion layer is formed so as not to contact the second well.

  According to a fifth aspect of the present invention, in the lateral short-channel DMOS according to the third or fourth aspect, in the region from the diffusion layer to the drain region, the gate electrode is connected to the epitaxial layer via a field oxide film. It is characterized by facing the layer.

  According to the present invention, it is possible to provide a lateral short-channel DMOS that has low gate resistance and low on-resistance and is excellent in high-speed switching characteristics and current drive characteristics.

The best mode for carrying out the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of a lateral short-channel DMOS according to a first embodiment of the present invention. In the lateral short channel DMOS 1A according to the present embodiment, an N ⁻ type epitaxial layer 110 is formed on the surface of a P type semiconductor substrate 106 made of P type silicon. A P-type well 114 (first well) including a channel formation region C is formed near the surface of the N ⁻ -type epitaxial layer 110, and an N ⁺ -type source region 116 is formed near the surface of the P-type well 114. Is formed. On the other hand, an N-type well 134 for reducing on-resistance (second well) is formed in the vicinity of the surface of the N ⁻ -type epitaxial layer 110 so as not to contact the P-type well 114. An N ⁺ type drain region 118 is formed in the vicinity of the surface.

At least a portion of the boundary between the P-type semiconductor substrate 106 and the N ⁻ -type epitaxial layer 110 that overlaps with the P-type well 114 when viewed from the upper surface includes an N-type impurity that is higher in concentration than the N ⁻ -type epitaxial layer 110. A buried layer 108 (first buried layer) is formed, and P-type buried layers 107 and 109 (second buried layer) are formed so as to cover the upper and lower sides of the N-type buried layer 108. The N-type buried layer 108 is formed so as not to contact the element isolation region 140. The P-type buried layer 109 does not cover the entire upper surface of the N-type buried layer 108, but is formed so that at least a part of the upper surface of the N-type buried layer 108 is in contact with the N ⁻ -type epitaxial layer 110. The effect of providing the N-type buried layer 108 and the P-type buried layer 107 will be described later.

A polysilicon gate electrode 122 as a gate electrode is formed through a gate insulating film 120 at least above the channel formation region C in the region from the N ⁺ type source region 116 to the N ⁺ type drain region 118. . The polysilicon gate electrode 122 is connected to the gate resistance reducing metal layer 130. The gate resistance reducing metal layer 130 is configured as the same layer as the metal layer constituting the source electrode 126 and the metal layer constituting the drain electrode 128.

An interlayer insulating film 124 is formed between the source electrode 126 and drain electrode 128 and the polysilicon gate electrode 122. A field oxide film 136 is provided on the N ⁺ -type drain region 118, the N-type well 134 for reducing on-resistance, and the N ⁻ -type epitaxial layer 110. An element isolation region 140 is provided on the right side of the N ⁺ type drain region 118. A P-type buried region 141 is provided below the element isolation region 140. This P type buried region 141 is formed simultaneously with the P type buried regions 107 and 109. The P-type semiconductor substrate 106 is connected to a ground 132 fixed at 0V.

According to the lateral short channel DMOS 1A, the N-type well 134 for reducing on-resistance is formed in the vicinity of the surface of the N ⁻ -type epitaxial layer 110 so as not to contact the P-type well 114. since the N ⁺ -type drain region 118 is formed near the surface, mostly low on-resistance lowering N-type well resistance of the current path from the N ⁺ -type drain region 118 at the time on the N ⁺ -type source region 116 Even if the gate length is increased to reduce the gate resistance, the on-resistance can be sufficiently reduced as a whole. Therefore, the lateral short-channel DMOS 1A according to the present embodiment is a lateral short-channel DMOS having low gate resistance and low on-resistance and excellent in high-speed switching characteristics and current drive characteristics.

Further, according to the lateral short-channel DMOS1A according to the present embodiment, N ^- than -type epitaxial layer 110 so it was decided to provide a separate on-resistance lowering N-type well 134 containing a high concentration of N-type impurity, N ^- -type epitaxial Even when the impurity concentration itself of the layer 110 is not increased, the on-state resistance can be reduced, and the breakdown voltage performance of the lateral short-channel DMOS is not deteriorated.

In the lateral short-channel DMOS 1A according to the present embodiment, the depth of the P-type well 114 is, for example, 1.5 μm, the depth of the N ⁺ -type source region 116 is, for example, 0.3 μm, and the N ⁺ -type drain region 118 The depth is also 0.3 μm, for example, and the depth of the on-resistance reducing N-type well 134 is 2 μm, for example. Further, the thickness of the N ⁻ type epitaxial layer 110 is, for example, 10 μm. The impurity concentration of the on-resistance reducing N-type well 134 is, for example, 1 × 10 ¹⁹ atoms / cm ³ , and the impurity concentration of the N ⁻ -type epitaxial layer 110 is, for example, 1 × 10 ¹⁶ atoms / cm ³ .

Next, the effect of providing the N-type buried layer 108 will be described. In the lateral short-channel DMOS 1A according to the present embodiment, since the voltage of the drain electrode 128 rises at the time of OFF, the PN junction between the P-type semiconductor substrate 106 and the N ⁻ -type epitaxial layer 110 becomes a reverse bias, and the depletion layer becomes The N ⁻ type epitaxial layer 110 extends from the junction. At this time, since the potential of the source electrode 126 is also set lower than the potential of the drain electrode 128, the PN junction between the P-type well 114 and the N ⁻ -type epitaxial layer 110 is also reverse-biased. A depletion layer extends to the N ⁻ type epitaxial layer 110. At this time, when these depletion layers are in contact with each other, breakdown is likely to occur even under a milder condition, so that the withstand voltage performance is lowered.

However, according to the lateral short-channel DMOS 1A of this embodiment, at least the portion of the boundary between the P-type semiconductor substrate 106 and the N ⁻ -type epitaxial layer 110 that overlaps at least the P-type well 114 when viewed from above, is N ⁻ -type epitaxial. Since the N-type buried layer 108 containing an N-type impurity having a higher concentration than the layer 110 is formed, the above-described depletion layers are effectively prevented from contacting each other at the time of OFF. For this reason, it becomes possible to suppress a decrease in the pressure resistance performance due to the contact of these depletion layers.

This also makes it possible to shorten the distance between the PN junction between the P-type semiconductor substrate 106 and the N ⁻ -type epitaxial layer 110 and the PN junction between the P-type well 114 and the N ⁻ -type epitaxial layer 110. The thickness of the N ⁻ type epitaxial layer 110 can be reduced. For this reason, the time for growing the N ⁻ -type epitaxial layer 110 and the time for forming the element isolation region 140 formed at the position surrounding the lateral short-channel DMOS 1A can be shortened. Can be shortened and the cost can be reduced.

In the lateral short-channel DMOS 1A according to the present embodiment, in order to more effectively suppress the contact between the depletion layers described above, an N-type buried layer is formed from a PN junction between the P-type semiconductor substrate 106 and the N-type buried layer 108. It is preferable to make the depletion layer extending to the layer 108 side (N ⁻ type epitaxial layer 110 side) a short distance. For this reason, it is necessary to increase the impurity concentration of the N-type buried layer 108 to some extent. On the other hand, from the viewpoint of reducing a decrease in breakdown voltage at the PN junction between the P-type semiconductor substrate 106 and the N-type buried layer 108, it is preferable not to increase the impurity concentration of the N-type buried layer 108 unnecessarily. For this reason, in the lateral short-channel DMOS 1A according to the first embodiment, the impurity concentration of the N-type buried layer 108 is preferably 5 × 10 ¹⁷ pieces / cm ^{3 to} 5 × 10 ¹⁹ pieces / cm ^3. More preferably, it is in the range of 10 ¹⁸ pieces / cm ^{3 to} 5 × 10 ¹⁸ pieces / cm ³ .

In the lateral short-channel DMOS 1A according to the present embodiment, the N-type buried layer 108 is formed so as not to overlap with the on-resistance reducing N-type well 134 when viewed from above. This eliminates the need to consider the contact between the N-type buried layer 108 and the N-type well 134 for reducing on-resistance, so that the thickness of the N ⁻ -type epitaxial layer 110 can be made as thin as possible. In this case, the N-type well 134 for reducing on-resistance has a shallow depth at the periphery thereof and is difficult to contact the N-type buried layer 108. As seen, it may be formed so as not to overlap with the opening of the ion implantation mask used when forming the N-type well 134 for reducing on-resistance, and even in that case, a predetermined effect can be obtained.

Next, a second embodiment of the present invention will be described. FIG. 2 is a cross-sectional view of the lateral short-channel DMOS according to the present embodiment. In the lateral short-channel DMOS 1B shown in FIG. 2, floating is performed between the P-type well 114 and the N ⁺ -type drain region 118 in the vicinity of the surface of the N ⁻ -type epitaxial layer 110 so as not to contact the P-type well 114. A p-type diffusion layer 138 in a state is formed. According to the lateral short-channel DMOS 1B, the electric field strength at the time of reverse bias in the vicinity of the region where the P-type diffusion layer 138 is formed is relaxed, and the breakdown voltage can be further stabilized. The P-type diffusion layer 138 is formed so as not to contact the N-type well 134 for reducing on-resistance. Thereby, the fall of a proof pressure and the increase in leak current can be suppressed as much as possible.

In the region from the P-type diffusion layer 138 to the N ⁺ -type drain region 118 of the lateral short-channel DMOS 1B according to the present embodiment, the polysilicon gate electrode 122 is opposed to the N ⁻ -type epitaxial layer 110 through the field oxide film 136. ing. Therefore, the capacitance between the gate and the source and between the gate and the drain can be reduced, and the high-speed switching characteristics can be further improved. This is because the electric field strength at the time of reverse bias in the vicinity of the region where the P-type diffusion layer 138 is formed is relaxed, so that the thick field oxide film 136 is formed in the region extending from the P-type diffusion layer 138 to the N ⁺ -type drain region 118. This is because the polysilicon gate electrode 122 can be configured to face the N ⁻ type epitaxial layer 110 via the n ^- type electrode.

Note that the current from the N ⁺ -type drain region 118 to the N ⁺ -type source region 116 during the on-state avoids the P-type diffusion layer 138 and causes a portion deeper than the P-type diffusion layer 138 (N ⁻ -type epitaxial layer 110). Therefore, the on-resistance is not increased by providing the P-type diffusion layer 138. The impurity concentration of the P-type diffusion layer 138 according to the present embodiment is, for example, 3 × 10 ¹⁷ pieces / cm ³ .

Next, an effect obtained by providing the P-type buried layer 109 in the first and second embodiments described above will be described. FIG. 3 shows the state of the depletion layer when the reverse bias voltage is increased in the lateral short-channel DMOS 1B according to the second embodiment. In FIG. 3, a depletion layer extending from the boundary between the N ⁻ type epitaxial layer 110 and the P type well 114 reaches the floating P type buried layer 109. The P-type buried layer 109 receives a voltage corresponding to the concentration and the width of the diffusion layer, and a floating P-type diffusion for relaxing the surface electric field strength at the step portion between the gate oxide film 120 and the field oxide film 136 on the wafer surface. The layer 138 has almost the same effect as the guard ring effect. Thereby, the relaxation of the electric field strength is further increased and the breakdown voltage can be improved. However, since it is necessary to prevent the depletion layers from contacting each other, the concentration of the P-type buried layer 109 and the width of the diffusion layer, the upper and lower diffusion amount and concentration of the N-type buried layer 108, and the P-type as viewed from above. It is necessary to appropriately set a lateral distance or the like of a portion that does not overlap with the buried layer 109.

In the case where the P-type buried layer 109 is not provided, when a reverse bias is applied between the source electrode 126 and the drain electrode 128, the breakdown finally occurs. However, the breakdown occurs at the channel formation region C or the floating P-type. This is a curved portion of the diffusion layer 138 (see FIG. 4). At this time, since the drain electrode 128 is on the same surface as the source electrode 126 and breakdown occurs near the surface, the breakdown current easily flows in the lateral direction, and is below the N ⁺ type source region 116. The P-type well 114 easily passes through a portion having a high resistance value or a silicon surface.

If current flows through this portion, electrical characteristics and reliability are likely to deteriorate, so that a two-stage base method has been generally used as an improvement method. This is because, as shown in FIG. 5, by inserting a P ⁺ -type diffusion layer 113 having a higher concentration and deeper depth than the P-type well 114, the electric field strength at the lower part of the P ⁺ -type diffusion layer 113 is increased. The final breakdown location is made lower than the P ⁺ type diffusion layer 113. Since the breakdown current does not pass through the portion where the resistance value of the P-type well 114 under the N ⁺ -type source region 116 is high or the silicon surface, the above-described deterioration in electrical characteristics and reliability is less likely to occur.

However, since it is necessary to add a new P ⁺ type diffusion, the manufacturing process increases, and when the P ⁺ type diffusion layer 113 is diffused, it must be diffused deeper than the P type well 114. Therefore, a photographic margin on the silicon surface of the source electrode 126 portion is further required, and there is a problem that the size of the source electrode 126 must be increased. Therefore, such P ⁺ -type diffusion is not introduced. However, there is a need for a method of breakdown inside silicon.

On the other hand, in the lateral short-channel DMOS 1B according to the present embodiment, the depletion layer is filled in the near saturation state in the N ⁻ type epitaxial layer 110 at the time of reverse bias, and the drain bias is relatively high. The N-type buried layer 108 and the floating P-type buried layer 109 which is biased close to the source bias are adjacent to each other, so that the place where the breakdown finally occurs is the N-type buried layer 108 and the P-type buried layer. It becomes a joint portion with the layer 109 (see FIG. 6). As described above, by providing the P-type buried layer 109, it is possible to improve the breakdown voltage and to prevent the deterioration of electrical characteristics and reliability.

  In the lateral short-channel DMOSs 1A and 1B according to the first and second embodiments, by providing the P-type buried region 141, the diffusion heat treatment time can be shortened by reducing the diffusion depth of the element isolation region 140. In addition, when the diffusion depth of the element isolation region 140 is reduced, the element area can be reduced by reducing the lateral diffusion distance.

In the first and second embodiments, N ^- type in the epitaxial layer 110, in order to adjust the breakdown voltage of the lateral short-channel DMOS N-channel, N ^- -type epitaxial layer 110 and the on-resistance lowering N-type well 134 An N-type well having an intermediate concentration may be added. As long as the depth of the N-type well is within a range that satisfies the breakdown voltage of the element, there is no problem even if it is in contact with the P-type buried layer 109 on the N-type buried layer 108. If the breakdown voltage of the lateral short-channel DMOS can be ensured by this N-type well, it becomes difficult to affect the characteristics of IC components other than the lateral short-channel DMOS in an IC or the like.

  In the first and second embodiments, silicon can be preferably used as the P-type semiconductor substrate 106. In addition to polysilicon, tungsten silicide, molybdenum silicide, tungsten, molybdenum, copper, aluminum, and the like can be preferably used as the material for the gate electrode. Further, tungsten, copper, aluminum or the like can be preferably used as the gate resistance reducing metal.

  Next, a method for forming the N-type buried layer 108 and the P-type buried layer 109 in the above-described embodiment will be described. 7 and 8 are process diagrams showing the manufacturing process of these buried layers. First, a thick oxide film 144 is formed on the P-type semiconductor substrate 106, and the oxide film 144 is etched through a photographic process where the N-type buried layer 108 is to be formed (FIG. 7A). Subsequently, the N-type buried layer 108 is formed by performing diffusion in a gas source atmosphere of an N-type impurity such as antimony or phosphorus, or implanting arsenic ions or the like (FIG. 7B).

  Subsequently, diffusion is performed in an oxygen atmosphere. Simultaneously with this diffusion, an oxide film 144 is also formed on the surface of the N-type buried layer 108 (FIG. 7C). Subsequently, in the oxide film 144 formed on the P-type semiconductor substrate 106, the oxide film 144 is etched through a photographic process at a place where the P-type buried layer 109 is formed (FIG. 7D).

  Subsequently, diffusion or ion implantation is performed in a gas source atmosphere of a P-type impurity such as boron to form a P-type buried layer 109a (FIG. 8A). Subsequently, when diffusion is performed in an oxygen atmosphere, a P-type buried layer 107 is formed. Simultaneously with this diffusion, an oxide film 144 is also formed on the surface of the P-type buried layer 107 (FIG. 8B). Boron used as an impurity of the P-type buried layer 107 has a larger diffusion coefficient than antimony and arsenic, which are impurities of the N-type buried layer 108, and can be diffused deeply even if diffusion is performed under the same diffusion conditions. In the case of FIG. 8B, since the surface concentration of the N-type buried layer 108 is higher than the concentration of the P-type buried layer 107, the surface of the P-type buried layer 107 has an impurity concentration of the N-type buried layer 108. Since it is winning, it is N type.

Subsequently, the oxide film 144 formed at the time of diffusion is entirely removed to form an N ⁻ type epitaxial layer 110. By heat treatment when the N ⁻ type epitaxial layer 110 is stacked, the P type and N type buried layers are diffused also in the direction of the N ⁻ type epitaxial layer 110, and the P type buried layer 109 and the N type buried layer 108 are formed. (FIG. 8C). In the above-described manufacturing process, the N-type buried layer 108 is formed first and the P-type buried layer 109 is formed after that because of the diffusion coefficient of impurities. Good.

  As described above, the embodiments of the present invention have been described in detail with reference to the drawings, but the specific configuration is not limited to these embodiments, and includes design changes and the like within a scope not departing from the gist of the present invention. It is.

1 is a cross-sectional view showing a structure of a lateral short-channel DMOS according to a first embodiment of the present invention. It is sectional drawing which shows the structure of the horizontal short channel DMOS by the 2nd Embodiment of this invention. It is sectional drawing which shows the state in which the depletion layer generate | occur | produced in the horizontal type short channel DMOS by 2nd Embodiment. It is sectional drawing for demonstrating the path of a breakdown current. It is sectional drawing for demonstrating the path of a breakdown current. It is sectional drawing for demonstrating the path of the breakdown current of the horizontal type short channel DMOS by 2nd Embodiment. It is process drawing which shows the manufacturing process of the embedded layer in 1st and 2nd embodiment. It is process drawing which shows the manufacturing process of the embedded layer in 1st and 2nd embodiment. It is sectional drawing which shows the structure of the conventional horizontal type short channel DMOS. It is sectional drawing which shows the other structure of the conventional horizontal type short channel DMOS.

Explanation of symbols

1A, 1B, 90, 92 ... lateral short channel DMOS, 106 ... P-type semiconductor substrate, 107, 109 ... P-type buried layer, 108 ... N-type buried layer, 110, 910 ... N ^- type epitaxial layer, 113 · · · ^{P +} -type diffusion layer, 114,914 ··· P-type well, 116,916 ··· ^{N +} -type source region, 118,918 ··· ^{N +} -type drain region, 120, 920... Gate insulating film, 122, 922... Polysilicon gate electrode, 124, 924 .. interlayer insulating film, 126, 926... Source electrode, 128, 928. , 930... Gate resistance reducing metal layer, 132, 932... Ground, 134... On-resistance reducing N-type well, 136. 140 ... element isolation region, 141 ... P-type buried region, 144 ... oxide film, 908 ... P ^- type semiconductor substrate.

Claims (5)

A second conductivity type epitaxial layer formed near the surface of the first conductivity type semiconductor substrate;
A first well of a first conductivity type including a channel formation region formed in the vicinity of the surface of the epitaxial layer;
A high-concentration source region of the second conductivity type formed in the vicinity of the surface of the first well;
A second well of a second conductivity type for reducing on-resistance formed near the surface of the epitaxial layer so as not to contact the first well;
A high-concentration drain region of the second conductivity type formed near the surface of the second well;
A gate electrode formed through a gate insulating film at least above the channel formation region of the region from the source region to the drain region;
The boundary between the semiconductor substrate and the epitaxial layer is formed at least in a portion overlapping with the first well when viewed from above, and includes a second conductivity type impurity having a concentration higher than that of the epitaxial layer, A first buried layer formed so as not to contact the well;
A first conductivity type second buried layer formed so as to cover an upper surface of the first buried layer so that at least a part of the first buried layer and the epitaxial layer are in contact with each other;
A lateral short-channel DMOS comprising:   2. The lateral short-channel DMOS according to claim 1, wherein the first buried layer is formed so as not to overlap the second well when viewed from above.   A diffusion layer of a first conductivity type is formed in the vicinity of the surface of the epitaxial layer between the first well and the drain region so as not to contact the first well. The lateral short-channel DMOS according to claim 1 or 2.   4. The lateral short-channel DMOS according to claim 3, wherein the diffusion layer is formed so as not to contact the second well. 5. The lateral short-channel DMOS according to claim 3, wherein in the region from the diffusion layer to the drain region, the gate electrode is opposed to the epitaxial layer through a field oxide film. .

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