JP2006020347A - Apparatus and method for generating coefficient - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To generate coefficients for converting image information of standard resolution supplied from outside to image information of high resolution. <P>SOLUTION: An image signal of SD (Standard Definition) data obtained through a vertical pixel-skipping filter 22 and a horizontal pixel-skipping filter 23 is segmented into a plurality of blocks by a block segmentation circuit 24. An ADRC (Adaptive Dynamic Range Coding) circuit 25 detects and compressed the pattern of the level distribution of the SD data supplied to each block to form pattern compressed data. A class code generation circuit 26 detects the class to which the block belongs based on the supplied pattern compressed data, and outputs the class code (class). A normal equation adding circuit 27 executes addition of the normal equation using the supplied class code (class), SD data, and HD pixel levels y that correspond to the SD data. A predictive coefficient determining circuit 28 solves the normal equation with respect to w<SB>i</SB>using the sweep-out method and the like, and calculates the predictive coefficients. The predictive coefficient determining circuit 28 stores the calculated predictive coefficients in a memory 29. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an image information conversion device suitable for use in, for example, a television receiver, a video tape recorder device, and the like, and in particular, converts normal resolution image information supplied from the outside into high resolution image information. The present invention relates to a coefficient generation apparatus and method suitable for use in an image information conversion apparatus that outputs data.

  Nowadays, development of a tape receiver capable of obtaining a higher resolution image is desired due to an increase in audio / visual orientation, and in response to this demand, a so-called high vision system has been developed. In this high-definition method, the number of scanning lines specified in the so-called NTSC method is 1125, which is more than twice the number of scanning lines, and the aspect ratio of the display screen is also high-definition for the NTSC method is 3: 4. The system is a wide-angle screen of 9:16. For this reason, a high-resolution and realistic screen can be obtained.

  However, although it is a high-definition system having such excellent characteristics, an image cannot be displayed even if an NTSC video signal is supplied as it is. This is because the standards differ between the NTSC system and the high vision system as described above. For this reason, when attempting to display in a high-definition system corresponding to an NTSC system video signal, conventionally, for example, an image information converter as shown in FIG. 8 is used to convert the video signal rate.

  In FIG. 8, a conventional image information conversion apparatus includes a horizontal interpolation filter 32 that performs horizontal interpolation processing of an NTSC video signal supplied via an input terminal 31, and a video that has undergone horizontal interpolation processing. An NTSC system signal that is composed of a vertical interpolation filter 33 that performs interpolation processing in the vertical direction of the signal and that has been subjected to interpolation processing in the horizontal direction and the vertical direction is taken out from the output terminal 34.

Specifically, the horizontal interpolation filter 32 has a configuration as shown in FIG. 9, and an NTSC video signal supplied via the input terminal 31 receives the first to first signals via the input terminal 41. The m-th multipliers 42 to 42 _m are respectively supplied. Each multiplier 42 multiplies the video signal by a coefficient and outputs the result. The video signals multiplied by the coefficients are supplied to _first to _mth adders 43 to 43 _m−1 , respectively. Delay registers 44 _{1 to} 44 _{m for} time T are provided between the adders 43 to 43 _m−1 , respectively. The video signal output from the mth multiplier 42 _m is delayed by time T by the mth delay register 44 _m and supplied to the _m− 1th adder 43 _m−1 .

The m−1th adder 43 _m−1 includes the video signal delayed by time T from the _mth delay register 44 _m and the video signal from the m−1th multiplier 42 _m−1. Are added and output. The video signal subjected to the addition processing is again delayed by time T by the (m-1) th delay register 44 _m-1 , and is also shown in the m-2th adder 43 _m-2 (not shown). The video signal from the _m- 2th multiplier 43 _m-2 is not added. In this way, the horizontal interpolation filter 32 supplies the NTSC video signal to the vertical interpolation filter 33 via the output terminal 45.

  The vertical interpolation filter 33 has the same configuration as the horizontal interpolation filter 32 described above, and performs pixel interpolation in the vertical direction on the video signal subjected to the horizontal interpolation processing. Thus, vertical pixel interpolation is performed on the NTSC video signal. The high-definition video signal thus converted is supplied to a high-definition receiver. As a result, an image corresponding to the NTSC video signal can be displayed on the high-definition receiver.

  However, as described above, the conventional image information conversion apparatus simply performs horizontal and vertical interpolation based on the NTSC video signal, so that the resolution is based on the NTSC standard. It was no different from the video signal. In particular, when a normal moving image is to be converted, it is generally performed by interpolation field processing in the vertical direction. However, in this case, since inter-field correlation of the image is not used, the NTSC is used in the still image portion. There is a drawback that the resolution is deteriorated compared to the video signal of the system.

On the other hand, in the conventional digital data conversion apparatus and method, classification is performed according to the distribution state of a plurality of input data, and data conversion related to each class, that is, class information is converted into output data, or class information is output data. A mapping table is used that translates into parameters to form This mapping table is formed in advance using source images of various patterns for training. Therefore, this mapping table can restore high-resolution components that are not included in the input image signal. (For example, refer to Patent Document 1.)
JP-A-5-328185

Further, in the conventional image signal conversion apparatus, a storage unit that performs class division according to the three-dimensional (spatio-temporal) distribution of the image signal level that is an input signal, and stores a prediction coefficient value obtained by learning in advance for each class. And an image signal converter that outputs an optimum estimated value by a calculation based on a prediction formula. (For example, see Patent Document 2.)
Japanese Patent Application Laid-Open No. 7-079418 (Japanese Patent Application No. 5-172617)

  In this method, when creating HD (High Definition) pixels, a plurality of SD (Standed Definition) pixel data existing in the vicinity thereof are divided into classes in terms of time and space, and prediction coefficient values are obtained for each class. Is obtained by learning, using the correlation in the time direction such as between fields and between frames in the still image portion, and by using only the intra-field correlation in the motion portion, an HD pixel value close to the true value is obtained. , Is a clever thing.

That is, in FIG. 10, when the difference value of the SD pixel x ₁ and SD pixels x ₂ is small, HD pixels y periphery of the image to create is likely to be stationary. Therefore, in the image signal conversion apparatus, the HD pixel y is created by placing emphasis on the SD pixel x ₁ and the SD pixel x ₂ having a low spatial position. On the other hand, when the difference value between the SD pixel x ₁ and the SD pixel x ₂ is large, there is a high possibility that the image around the HD pixel y to be created is moving. Therefore, in the image signal conversion apparatus, the HD pixel y is created by placing emphasis on the SD pixel x ₃ and the SD pixel x ₄ that are close in time.

  According to this method, the static / motion switching can be expressed smoothly by learning using actual images, so that the occurrence of unnaturalness due to the switching of static / motion is greatly increased as in the conventional motion adaptation method. Can be reduced.

  However, the above-described method needs to express motion information and a waveform in a section by a finite number of class divisions. Depending on the class, patterns that should be separated are mixed in one class. There was a case.

For example, in FIG. 10, when the difference value between the SD pixel x ₁ and the SD pixel x ₂ is small, the surrounding image is very likely to be still as described above, but it is a slight possibility. However, the image may actually be moving. For example, when a moving object has entered only the (k−1) field, or an object in the image is moving between the k field and the (k + 2) field, it happens that the SD pixel x ₁ and the SD pixel x _Since the difference value of ₂ is small, the HD pixel y is created in the image signal conversion device with emphasis on the SD pixel x ₁ and the SD pixel x ₂ that are close to each other in spatial position. Therefore, in this case, the error between the created HD pixel and the true HD pixel is large, and the quality of the restored image is noticeably deteriorated.

  As a countermeasure, a method of reducing the quality degradation of the restored image by increasing the number of pixels used for class division and increasing the number of classes may be considered. However, according to this method, the number of classes becomes very large, resulting in an increase in hardware scale and poor realism.

  Therefore, the present invention has been made in view of the above-described problems, and is used for an image information conversion apparatus capable of improving resolution and converting an NTSC video signal into a high-definition video signal. An object of the present invention is to provide a suitable coefficient generation apparatus and method.

The present invention provides a thinning means for thinning out pixels of a high-resolution digital image signal at a predetermined ratio to generate thinned image information;
Image information dividing means for dividing the thinned image information into a plurality of blocks;
Class detection means for detecting a level distribution pattern of image information for each divided block, determining a class to which image information for each block belongs based on the detected pattern, and outputting class detection information;
Coefficient data generating means for generating coefficient data for obtaining a target pixel of a high-resolution digital image signal corresponding to the image information for each block from the image information for each block of the determined class;
And a memory unit that stores the generated coefficient data for each determined class.

The present invention also thins out pixels of a high-resolution digital image signal at a predetermined ratio, generates thinned image information,
Divide the thinned image information into multiple blocks,
A level distribution pattern of image information is detected for each divided block, and based on the detected pattern, a class to which the image information for each block belongs is determined, and class detection information is output,
Generating coefficient data for obtaining a pixel of interest of a high-resolution digital image signal corresponding to the image information for each block from the image information for each block of the determined class,
The coefficient generation method is characterized in that the generated coefficient data is stored in a memory unit for each determined class.

  According to the present invention, the estimated HD image is down-converted, the down-converted image is divided into a plurality of blocks, and the target pixel of the HD image is obtained from the down-converted image for each divided block. Image data is stored in a memory, and the image data of normal resolution is converted into high resolution image information by using the coefficient data stored in the memory. It can be greatly improved.

  Embodiments of an image signal converter according to the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a schematic configuration of signal processing of this embodiment, that is, an image signal conversion apparatus. For example, a so-called NTSC video signal is digitized and supplied as SD data as image information supplied from the input terminal 1.

The positional relationship between the SD pixel and the HD pixel to be created in this embodiment is as shown in FIG. That is, in the same field, there are two types of HD pixels to be created: HD pixel y ₁ that exists near the SD pixel and HD pixel y ₂ that exists far from the SD pixel. Hereinafter, a mode for estimating an HD pixel existing at a position close to the SD pixel is referred to as mode 1, and a mode for estimating an HD pixel existing at a position far from the SD pixel is referred to as mode 2.

The area dividing circuit 2 divides the SD image signal supplied from the input terminal 1 into a plurality of areas. In this embodiment, for example, two upper and lower SD pixels of HD pixels to be created for mode 1 are divided into a total of four pixels of 1 pixel × 4 lines. This area will be called block 1. SD pixels of the block 1 for HD pixel y1 becomes _{x 1, x 2, x 3} , x 4 in FIG.

On the other hand, for mode 2, two types of area division are performed. First, in the same manner as in mode 1, for example, each of the upper and lower HD pixels to be created is divided into areas each consisting of four pixels of 1 pixel × 4 lines. SD pixels of the domain block 2-1, the _{x 1, x 2, x 3} , x 4 in FIG.

Further, for mode 2, a 4-pixel region division including SD pixels belonging to other fields is performed. Specifically, for example, one HD pixel, one pixel above and below each HD pixel to be created, is made into a block, and so-called region division having a spatio-temporal structure is performed. This area will be called a block 2-2. SD pixel block 2-2 for HD pixel y2 becomes _{x 1, x 2, x 3} , x 4 in FIG. 3.

  The data blocked by the area dividing circuit 2 is supplied to the ADRC circuit 3 and the delay circuit 6. The delay circuit 6 delays the data by the time necessary for processing of the ADRC circuit 3, the class code generation circuit 4, and the ROM table 5 and outputs the data to the estimation calculation circuit 7.

  The ADRC circuit 3 detects a one-dimensional or two-dimensional level distribution pattern of the SD data supplied for each region, and converts the data of each region into 2 bits from, for example, 8-bit SD data as described above. Pattern compression data is formed by performing operations such as compression into bit SD data, and this pattern compression is supplied to the class code generation circuit 4.

  Originally, ADRC (Adaptive Dynamic Range Coding) is an adaptive requantization method developed for high-efficiency coding for VTRs, but it can efficiently express a local pattern at a signal level with a short word length. In the embodiment of the present invention, it is used for code generation of signal pattern classification. The ADRC circuit 3 sets the dynamic range in the region as DR, bit allocation as n, the pixel level in the region as L, the requantization code as Q, and the maximum value MAX in the region as Re-quantization is performed by equally dividing the space between the minimum value MIN and the designated bit length.

DR = MAX-MIN + 1
Q = {(L−MIN + 0.5) × 2 ⁿ / DR} (1)
However, {} means a truncation process.

In this embodiment, SD data of 4 pixels each separated by the region separation circuit 2 is compressed to 2 bits each. The compressed SD data, respectively, and q ₁ to q _4.

  The class code generation circuit 4 detects the class to which the block belongs by performing the following equation (2) based on the pattern compression data supplied from the ADRC circuit 3, and the class code class indicating the class is It is supplied to the ROM table 5. This class code class indicates an address read from the ROM table 5.

この実施例では、ｎは４、ｐは２である。

In this embodiment, n is 4 and p is 2.

  In the ROM table 5, coefficient data for calculating HD data corresponding to the SD data is stored for each class using a linear estimation formula by learning the relationship between the SD data pattern and the HD data. . This is information for converting SD data into HD data conforming to a so-called high-definition standard, which is image information having a resolution higher than that of the image information, using a linear estimation formula.

In this embodiment, the coefficient data is prepared independently for each of mode 1 and mode 2, and regarding mode 2, the data of block 2-1 and the data of block 2-2 are used. The coefficient data is prepared independently. A method for creating coefficient data stored in the ROM table 5 will be described later. From the ROM table 5, w _i (class) which is coefficient data of the class is read from the address indicated by the class code class. The coefficient data is supplied to the estimation calculation circuit 7.

The estimation calculation circuit 7 inputs the SD data based on the SD data supplied from the area dividing circuit 2 and the coefficient data _wi (class) supplied from the ROM table 5 via the delay circuit 6. HD data corresponding to the data is calculated. The estimation calculation circuit 7 will be described in detail with reference to FIG.

The SD data supplied from the delay circuit 6 and the coefficient data supplied from the ROM table 5 are first supplied to the initial estimation calculation circuit 11. The initial estimation calculation circuit 11 uses the coefficient for the block 1 in the mode 1 and performs the calculation shown in the following equation (3) based on the coefficient data w _i (class), thereby inputting HD data corresponding to the SD data is calculated. Further, there are two types of data for the mode 2 HD pixels.

  The HD data created using the mode 1 HD data and the coefficient data for the block 2-2 among the mode 2 HD data is supplied to the vertical thinning filter 12. The HD data in mode 1 is also supplied to the horizontal interpolation filter 8 at the same time. The HD data created using the coefficient data for the block 2-2 is supplied to the switch circuit 14 at the same time. The mode 2 HD data created using the coefficient data for the block 2-1 is supplied to the switch circuit 14.

hd ′ = w ₁ x ₁ + w ₂ x ₂ + w ₃ x ₃ + w ₄ x ₄ (3)

  The vertical thinning filter 12 is the same as the vertical thinning filter 22 described in detail later, and thins the number of pixels in the vertical direction of the HD image signal to the number of pixels of the SD image signal by filtering. The vertical decimation filter 12 down-converts the HD data supplied from the initial estimation calculation circuit 11 to create SD data, and outputs the SD data to the comparison determination circuit 13.

  The comparison determination circuit 13 is supplied with the SD data generated by the down-conversion of the estimated HD data generated by the vertical thinning filter 12 and the SD data supplied from the delay circuit 6. The comparison determination circuit 13 compares the original SD data supplied from the delay circuit 6 with the SD data supplied from the vertical thinning filter 12 and created by down-converting the estimated HD data.

  Original SD data supplied from the delay circuit 6 is originally down-converted from true HD data by the same filter as the vertical thinning filter 12. Therefore, if the HD data estimated by the initial estimation arithmetic circuit 11 completely matches the true value, the original SD data supplied from the delay circuit 6 and the estimated HD data supplied from the vertical thinning filter 12 are estimated. Should match. However, since it is virtually impossible to completely estimate the HD data from the SD data, it is common that some errors occur.

  However, a large error may occur in the comparison / determination circuit 13. In this case, there is a high possibility that a large error has occurred when estimating HD data in the vicinity of the SD data in which the error has occurred.

  Now, the estimation of the pixels in mode 1 is performed by the complete intra-field estimation method. Therefore, extreme performance degradation does not occur due to movement or the like, and it is unlikely that a large error will occur in mode 1 pixel estimation.

  In contrast, mode 2 pixel estimation is performed by an estimation method having a spatiotemporal tap structure. An estimation method with this structure has high estimation accuracy on average, but if this estimation is performed in a class that is not so many, a very large error may occur due to a mistake in determining that the moving image scene is still. is there.

  Therefore, if a large error occurs in the comparison / determination circuit 13, it can be said that there is a high possibility that a large error has occurred when estimating HD data in mode 2 near the SD data in which the error has occurred.

  Therefore, in the estimation operation circuit 7, when there is no error in the HD data output in mode 2 and the comparison in the comparison / determination circuit 13 is small or small, it is calculated by estimation using the pixel of the block 2-2 and coefficient data. Output the HD data. Further, in the comparison by the comparison / determination circuit 13, when the error is large, the HD data calculated by the estimation using the pixel of the block 2-1 and the coefficient data is output. In HD data output in mode 1, HD data calculated by estimation using the pixel of block 1 and coefficient data is always output.

Specifically, the threshold value TH in which there is an error between the original SD data and the SD data created by down-converting the estimated HD data in the SD data x ₁ and x ₂ in FIG. In the case of exceeding, the output data in the HD data y of mode 2 uses the HD data calculated by the estimation using the pixel of the block 2-1 and the coefficient data. HD data calculated by estimation using the pixel and coefficient data are used.

  The horizontal interpolation filter 8 is the same as the horizontal interpolation filter 33 in FIG. 8, and doubles the number of pixels in the horizontal direction by interpolation processing. The output of the horizontal interpolation filter 8 is output via the output terminal 9. The HD data output via the output terminal 9 is supplied to, for example, an HD television receiver or an HD video tape recorder device.

  As described above, the coefficient data for estimating the HD data corresponding to the SD data is obtained by learning for each class in advance and stored in the ROM table 5, and the input SD data and the ROM table 5 are stored. The HD data corresponding to the input SD data is formed and output based on the coefficient data read out from the actual SD data. Can be output.

  Moreover, if the improvement is made by increasing the class classification, the number of classes becomes enormous. However, according to the method of the present invention, a mode that requires twice as many classes as the conventional one is required by the mode 2 estimation. As the total number of classes, a significant improvement in image quality can be obtained with a sufficiently practical number of classes that is 1.5 times the number of classes.

  Next, a method for creating coefficient data stored in the ROM table 5 will be described with reference to FIG. In order to obtain coefficient data by learning, first, an SD image having a 1/4 pixel number of an HD image corresponding to an already known HD image is formed. Specifically, with the ideal filter circuit shown in FIG. 6, the vertical frequency of the HD data supplied via the input terminal 21 is halved by the vertical thinning filter 22 in the vertical direction in the field. Then, the horizontal thinning filter 23 thins out pixels in the horizontal direction of the HD data to obtain SD data. SD data obtained by the vertical thinning filter 22 and the horizontal thinning filter 23 is supplied to the area dividing circuit 24.

  In the area dividing circuit 24, the SD image signal supplied from the horizontal thinning filter 23 is divided into a plurality of areas. Specifically, the area dividing circuit 24 has the same function as the area dividing circuit 2 described above. In this embodiment, similarly to the area dividing circuit 2, the area is divided into 4 pixels. That is, area division of the area of block 1 is performed for mode 1, and two types of area division of block 2-1 and block 2-2 are performed for mode 2. The SD data for each area is supplied to the ADRC circuit 25 and the normal equation adding circuit 27.

The ADRC circuit 25 detects a one-dimensional or two-dimensional level distribution pattern of the SD data supplied for each region, and, as described above, all or a part of the data in each region. For example, pattern compression data is formed by performing an operation such as compression from 8-bit SD data to 2-bit SD data, and the pattern compression data is supplied to the class code generation circuit 26. The ADRC circuit 25 is the same as the ADRC circuit 3 described above. In this embodiment, the SD data of each area composed of four pixels divided by the area dividing circuit 24 (in FIGS. 2 and 3). x _{1 to} x ₄ ) are compressed to 2 bits each by ADRC.

  The class code generation circuit 26 is the same as the class code generation circuit 4 described above, and by performing the calculation of the expression (2) based on the pattern compression data supplied from the ADRC circuit 25, the block is generated. A class to which the class belongs is detected, and a class code class indicating the class is output. The class code generation circuit 26 outputs the class code class to the normal equation addition circuit 27.

Here, in order to explain the normal equation adding circuit 27, learning of a conversion formula from a plurality of SD pixels to HD pixels and signal conversion using the prediction formula will be described. For the sake of explanation, a case where prediction is performed using n pixels by generalizing pixels will be described below. X ₁ The SD pixel level, ...., as x _n, a result of the p-bit ADRC to each re-quantized data q _1, ..., a q _n. At this time, the class code class of this area is defined by equation (2).

As described above, the SD pixel level, respectively, x _1, · · · ·, and x _n, when the HD pixel level was y, the coefficient data w ₁ for each class, · · · ·, n taps by w _n Set the linear estimation formula. This is shown in equation (4). Here, w _i is an undetermined coefficient before learning.

y = w ₁ x ₁ + w ₂ x ₂ + w ₃ x ₃ + w ₄ x ₄ (4)

  Learning is performed on a plurality of signal data for each class. When the number of data is m, equation (5) is set according to equation (4).

_{y = w 1 x j1 + w} 2 x j2 + w 3 x j3 + w 4 x j4 (5)
(J = 1, 2,..., M)

When m> n, the coefficient data w ₁ ,... w _n are not uniquely determined. Therefore, the element of the error vector e is defined by Expression (6), and coefficient data that minimizes Expression (7) is obtained. . This is a so-called least square method.

_{e j = y j - {w} 1 x j1 + w 2 x j2 + w 3 x j3 + w 4 x j4} (6)
(J = 1, 2,..., M)

Here, the partial differential coefficient according to w _i in equation (7) is obtained. It may be obtained each w _i to the equation (8) to "0".

Hereinafter, as defined in equations (9) and (10), when X _ji and Y _i are defined, equation (8) is rewritten into equation (11) using a matrix.

This equation is generally called a normal equation. In the normal equation adding circuit 27, the class code class supplied from the class code generating circuit 26, the SD data x ₁ ,..., X _n supplied from the area dividing circuit 24, the SD supplied from the input terminal 21. This normal equation is added using the HD pixel level y corresponding to the data.

After all the training data has been input, the normal equation adding circuit 27 outputs the normal equation data to the prediction coefficient determining circuit 28. The prediction coefficient determination circuit 28 solves w _i by using a general matrix solving method such as a sweeping method, and calculates a prediction coefficient. The prediction coefficient determination circuit 28 writes the calculated prediction coefficient into the memory 29.

As a result of the training as described above, the memory 29 stores, for each pattern defined by the quantized data q _{1 to} q ₄ , the statistically closest pixel for estimating the target HD data y. Stores the prediction coefficients for which an estimate can be generated. The table stored in the memory 29 is the ROM table 5 used in the image signal converter of the present invention. With the above processing, learning of coefficient data for creating HD data from SD data using the linear estimation formula is completed.

  Here, FIG. 7 shows another embodiment of the comparison / determination portion in the estimation arithmetic circuit according to the present invention. HD data created using mode 1 HD data, that is, coefficient data for block 1, is supplied from the input terminal 31, and coefficient data for block 2-2 of the HD data of mode 2 is used from the input terminal 32. The HD data created in this way is supplied, and the HD created using the coefficient data for block 2-1 of the mode 2 HD data is supplied from the input terminal 33.

  The HD data created using the coefficient data for block 1 is supplied to the vertical thinning circuits 34 and 35 for thinning processing. The vertical thinning circuits 34 and 35 have the same function as the vertical thinning circuit 12 described above. The HD data created using the coefficient data for the block 2-1 is supplied to the vertical thinning circuit 34, and the HD data created using the coefficient data for the block 2-2 is supplied to the vertical thinning circuit 35. Each of them is thinned out.

  In the vertical thinning circuit 34, the thinned mode 1 HD data and the HD data created using the coefficient data of the block 2-1 of the mode 2 HD data are supplied to the comparison circuit 36, and the error is reduced. Detected. The detected error is supplied to the determination circuit 38. Similarly, in the vertical thinning circuit 35, the thinned mode 1 HD data and the HD data created using the coefficient data of the block 2-2 of the mode 2 HD data are supplied to the comparison circuit 36. An error is detected. The detected error is supplied to the determination circuit 38.

  The determination circuit 38 determines which error of the two types of HD data in mode 2 is smaller than that in the mode 1 HD data, and the switch 39 is controlled based on the determination result. Created by using the mode 1 HD data and the block 2-1 coefficient data in the determination circuit 38 as compared with the error between the mode 1 HD data and the HD data created using the block 2-2 coefficient data. If it is determined that the error from the HD data is small, the HD data created using the pixel of the block 2-1 and the coefficient data of the block 2-1 is selected by the switch 39 and taken out from the output terminal 40. It is.

  In addition, the determination circuit 38 uses the mode 1 HD data and the block 2-2 coefficient data in comparison with the error between the mode 1 HD data and the HD data created using the block 2-1 coefficient data. When it is determined that the error with the HD data created in this way is small, the HD data created using the pixel of the block 2-2 and the coefficient data of the block 2-2 is selected by the switch 39, and the output terminal 40 Taken from.

  In the description of the embodiment, the ADRC is provided as the information compression means. However, this is only an example, and any information compression means that can be expressed by a class having few signal waveform patterns is provided. For example, compression means such as DPCM (predictive coding) or VQ (vector quantization) may be used.

  Further, in the description of the embodiment, for the sake of simplicity, the horizontal interpolation filter 9 is used for horizontal up-conversion. Instead, a horizontal up-conversion ROM is prepared, and estimation is also performed for horizontal up-conversion. Of course, it is possible to adopt a method using an equation.

  Furthermore, in the description of the embodiment, the signal waveform pattern is expressed by one-dimensional division by the region dividing circuit 4, but may be divided into two-dimensional divisions.

  The present invention is not limited to the above-described embodiment of the present invention, and various modifications and applications are possible without departing from the spirit of the present invention.

It is a block diagram which shows one Example of the image information converter concerning this invention. It is a basic diagram for demonstrating the positional relationship of SD data and HD data, and the data used for a class division. It is a basic diagram for demonstrating the data used for a class division. It is a block diagram which shows one Example of the image information converter concerning this invention. It is a basic diagram for demonstrating operation | movement of an estimation arithmetic circuit. It is a block diagram for explanation when creating a correction data table. It is a block diagram which shows the other Example of the image information converter which concerns on this invention. It is a block diagram which shows an example of the conventional image information converter. It is a block diagram which shows an example of the principal part of the conventional image information converter. It is a basic diagram for demonstrating the positional relationship of SD data and HD data, and the problem of the conventional space-time class division system.

Explanation of symbols

2 area division circuit 3 ADRC circuit 4 class code generation circuit 5 ROM table 6 delay circuit 7 estimation operation circuit 8 horizontal interpolation filter

Claims (6)

Thinning means for thinning out pixels of a high-resolution digital image signal at a predetermined ratio and generating thinned image information;
Image information dividing means for dividing the thinned image information into a plurality of blocks;
A class detection unit that detects a level distribution pattern of the image information for each of the divided blocks, determines a class to which the image information for each block belongs based on the detected pattern, and outputs class detection information When,
Coefficient data generating means for generating coefficient data for obtaining a target pixel of the high-resolution digital image signal corresponding to the image information for each block from the image information for each block of the determined class;
And a memory means for storing the generated coefficient data for each of the determined classes. In the image information dividing means, mode dividing means for dividing the thinned image information into blocks of the first mode and / or the second mode;
2. The coefficient generation apparatus according to claim 1, wherein the second mode of the mode dividing means includes field dividing means for dividing the block into blocks in the same field and / or between a plurality of fields. The coefficient data generating means is
The coefficient data is generated by a linear estimation equation using the image information for each block of the determined class and the target pixel of the high-resolution digital image signal corresponding to the image information for each block. The coefficient generation device according to claim 1, wherein A high-resolution digital image signal is thinned out at a predetermined rate to generate thinned image information,
Divide the thinned image information into multiple blocks,
A pattern of level distribution of the image information is detected for each of the divided blocks, a class to which the image information for each block belongs is determined based on the detected pattern, and class detection information is output,
Generating coefficient data for obtaining a target pixel of the high-resolution digital image signal corresponding to the image information for each block from the image information for each block of the determined class,
A coefficient generation method characterized in that the generated coefficient data is stored in a memory unit for each of the determined classes. Dividing the thinned image information into blocks of a first mode and / or a second mode;
5. The coefficient generation method according to claim 4, wherein the second mode is divided into blocks within the same field and / or between a plurality of fields. The above coefficient data is
The image information for each block of the determined class and the target pixel of the high-resolution digital image signal corresponding to the image information for each block are generated by a linear estimation equation. The coefficient generation method according to claim 4.

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