JP4241720B2 - Multiply and accumulate circuit - Google Patents

Description

  The present invention relates to a product-sum operation circuit that can obtain substantially the same result even when a smaller number of multiplicands and multipliers are used when a plurality of multiplicands are multiplied by the multipliers.

  Nowadays, development of a television receiver capable of obtaining a higher resolution image is desired due to an increase in audio / visual orientation, and so-called high vision has been developed in response to this demand. This high-definition has 1125 lines more than twice the number of scanning lines 525 defined in the so-called NTSC system, and the aspect ratio of the display screen is 9:16 compared to 3: 4 for the NTSC system. And a wide-angle screen. For this reason, a high-resolution and realistic screen can be obtained.

  Here, although it is a high vision having such excellent characteristics, even if an NTSC video signal is supplied as it is, an image cannot be displayed. This is because the standards differ between the NTSC system and the high vision system as described above. For this reason, when an image corresponding to an NTSC video signal is to be displayed in high definition, conventionally, the supplied NTSC video signal (SD (Standerd Definition) data) is subjected to a horizontal interpolation process, and thereafter Video signal rate conversion was performed by performing vertical interpolation processing.

  This horizontal direction and vertical direction interpolation processing is composed of cascaded FIR filters, and these are merely performing interpolation in the horizontal direction and vertical direction. Therefore, the resolution is based on the NTSC system. The video signal was not different. In particular, when a normal image is to be converted, it is common to perform vertical interpolation by intra-field processing, but in that case, since the inter-field correlation of the image is not used, However, due to conversion loss, there is a drawback that the resolution is deteriorated rather than the NTSC video signal.

  On the other hand, the applicant performs class division according to the three-dimensional (spatio-temporal) distribution of the image signal level as the input signal in the image signal conversion apparatus of Japanese Patent Application No. 6-205934, and learns in advance for each class. Has proposed a storage means for storing a prediction coefficient value obtained by the above-described method and outputting an optimum estimated value by a calculation based on a prediction formula.

  In this method, when HD (High Definition) data is created, class division is performed using SD data in the vicinity of the created HD pixel, and a prediction coefficient value is obtained by learning for each class. It is a clever technique to obtain HD data closer to the true value in the stationary part.

For example, an average value of inter-frame differences between pixels at the same spatial position of each of the SD pixels m _{1 to} m ₅ and SD pixels n _{1 to} n ₅ shown in FIG. By class classification, class classification is mainly performed for expressions of the degree of movement. At the same time, as shown in FIG. 7, the SD pixels k _{1 to} k ₅ are subjected to ADRC (Adaptive Dynamic Range Coding) processing, thereby performing class classification mainly for the purpose of waveform representation in space with a small number of bits.

For each class determined by the above two types of class classification, a linear linear expression is formed using SD pixels x _{1 to} x ₂₅ as shown in FIG. 9, and a prediction coefficient value is obtained by learning. In this method, class classification that mainly represents the degree of motion and class classification that mainly represents the waveform in the space are individually performed in a suitable form, so high conversion performance can be obtained with a relatively small number of classes. There is a characteristic. Estimating calculation of HD pixel y is performed in the formula (1) as follows using the prediction coefficients w _n obtained by the above procedure.

y = w ₁ x ₁ + w ₂ x ₂ +... + w _n x _n (1)
In this example, n = 9.

  As described above, the prediction coefficient value for estimating the HD data corresponding to the SD data is obtained by learning in advance for each class, stored in the ROM table, and read from the input SD data and the ROM table. By outputting the predicted coefficient value, data that is closer to the actual HD data can be output, unlike the case where the input SD data is simply interpolated.

  A product-sum operation circuit used in such an image signal conversion apparatus is shown in FIG. A plurality of SD data is supplied from the multiplicand register 51 to the multiplier / summer 52. The class code class corresponding to the plurality of SD data is supplied from the address control circuit 53 to the multiplier memory 54, and the multiplier memory 54 supplies the coefficient data corresponding to the class code class to the multiplier / summer 52. The product-sum unit 52 performs a product-sum operation on the SD data and the coefficient data, and the product-sum output is output from the output terminal 55.

  As an example of the product-sum multiplier 52, as shown in FIG. 11, SD data is supplied from an input terminal 61, and the SD data is supplied to a multiplier 65 via a register 62. Coefficient data is supplied from the input terminal 63, and the coefficient data is supplied to the multiplier 65 via the register 64. The multiplier 65 multiplies the SD data and the coefficient data, and the multiplication output is supplied to the adder 67 via the register 66. In the adder 67, the two multiplication outputs are added, and the addition output is supplied to the adder 69 via the register 68. In the adder 69, two additional outputs are added, and a product-sum output is output from the output terminal 71 via the register 70.

  Thus, in the calculation using the product-sum operation circuit, a multiplier (coefficient data) is prepared in advance in a memory or the like, and a configuration in which the multiplier can be varied according to image characteristics (that is, class information) is used for image signal conversion. It was used.

  Increasing the number of classes and the number of types of multipliers can improve the accuracy of image estimation. However, there is a problem that the larger the number of types of multipliers, the larger the capacity of the multiplier memory and the hardware scale.

  Accordingly, an object of the present invention is to provide a product-sum operation circuit capable of reducing the hardware scale in view of the above-described problems.

In order to achieve the above-described problem, the present invention provides a product-sum operation circuit in which a digital filter operation is performed with M taps by adding a product of a multiplier and a multiplicand.
An input means for inputting a digital signal;
It is represented by a third bit number composed of a first bit number representing the degree of movement of the pixel of interest in the input digital signal and a second bit number representing the degree of waveform in the spatial direction around the pixel of interest. When the value represented by the first number of bits is equal to the threshold value , the L-bit class code is changed to the S-bit class code represented by the fourth number of bits that is smaller than the third number of bits. If the value expressed by the first bit number is different from the threshold value, the value expressed by the second bit number is reduced to 1/2, and the first bit number is reduced to 1/2. Converting means for converting the second bit number thus converted into an S-bit class code represented by a fourth bit number ;
Multiplier data reading means for reading M multiplier data corresponding to the address from the multiplier memory using the S-bit class code as an address;
It is a product-sum operation circuit having operation means for generating a product-sum output of M multiplier data read from the multiplier memory and M multiplicand data.

  According to the present invention, the addition circuit of the circuit itself is increased by having the address degeneration operation circuit. However, since the hardware scale reduction of the coefficient memory and the product-sum unit is considerably larger than that, the hardware is greatly reduced. The scale can be reduced. Further, by degenerating the address, image quality performance substantially equivalent to the original performance can be obtained even if the coefficient memory originally controlled by the L bit is replaced with the coefficient memory controlled by the S bit.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 schematically shows a configuration for explaining an embodiment of the present invention. The multiplicand register 1 stores SD data as a multiplicand, and the SD data is supplied from the multiplicand register 1 to the multiplier 2. The address control circuit 3 generates an L-bit class code class based on the SD data, and the generated L-bit class code L-class is supplied to the address degeneration memory 4.

  The address degeneration memory 4 includes a data conversion table for degenerating the supplied class code from L bits to S bits. Therefore, the S-bit class code S-class corresponding to the L-bit class code L-class is read, and the read class code S-class is supplied to the coefficient memory 5. In the coefficient memory 5, coefficient data in response to the supplied class code S-class is read, and the read coefficient data is supplied to the product-sum multiplier 2. The coefficient memory 5 stores coefficient data obtained by learning in advance. The product-sum unit 2 performs a product-sum operation on the pixel data and the coefficient data, and outputs the product-sum result, that is, HD (High Definition) data from the output terminal 6.

  FIG. 2 shows an example of a data conversion table that can be used for the address degeneration memory 4. The class code L-class supplied from the address control circuit 3 is, for example, 6-bit data. This 6-bit class code is a 2-bit class classification (hereinafter referred to as a motion class) for mainly representing the degree of motion. And a class classification (hereinafter referred to as a space class) consisting mainly of 4 bits for waveform expression in space. Here, this 6-bit class code is reduced to a 5-bit class code.

  As shown in FIG. 2, the motion class mv-class is represented by 0, 1, and 2. When the motion class mv-class is 0, there is no change in the number of addresses before and after degeneration, and when the motion class mv-class is 1 and 2, the number of addresses is degenerated by half before and after the degeneration. For this reason, the total number of addresses is reduced from 48 to 32 by degeneration, and can be expressed by 5 bits.

  Further, as shown in FIG. 3, the motion class mv-class can be represented by 0, 1, 2, and 3. At this time, when the motion class mv-class is 0, 1, and 2, it is degenerated as described above. However, when the motion class mv-class is 3, the motion class mv-class is degenerated to the same address as 2. For example, when the address before degeneration is 32, the address after degeneration is 24. Similarly, when the address before degeneration is 48, the address after degeneration is 24. When the address before degeneration is 42, the address after degeneration is 29. Similarly, when the address before degeneration is 58, the address after degeneration is 29.

  Next, another embodiment of the product-sum operation circuit of the present invention is shown in FIG. In the description of the other embodiments, the same parts as those in the above-described embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  A plurality of pixel data is supplied from the multiplicand register 1 to the multiplier / summer 2. In the address control circuit 3, the L-bit class code L-class is supplied to the degeneration operation circuit 11. In the degeneration operation circuit 11, as will be described later, an operation is performed to reduce the supplied L-bit class code L-class to an S-bit class code S-class. The degenerated class code S-class is supplied from the degeneration operation circuit 11 to the coefficient memory 5. In the coefficient memory 5, coefficient data responding to the class code S-class is read and supplied to the product-sum multiplier 2. The product-sum unit 2 performs a product-sum operation on the pixel data and the coefficient data, and the product-sum output is output from the output terminal 6.

  Here, a detailed circuit diagram of the degeneration operation circuit 11 is shown in FIG. The LSB of the motion class mv-class is supplied from the input terminal 21 and supplied to the OR gate 27. The MSB of the motion class mv-class is supplied from the input terminal 22 and supplied to the 2nd-MSB on one input side of the OR gate 27 and the adder 28. The OR gate 27 receives bits from the input terminals 21 and 22, and its output is input as the MSB on one input side of the adder 28. The bit from the input terminal 22 is supplied as one 2nd-MSB of the adder 28. One LSB, 2nd-LSB, and 3rd-LSB of the adder 28 are grounded. That is, it is always `0 '.

  The space class LSB is supplied from the input terminal 23, the space class 2nd-LSB is supplied from the input terminal 24, the space class 2nd-MSB is supplied from the input terminal 25, and the space class MSB is supplied from the input terminal 26. Is done. Bits from these input terminals 23, 24, 25 and 26 are supplied to the shift register 29. The MSB on the input side of the shift register 29 is grounded, the MSB bit of the space class is supplied to the 2nd-MSB on the input side of the shift register 29, and the space class 2nd is supplied to the 3rd-LSB on the input side of the shift register 29. -MSB is supplied, 2nd-LSB of the space class is supplied to 2nd-LSB on the input side of the shift register 29, and LSB of the space class is supplied to LSB on the input side of the shift register 29.

  The shift register 29 is supplied with a control signal for controlling the N-bit shift from the outside, and this control signal corresponds to the motion class mv-class. In another embodiment, a 1-bit shift control signal is provided. When the motion class mv-class is 0, in the shift register 29, the lower 4 bits are supplied to the other input side of the adder 28, and when the motion class mv-class is not 0, the supplied bit is 1 on the LSB side. Shifted bit by bit. By the 1-bit shift, the output of the shift register 29 is set to a half value of the input. The shifted 4-bit data is supplied to the other input side of the adder 28. The MSB on the other input side of the adder 28 is grounded. In the adder 28, the input data are added and output from the output terminal 31 via the register 30 as 5-bit data.

  As an example, when the class code class is `010011 ',` 10000` is supplied to one input side of the adder 28 and `00001` is supplied to the other input side. The output is `10001 ', and the class code class is degenerated. That is, the class code class is degenerated from 19 to 17. Similarly, when the class code class is `100101 ',` 11000' is supplied to one input side of the adder 28 and `00010 'is supplied to the other input side. The output is `11010 ', and the class code class is degenerated. That is, the class code class is degenerated from 37 to 26.

FIG. 6 shows an example of a signal conversion apparatus configured using the estimation arithmetic circuit according to the present invention as described above. SD data is supplied from the input terminal 41, and the SD data is supplied to the area extraction circuits 42, 44 and 49. The area cutout circuit 42 cuts out SD data necessary for the space class from the SD data supplied from the input terminal 41. In this example, it cuts out five SD data k ₁ to k ₅ located in the vicinity of HD data y ₁ ~y ₄ to create, as shown in FIG. 7, for example.

  The SD data cut out by the area cutout circuit 42 is supplied to an ADRC (Adaptive Dynamic Range Coding) circuit 43. For the purpose of patterning the level distribution of the supplied SD data, the ADRC circuit 43 performs an operation such as compressing the data in each region from, for example, 8-bit SD data to 2-bit SD data. As a result, the formed pattern compression data is supplied to the class code generation circuit 46.

The area cutout circuit 44 cuts out SD data necessary for the motion class. In this example, for example, 10 pieces of SD data m _{1 to} m ₅ and n _{1 to} n ₅ existing at positions shown in FIG. 8 are cut out from the HD data y _{1 to} y ₄ to be created from the supplied SD data. .

  The SD data cut out by the area cutout circuit 44 is supplied to the motion class determination circuit 45. The motion class determination circuit 45 calculates a difference between frames of the supplied SD data, and calculates a motion parameter that is an index of motion by thresholding the average value of the absolute values. Specifically, the motion class determination circuit 45 calculates the average value param of the absolute value of the difference of the supplied SD data by the following equation (2).

ただし、図７の画素配置では、ｎ＝５である。

However, in the pixel arrangement of FIG. 7, n = 5.

  The motion parameter is, for example, four motion classes. That is, when the average value param ≦ 2 of the SD data difference is determined, the motion class mv-class is determined as 0, and when the average value param ≦ 4, the motion class mv-class is determined as 1 and the average value is determined. When param ≦ 8, the motion class mv-class is determined to be 2, and when the average value param> 8, the motion class mv-class is determined to be 3. The motion class mv-class determined in this way is supplied to the class code generation circuit 46.

  The class code generation circuit 46 detects the class to which the block belongs by performing the following expression (3) based on the space class from the ADRC circuit 43 and the motion class mv-class from the motion class determination circuit 45. Then, a class code class indicating the class is supplied to the coefficient memory 47. This class code class indicates an address read from the coefficient memory 47.

この例では、ｎ＝５、ｐ＝２である。

In this example, n = 5 and p = 2.

The coefficient memory 47 stores, for each class, coefficient data for calculating HD data corresponding to SD data using a linear estimation equation by learning the relationship between the SD data pattern and HD data. Yes. From the coefficient memory 47, w _i (class) which is coefficient data of the class is read from the address indicated by the class code class. The coefficient data is supplied to the estimation calculation circuit 48.

On the other hand, the SD data is also supplied to the area cutout circuit 49. Area extracting circuit 49 cuts out the 25 SD data x ₁ ~x ₂₅ to be used for estimation operation in the SD data to a position as shown in FIG. The output signal of the region cutout circuit 49 is supplied to the estimation calculation circuit 48. The estimation calculation circuit 48 calculates HD data corresponding to the input SD data based on the SD data from the region cutout circuit 49 and the coefficient data from the coefficient memory 47. An example for the calculation is shown in Equation (4). The calculated HD data is output from the output terminal 50.

HD = w ₁ x ₁ + w ₂ x ₂ +... + W ₂₅ x ₂₅ (4)

  The present invention is not limited to the above-described embodiment of the present invention, and various modifications and applications are possible without departing from the spirit of the present invention.

1 is a circuit diagram showing one embodiment of a product-sum operation circuit of the present invention. FIG. 4 is a table showing an embodiment of an address degeneration memory according to the present invention. 4 is a table showing an embodiment of an address degeneration memory according to the present invention. It is a circuit diagram which shows the other Example of the product-sum operation circuit of this invention. 1 is a circuit diagram showing an embodiment of an address degeneration operation circuit according to the present invention. FIG. It is a block diagram which shows an example of the signal converter which can apply this invention. It is a basic diagram for demonstrating area extraction. It is a basic diagram for demonstrating area extraction. It is a basic diagram for demonstrating area extraction. It is a circuit diagram which shows the conventional product-sum operation circuit. It is a circuit diagram which shows the conventional signal interpolation circuit.

Explanation of symbols

1 Multiplicand Memory 2 Multiply and Accumulator 3 Address Control Circuit 4 Address Degeneration Memory 5 Multiplier Memory

Claims (2)

In a product-sum operation circuit in which a digital filter operation is performed with M taps by adding a product of a multiplier and a multiplicand,
An input means for inputting a digital signal;
Represented by the third number of bits comprised by the second number of bits representing the degree of the input the digital signal first bit number and spatial direction of the waveform around the target pixel representing the degree of motion of the pixel of interest When the value represented by the first number of bits is equal to the threshold value , the L bit class code of the S bit represented by the fourth number of bits that is smaller than the third number of bits If the value expressed by the first bit number is different from the threshold value after being converted into a class code, the value expressed by the second bit number is degenerated to ½, and the first bit Conversion means for converting the number and the second number of bits reduced to ½ into the S-bit class code represented by the fourth number of bits ;
Multiplier data reading means for reading M multiplier data corresponding to the address from the multiplier memory using the S-bit class code as an address;
A product-sum operation circuit having operation means for generating a product-sum output of the M multiplier data read from the multiplier memory and the M multiplicand data. In a product-sum operation circuit in which a digital filter operation is performed with M taps by adding a product of a multiplier and a multiplicand,
An input means for inputting a digital signal;
Represented by the third number of bits comprised by the second number of bits representing the degree of the input the digital signal first bit number and spatial direction of the waveform around the target pixel representing the degree of motion of the pixel of interest When the value expressed by the first bit number is equal to the first threshold value, the L-bit class code is expressed by a fourth bit number that is smaller than the third bit number. When converted to an S-bit class code and the value represented by the first number of bits is equal to a second threshold value that is greater than the first threshold value, represented by the second number of bits The value is reduced to ½ and converted from the first bit number and the second bit number reduced to ½ to the S-bit class code represented by the fourth bit number. The value represented by the number of bits of 1 is the second value. When the third threshold value is greater than the threshold value, the value expressed by the second bit number is reduced to ¼, and the first bit number and the second value reduced to ¼. Conversion means for converting from the number of bits to the S-bit class code represented by the fourth number of bits ,
Multiplier data reading means for reading M multiplier data corresponding to the address from the multiplier memory using the S-bit class code as an address;
A product-sum operation circuit having operation means for generating a product-sum output of the M multiplier data read from the multiplier memory and the M multiplicand data.

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