JP2006014446A - Monitor apparatus and power conversion apparatus using this - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a monitor apparatus which can reduce sharply the number of memories for storing historical data and to provide a power conversion apparatus using this. <P>SOLUTION: The monitor apparatus includes a means for receiving a plurality of first status signals and second status signals which are inputted into time series from an apparatus to be monitored, a first storage means for storing the first status signals as first historical data of predetermined time period by predetermined sampling time, a detecting means for detecting a level after that level of the second status signal of the above change, and a second storage for storing as the predetermined time period second historical data together with a time information when the second status signal of the changes level after the above variation. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a monitoring device and a power conversion device using the same, and more particularly to a monitoring device with an improved history data storage method and a power conversion device using the same.

  Among electrical devices used in a plant, for example, a power conversion device such as an electric motor control device is connected to a storage unit provided in a monitoring device that monitors the power conversion device in order to perform failure analysis of the device. State information was stored as history data. When a device failure occurs, the cause of the failure is identified by referring to history data temporally prior to the failure occurrence time stored in the storage unit. For this purpose, a so-called traceback function that reproduces history data is added to the equipment, and the time transition of the data of each related part before the failure occurs, or the data of each related part after the failure occurs in addition to this. The trend was displayed (for example, see Non-Patent Document 1).

  For example, the failure trend display of a conventional motor control device used in an iron or paper plant is as follows.

  The motor control device includes a converter / inverter that converts commercial power into an arbitrary voltage and frequency, and a control circuit that controls the converter / inverter. This control circuit normally receives an external command from a higher-level driving operation or monitoring process controller and controls the motor speed or torque to a desired value. In this control, a signal such as an electric motor voltage, current or speed is used as a feedback signal.

  In addition, the motor control device has a monitoring device with a traceback function, and the sequence signal and feedback signal such as the above-mentioned external command or the state signals such as voltage and current of each part in the motor control device are output at a constant sampling interval. Thus, the history data is stored in the internal memory for a predetermined time. When a failure occurs, the history data stored in the internal memory is reproduced and displayed as trend information.

In this conventional system, analog data including digital data such as a gate signal of a converter / inverter in an electric motor control device is handled.
Nakamura, Abe, Miyazaki “Plant drive device with advanced intelligent technology”, Toshiba Review Vol55No7, July 1, 2000, P29

  In the traceback function described above, particularly for gate-related signals, high-speed sampling is required, and all data is recorded at a certain sampling time, so that more data sampling than necessary is performed. For this reason, there has been a problem that the memory capacity of the storage unit of the monitoring device becomes enormous.

  For example, in the case of a motor control device having a three-level converter / inverter according to the conventional method, the memory capacity used for the gate signal is 48 gates (a value obtained by multiplying the gate reference and gate control signal by the number of power devices). When sampling at 1 μs for 100 ms, it becomes 480 kbytes, and considering this for 4 banks (a bank means a trace for one failure), this is four times 1920 kbytes.

  On the other hand, other analog status signals have 16 bits of AD converted data, a sampling period of about 1 ms, 0.6 ms for 300 ms, 50 signals, and 8 banks. Even when the memory capacity was calculated, it was at most 240 kbytes.

  Therefore, the memory capacity of the storage unit is mostly the gate signal history data, the memory capacity is unreasonably large, and the time to create the trend data for display by collecting the traceback data has been long.

  The present invention has been made in view of the above, and provides a monitoring device capable of significantly reducing the number of memories for storing historical data by rationally compressing a gate signal and a power conversion device using the same. The purpose is to do.

  In order to achieve the above object, the monitoring apparatus according to the first aspect of the present invention includes a means for receiving a plurality of first state signals and second state signals input in time series from the monitored device; First storage means for storing the first state signal as first history data for a predetermined time at a predetermined sampling time, and detecting that the level of the second state signal has changed and the level after the change. And a second storage unit that stores the level after the change as second history data for a predetermined time together with time information when the second state signal changes. .

  A power conversion device according to a second aspect of the present invention includes a converter / inverter that converts alternating current or direct current into another frequency or voltage, control means for controlling the converter / inverter, and monitoring the converter / inverter. A monitoring device configured to receive a plurality of first status signals and second status signals input in time series from the control means; and the first status signal. First storage means for storing first history data for a predetermined time at a predetermined sampling time, detection means for detecting that the level of the second state signal has changed, and a level after the change, and after the change And a second storage means for storing a predetermined time as second history data together with time information when the second state signal changes. That.

  According to the present invention, since the amount of history data is reduced by compressing the gate signal, it is possible to provide a monitoring device that greatly reduces the number of memories for storing history data and a power conversion device using the same. It becomes.

  Embodiments of the present invention will be described below with reference to FIGS.

  FIG. 1 is a block diagram of a monitoring device and a power conversion device using the same according to the present invention. The electric motor control device 1 is a power conversion device that drives an AC electric motor 2 by converting a commercial power source into an arbitrary voltage and frequency. The motor control device 1 includes a converter / inverter 3 constituting a main circuit for power conversion, a control circuit 4 for controlling the output voltage and frequency of the converter / inverter 3, and a monitoring device 5.

  The control circuit 4 receives each command such as an operation command, a speed command, and a torque command from the process controller 9 for monitoring the operation of the plant, performs gate control of a switching element (not shown) of the converter / inverter 3, and an AC motor 2 speed or torque is controlled. In order to perform this control, the control circuit 4 is supplied with various signals such as a speed feedback signal (not shown) of the AC motor 2 and a voltage signal and a current signal from the converter / inverter 3. A gate reference signal to be supplied to each switching element of the inverter 3 is obtained from the gate reference circuit 41, and this gate reference signal is amplified by the gate control circuit 42 and supplied to the gate of each switching element of the converter / inverter 3. The control circuit 4 is configured to output a failure signal to the monitoring device 5 when detecting an abnormal value of a state signal such as a speed feedback signal, a voltage signal from the converter / inverter 3, or a current signal.

  The monitoring device 5 includes an input / output circuit 6, a processor 7, a storage unit 8, and a state transition determination circuit 9. The input / output unit 6 also has a function of performing input / output processing between the control circuit 3 and the external process controller 9 and the monitoring device 5 and converting an analog signal into a digital signal.

  From the control circuit 4, in addition to the failure signal, the history signal recording status signal 1 and status signal 2 are input to the input / output circuit 6 and the status transition determination circuit 9 respectively in time series. The status signal 1 is the speed feedback signal described above, the signals from the converter / inverter 3, the operation command obtained from the process controller 9, and the like. These status signals 1 are stored in the history data first memory 81 of the storage unit 8 at every sampling time determined by the data recording processing function of the processor 7. The state signal 2 is a gate reference signal and a gate control signal, and is input to the state transition determination circuit 9 in time series.

  When the history data first memory 81 and the history data second memory 82 are filled with the written history data, the processor 7 overwrites the next history data with the oldest history data. I do. Accordingly, history data for a certain time is always stored in the history data first memory 81 and the history data second memory 82. In this way, when the monitoring device 5 receives a failure signal, the history data before and after the failure can be reproduced.

  FIG. 2 is a block diagram showing an example of the state transition determination circuit.

  In FIG. 2, among the status signals 2, for example, a positive gate reference signal from the gate control reference circuit 41 is used as a first D-type flip-flop circuit 91 and a second D-type flip-flop circuit 92 connected in series. Give to the input. The data recording gate signal that is the output of the first D-type flip-flop circuit 91 and the output signal of the second D-type flip-flop circuit 92 are input to the EXOR circuit 93, and a gate state transition trigger signal is output as the output. can get. At the timing of this state transition trigger signal, the processor 7 reads the logical value of the data recording gate signal and writes it into the history data second memory 82. The clock circuit 71 in the processor 71 measures the time information of the timing when the state transition trigger signal is obtained, and associates this time data with the logical value of the data recording gate signal in the history data second memory 82. Write.

  The above operation will be described below with reference to FIG. FIG. 3 is a time chart for explaining a gate signal recording operation using the triangular wave carrier comparison method.

  In FIG. 3, time t0 is the time when the triangular wave carrier crosses the voltage reference. At this time, the gate reference rises from level 0 to level 1 and maintains level 1 until time t2 when the triangular wave carrier again crosses the voltage reference. Similarly, the gate reference repeats level 0 and level 1 based on the magnitude relationship between the triangular wave carrier and the voltage reference.

  At time t1, the state transition trigger rises by the operation of the EXOR circuit 93, and as described above, the level 1 of the data recording gate signal corresponding to the gate reference point A at time t1 is the second memory for history data in FIG. Is written to. Similarly, at time t2, level 0 of the data recording gate signal corresponding to point B is written in the second history data memory shown in FIG.

  Using the same circuit, history data is also recorded for the negative gate reference signal and the positive and negative gate control signals.

  The data compression effect according to the present invention described above will be considered below. For example, if the gate trace function is 1 μs sampling, data storage for 100 ms, and the total number of gate reference signals and gate control signals is 48, the data amount in the conventional system for 4 banks is 1920 kbytes as described above. .

  When the present invention is used under the same conditions, the following occurs. That is, when the carrier comparison method is used, signal transition occurs in the gate output signal at the number of times synchronized with the carrier frequency. Therefore, when the triangular wave carrier is set to 500 Hz, the state transition occurs once in 1 ms. Therefore, only 100 transitions per gate occur in 100 ms. Therefore, when the time data is 32-bit data, the data amount of one bank is data amount × recording count = (10 bytes + 4 bytes) × 100 × 80≈100 kbytes, which is a significant reduction in memory capacity compared to the conventional method. become.

  Next, the display trend data creation function of the processor 7 will be described.

  As described above, the history data corresponding to the state signal 1 is stored in the history data first memory 81, for example, with a sampling period of 1 ms. Further, the history data second memory 82 stores the level at that time and the time information at that time each time the level changes as level information of the state signal 2. The latter history data, for example, has a sampling time as short as 1 μS. However, data writing is not performed if there is no level transition, so that the history data is an interval corresponding to the frequency of the state signal 2.

  When a failure signal is given in the above state or when a data reproduction request is made, the time data stored in the history data second memory 82 is used for history data in order to edit the history data into trend data. It is necessary to match the time of the history data stored in the first memory 81. This is relatively easy if the initial time of the history data stored in the history data first memory 81 is stored, and the traceback data of the status signal 1 and the status signal 2 are on the same time axis. It can be edited to trend data. If the trend data is transmitted to the process controller 10, for example, the trend data can be displayed outside.

  Note that such a trend data editing function is not necessarily provided in the processor 7, and the above-described time data adjustment may be performed on the process controller 10 side, for example.

In the above description, the state signal 2 is assumed to transition at two levels, but it may be a signal having more levels.

The block block diagram of the monitoring apparatus which concerns on this invention, and a power converter device using the same. The block block diagram which shows an example of a state transition determination circuit. The time chart explaining the recording operation of the gate signal using a triangular wave carrier comparison system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Motor control device 2 AC motor 3 Converter / inverter 4 Control circuit 5 Monitoring device 6 Input / output unit 7 Processor 8 Storage unit 9 State transition judgment circuit 41 Gate reference circuit 42 Gate control circuit 71 Clock circuit 81 First memory 82 for history data Second memory 91 for history data, 92 D-type flip-flop 93 EXOR circuit

Claims (5)

Means for receiving a plurality of first status signals and second status signals input in time series from the monitored device;
First storage means for storing the first state signal as first history data for a predetermined time at a predetermined sampling time;
Detecting means for detecting that the level of the second state signal has changed and the level after the change;
And a second storage means for storing the changed level as second history data for a predetermined time together with time information when the second state signal changes.   2. The monitoring according to claim 1, further comprising means for generating display trend data by reproducing the first and second history data after a predetermined time has elapsed after receiving a failure signal from the device to be monitored. apparatus. The detection means includes
A first D-type flip-flop;
A second D-type flip-flop having the output of the first D-type flip-flop as an input;
An EXOR circuit that receives the output of the second D-type flip-flop and the output of the first D-type flip-flop as inputs,
2. The monitoring apparatus according to claim 1, wherein when the output of the EXOR circuit becomes 1, the output of the first D-type flip-flop is detected. The monitored device is a power converter,
The monitoring apparatus according to claim 1, wherein the second state signal is at least one of a gate reference signal and a gate control signal. A converter / inverter that converts alternating current or direct current into other frequencies or voltages;
Control means for controlling the converter / inverter;
A monitoring device for monitoring the converter / inverter,
The monitoring device
Means for receiving a plurality of first state signals and second state signals input in time series from the control means;
First storage means for storing the first state signal as first history data for a predetermined time at a predetermined sampling time;
Detecting means for detecting that the level of the second state signal has changed and the level after the change;
A power converter comprising: second storage means for storing the changed level as second history data for a predetermined time together with time information when the second state signal changes.

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