JP2000354381A - Failure monitor for power converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce memory capacity for monitoring by decreasing the number of operations of a microcomputer and to shorten the tracking time of the failure factor of a switching element significantly by reproducing an analog monitor signal accurately upon occurrence of a failure. SOLUTION: The failure monitor for power converter comprises a clock generator 7 generating a pulse of constant period, a time counter 10 generating a time data when the edge of a gate pulse is detected, a monitor memory 13 for storing an analog monitor signal when the edge is detected along with the detection time thereof, an address counter 12 managing an address for linking each data with each time data when a monitor signal is reproduced, and a microcomputer 14 for controlling these operations. Varying point of the gate pulse, a failure detection signal and an abnormal pattern of the gate pulse are then detected and a data comprising the detection time data and an analog monitor signal of the DC input current, voltage or output current of a power converter is stored sequentially in the memory as a monitor data only for predetermined intervals and the monitor data is reproduced upon occurrence of a failure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power converter failure monitoring device for monitoring a failure of a power converter that converts DC to AC or AC to DC.

[0002]

2. Description of the Related Art A power converter using a plurality of switching elements is provided with a failure monitoring device for monitoring the state of an analog monitor signal such as a gate pulse or a current or voltage value of the element for failure analysis of the element. I have.

[0003] A conventional fault monitoring device is disclosed in Japanese Unexamined Patent Publication No. 9-289.
As described in Japanese Patent No. 780, there is a fault monitoring device that samples a gate pulse at high speed (several μs) and, when a change is detected, stores the data of the gate pulse at the time of detection and the detection time together in a monitor memory. As for the analog monitor signal other than the gate pulse (analog signal such as the DC input current or voltage or output current of the power converter), as shown in FIG.
After A / D conversion with a period trigger of about 50 μs, it is stored in the monitor memory. When a failure occurs, the monitor data is transferred from the failure monitor to the personal computer, and the gate pulse and the analog monitor signal are graphically displayed to confirm the operation at the time of the failure and to analyze the cause.

However, when monitor data of the gate pulse and data of the analog monitor signal are sampled at different scales and timings, when the monitor display is performed on the same screen, a change in the analog monitor signal is observed when the gate pulse is abnormal. Since the phenomenon at the time of occurrence of the failure is not accurately displayed, it may take time to determine the cause of the destruction of the switching element and take countermeasures.

Further, as a device for recording a waveform of an analog signal or the like, as described in JP-A-57-33363,
Some devices record waveforms with high-speed sampling when the signal changes.However, if sampling is performed asynchronously with the gate pulse, an unnecessary normal waveform is also recorded, or if the sampling of the monitor shifts when the gate pulse is abnormal, In some cases, a necessary change in the analog monitor signal cannot be reliably recorded.

[0006]

Under normal conditions, the change in the analog signal is very small compared to the change in the gate pulse, and the amount of monitor data after A / D conversion is 8 bits per operation.
As described above, if all the analog monitor signals are stored as they are in the same manner as the gate pulse, the capacity of the monitor memory increases. When synchronized only with the gate pulse,
If there is no change in the gate pulse, the analog signal will not be monitored.

SUMMARY OF THE INVENTION An object of the present invention is to sample the analog monitor signal synchronized with a gate pulse at the time of an abnormality so that only a large amount of analog monitor signal data necessary for failure analysis can be monitored. To reduce the time required for

[0008]

In the normal state, the analog monitor signal is sampled at a constant period (about 250 μs) in the same manner as in the prior art, and when an abnormality is detected (a change in the abnormality detection signal from other than the failure monitor device or a gate pulse). (Abnormal pattern detection) is analyzed by monitoring every change of the gate pulse.

According to the present invention, since the monitor data is collected in a concentrated manner at the time of an abnormality, the change of the analog monitor signal at the time of the abnormality required for the failure analysis becomes accurate, and the time required for tracing the cause of the failure and taking measures is reduced. be able to.

[0010]

FIG. 1 shows an embodiment of the present invention.
1 shows a failure monitoring device for a power converter (inverter) that drives an AC induction motor. The target power converter is
It may be a static inverter (SIV) or a converter that converts AC to DC.

In FIG. 1, in the case of a three-phase power converter, two switching elements (switching elements such as IGBTs) 4 connected in series between DC power supplies 6 are divided into three phases, and a switching element 4 for each phase is provided. Are connected to the AC induction motor 5 serving as a load. The PWM modulation signal output from the PWM generator 2 of each switching element 4 is input to the gate drive 3, and the gate pulse signal from the gate drive 3 is applied to the gate of the switching element 4. An analog monitor signal such as a gate pulse signal and an output current (or voltage) of a power converter and a failure detection signal are input to the failure monitor device 1 of the present embodiment. In FIG. 1, for convenience, only a failure monitoring device for one switching element is described, but it goes without saying that the monitoring is performed for all elements.

Next, details of the failure monitoring device 1 will be described. FIG. 2 is a block diagram of hardware of the failure monitoring device 1.

In FIG. 2, 7 is a clock generator, 8 is a circuit for detecting a change point of a gate pulse and a feedback pulse, 9 is a circuit for detecting an abnormal pattern of a gate pulse and a feedback pulse, 10 is a free-run timer, and 11 is A
/ D converter, 12 an address counter, 13 a monitor data storage memory, 14 a microcomputer, 15
Indicates a page register. Thick lines indicate address buses and data buses, and thin lines indicate control signal lines. The monitor data storage memory 12 includes an area (page) written by hardware and an area (page) written by software as shown in FIG. In FIG. 3, pages 1 to 7 are shown as areas to be written by hardware, and the first to seventh hard data are written for each page 1. Here, the time data analog data is written to the address of each page. Also, page 8 is shown as an area to be written by software, and this page contains the first to seventh failure software data. The respective failure software data includes an address counter value of hardware data at the time of failure occurrence, and failure occurrence time data. Write.

Next, the operation will be described. The microcomputer 14 sets a page (page address) for writing monitor data in the monitor memory 13 in the page register 15 and then outputs a monitor start signal. On the other hand, from the clock generator 7, a period sufficiently shorter than the gate pulse width for detecting an edge (in this example, the switching frequency of the IGBT is several kHz and the clock frequency is 1.25 MHz)
z. ) Is output.

First, when there is no failure detection signal, the pulse trigger is not output, and the address counter 12 is periodically operated by the timer trigger output from the timer 10, and the A / D conversion is performed to the address (page register value + address counter value). The output of the device 11 and the time data (relative time) output by the timer 10 at that time are stored as shown in FIG. If there is no failure detection thereafter, this operation is repeated,
Previously written data is overwritten.

Next, if there is a failure detection signal or an abnormal pattern of a gate pulse, when a transition point of the gate pulse is detected by the transition point detection 8, if there is an abnormal pattern detection 9 or an external failure detection signal, a pulse trigger is generated. Is output and the address counter 12 is activated at each change point of the gate pulse.
(Page register value + address counter value) A /
The output of the D converter 11 and the time data (relative time) output by the timer 10 at that time are stored as shown in FIG.

When the microcomputer 14 receives the failure detection signal, it first stores the management data shown in FIG. 3, that is, the address counter value of the hardware data at the time of failure occurrence, and the failure occurrence time data, and then starts monitoring within a predetermined time. Stop the signal output and stop updating the current data of hardware and software. Then, after the value of the page register 15 is incremented and the page of the monitor memory 13 stored by the hardware is switched to page 2 (second hard data) and the software writing area is switched to the second failure software data, Start monitoring again. Similarly, when a failure is detected, the value of the page register 15 is incremented, and the pages of the monitor memory 13 where the hardware sequentially stores the monitor data are changed to pages 3 to 7 (the third to seventh hard data). After switching, and after switching the software writing area to the third to seventh failed software data,
Start monitoring again.

FIG. 4 shows an example of a monitoring result when a gate failure occurs due to the occurrence of a failure during monitoring of the two gate pulses 1 and 2 and the analog signal. When the abnormality detection signal is output, a pulse trigger is output at each change point of the gate pulse at that time, and an analog monitor signal at the time of abnormality is intensively collected in the monitor memory in synchronization with the gate pulse.

As described above, the failure monitor device of the present embodiment accurately reproduces the analog monitor signal, and simultaneously generates the failure detection signal, the time when the monitor signal is abnormal, and the observation result of the analog monitor signal. Can quickly determine what happened and then take appropriate action.

[0020]

According to the present invention, a change in an analog signal synchronized with a gate pulse can be monitored, so that when a gate breakage accident occurs, a detailed analog signal state at the time of abnormality can be confirmed. The cause pursuit time is greatly reduced. In addition, by minimum sampling,
The number of operations of the microcomputer can be reduced, the monitor memory capacity can be reduced, and an economical system configuration can be achieved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a failure monitoring device for a power converter (inverter) according to an embodiment of the present invention.

FIG. 2 is a hardware block diagram of a failure monitoring device according to the present invention.

FIG. 3 is a diagram showing a structure of monitor data of the fault monitoring device of the present invention.

FIG. 4 is a diagram showing an example of a monitor signal by the fault monitoring device of the present invention.

FIG. 5 is a diagram showing an example of an analog monitor signal by a conventional fault monitoring device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Fault monitoring device, 2 ... PWM generation part, 3 ... Gate drive, 4 ... Switching element, 7 ... Clock generator,
8 ... change point detection circuit, 9 ... abnormal pattern detection circuit, 10
... Timer, 11 A / D converter, 12 Address counter, 13 Monitor memory, 14 Microcomputer, 15 Page register.

Claims (2)

[Claims] A power converter for driving a plurality of switching elements by a predetermined gate pulse detects a change point of a gate pulse, a failure detection signal and an abnormal pattern of the gate pulse, and detects time data and power at that time. Data consisting of an analog monitor signal such as a DC input current or a voltage or an output current of the converter is sequentially stored in a memory as a monitor data only for a predetermined section, and the monitor data is reproduced when a failure occurs. Power converter failure monitoring device. 2. A power converter for driving a plurality of switching elements by a predetermined gate pulse, a clock generator for outputting a pulse having a constant period, and detecting a change point of the gate pulse based on the timing of the clock. , A circuit for detecting an abnormal pattern of a gate pulse, a time counter for generating time data upon detection of a pulse trigger by a failure detection signal, and analog monitor signal data and time data when the circuit detects a pulse trigger. A fault monitoring device for a power converter, comprising: a monitor memory for storing an address, an address counter for managing an address for linking analog monitor data and time data at the time of monitor reproduction, and a microcomputer for controlling these operations.