JPH0773000B2 - Sample hold circuit - Google Patents

Description

The present invention relates to a circuit for sampling and holding a peak value of an input signal which changes in a burst shape, and particularly to a sample suitable for a signal level detecting circuit such as a TDMA wave. Hold circuit

[Conventional technology]

Conventionally, as shown in FIG. 3, a sample and hold circuit of this type has a sample and hold unit composed of an analog switch 2, a capacitor 3 and an amplifier 4, and a comparator 6 for driving the analog switch 2 in response to the rising edge of an input signal. The delay circuit 8 and the monostable multivibrator 9 are included.

[Problems to be Solved by the Invention]

In the circuit shown in FIG. 3, as shown in the signal waveform in FIG. 4, the sampling pulse only performs sampling once per burst. Therefore, there is a drawback that the response when the level of the burst signal fluctuates while continuing is impossible and the accurate peak value cannot be held. In particular, in the case of a signal with a gentle rising edge, the sample is held in a state in which the input signal has not risen sufficiently even after the elapse of the constant delay time t _d by the delay circuit 8, and an accurate peak value is obtained. There was a drawback that could not be obtained.

Therefore, the technical problem of the present invention is to provide a sample hold circuit which can detect the change and hold an accurate peak value even if the burst signals change in the same frame.

[Means for Solving the Problems]

The present invention is characterized in that a circuit for comparing the sampled and held output signal with the current input signal and a gate circuit for generating a sampling pulse again according to the output of the comparison circuit are provided.

[Action]

According to the present invention, even when the burst signal level changes in the same frame, or even when the input signal rises gently, when the subsequent input signal becomes larger than the value sampled and held previously, the signal from the comparison circuit is output. Is output,
This output operates to hold the new signal level by closing the analog switch again through the gate circuit.

〔Example〕

FIG. 1 is a diagram showing an embodiment of the present invention. Similar to FIG. 3, an analog switch 2 for sampling an input signal, a capacitor 3 for holding a sampled signal voltage, a buffer amplifier 4 having a high input impedance. The first comparator 6 for detecting the rising edge of the input signal, the reference voltage source 7 for giving the reference voltage of the comparator 6, the delay circuit 8 set in anticipation of the rising time of the input signal, and the sample pulse by the output of the delay circuit 8 And a monostable multivibrator 9 that is generated. In this embodiment, in addition to such a configuration, the output of the second comparator 10 is passed only when the second comparator 10 for comparing the input signal level and the sample hold output level and the first comparator 6 are in operation. AND gate 11, output of first comparator 6 and AND gate 11
There is provided an OR gate 12 that takes the logical sum of the output and the AND gate 13 that can output the sample pulse only while the first comparator is operating.

FIG. 2 is a time chart showing the timing of the input / output signals and the sampling pulse of the present invention, and t _d and t _s respectively show the operating time of the delay circuit 8 and the monostable multivibrator 9 in FIG.

The operation of this embodiment will be described with reference to FIGS. 1 and 2.
When the input signal applied to the input terminal 1 rises and rises to the voltage value set by the reference voltage source 7, the first comparator 6 outputs a signal and after the delay time t _{d determined} by the delay circuit 8, the monostable multivibrator. The analog switch 2 is opened by the sample width t _s determined by 9 and the capacitor 3 is charged. The output of the capacitor 3 is amplified by the amplifier 4, and the output terminal 5
Is output to the outside through. The output of the amplifier 4 is also compared with the input signal by a second comparator 10,
If the input signal level is higher, the delay circuit 8 and the monostable multivibrator 9 are driven through the AND gate 11 and the OR gate 12, and the input signal is sampled and held again. Here, the AND gates 11 and 13 enable sampling again only while the first comparator 6 is operating.

As is apparent from FIG. 2, the input signal is sampled and held by the time t _s of the first sampling pulse after the delay time t _d after the rising. Furthermore, when the input signal is increasing, the sampling pulse is output again.

This operation is repeated while the input signal is increasing, and as a result, the peak value per burst can be accurately detected.

〔The invention's effect〕

As described above, the present invention adds the circuit for generating the sample pulse by comparing the input signal and the output signal, so that the peak value is sampled and held corresponding to the signal level change after the rising edge of the input signal. It becomes possible to detect an accurate peak value.

Further, even when the rising edge of the input signal is gentle, an accurate peak value can be detected by similarly performing sampling operations a plurality of times.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a signal waveform diagram of each part of FIG. 1, FIG. 3 is a block diagram of a conventional example, and FIG. 4 is a signal waveform diagram of each part of FIG. . In the figure, 1 is an input terminal, 5 is an output terminal, and 7 is a reference voltage source.

Claims (1)

[Claims] 1. A sample hold circuit for generating a sampling pulse using a monostable multivibrator at the output of a comparator that detects the rising edge of an input signal that changes in burst form, and driving an analog switch to charge a capacitor, A sample and hold circuit comprising: a circuit for comparing a sampled and held output signal with a current input signal; and a gate circuit for generating a sampling pulse again according to the output of the comparison circuit.