JPH1028382A - Method for detecting at output stage of inverter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect the current of an inverter, while suppressing the cost increase in a circuit system and, at the same time, maintaining the system in a small size by calculating the phase current values of other two phases, based on the processed results of a sample hold circuit, A/D conversion circuit, etc., which process the phase current value of one phase at prescribed timing. SOLUTION: Resistors 7C and 7V are respectively connected to U- and V- phases and detect the quantities of currents flowing to transistors 5U and 5V or feedback diodes 6U and 6V. The detected analog quantities of the currents are sent to a sample hold circuit 10b and further to a register circuit 10d, through an A/D converter 10c and stored in a memory 10e. Of the U-, V-, and W-phase currents, the U- and V-phase currents are alternately detected, and when the U-phase current is detected, the V-phase current is subjected to approximate calculation. When on the contrary the V-phase current is detected, the U-phase current is subjected to approximate calculation. A three-phase bridge circuit 2 finds the phase current of W-phase from a relation between the current values of the three phases such that the sum of the current values becomes zero.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for detecting a current output from an inverter or a servo amplifier (both are collectively referred to as an "inverter" in the present specification). A modulation inverter, that is, a voltage-type PWM (Pulse Width M)
The present invention relates to a method for detecting a three-phase current of an inverter.

[0002]

2. Description of the Related Art The prior art will be described with reference to FIGS. FIG. 6 shows a circuit for detecting the current of the three-phase fundamental wave, and FIG. 7 shows the principle of detecting the current of the three-phase fundamental wave.

As a method for detecting a three-phase current of an inverter, there are known two methods as shown in FIG. One method is to use current transformers 14U and 14V
This is a method of detecting a current by using. Another method is to detect a passing current by arranging a current transformer in the upper stage and / or the lower stage (or both) of the output transistor, or to detect the current by detecting the current flowing through the resistors 13U and 13V. How to

In these detection methods, any one of the peak points (peaks or valleys) 22 and 2 of the carrier wave shown in FIG.
2. . . Of the upper (or lower) transistor 1
The current 23 is detected at the timing when the current 21 shown in FIG. 7 (2) flows through 1U, 11V or the feedback diodes 12U, 12V (FIG. 6). Current 2
3, the instantaneous value 25 of the fundamental wave component of the current necessary for, for example, vector control of the three-phase motor is selected from the output current 24 of the inverter including many harmonic components.
Can be obtained.

[0005] When performing vector operation control, at least two phase currents among the three phase currents must be detected at the same time, which is a problem of the prior art. That is, the A / D incorporated in the microcomputer (microcomputer) 15 indicated by a virtual line in FIG.
(Analog / digital) conversion circuit system (15a, 15
b, 15c, 15d) incorporate only one sample and hold circuit 15b and one A / D conversion circuit 15c, despite the large number of input channels.

[0006] Only one circuit is incorporated.
The A / D conversion circuit requires a large number of elements, so providing a plurality of circuits increases the cost of the microcomputer itself. Second, the area occupied by the microcomputer increases according to the number of elements. This is to avoid an increase in physical dimensions. For this reason, generally, in FIG.
A microcomputer is provided with a multiplexer circuit indicated by a, and a plurality of analog data input by the microcomputer is sequentially output to a subsequent sample and hold circuit 15b based on a selection control signal.

Therefore, the two-phase currents described above are not output to the A / D conversion circuit 15c at the same time but output with a time lag. Could not be used for. Therefore, conventionally, a sample hold circuit and an A / D conversion circuit system are separately provided outside the microcomputer to process a plurality of analog data. However, such a method not only increases the cost of the circuit system, but also goes against the downsizing.

[0008]

SUMMARY OF THE INVENTION The technical problem to be solved by the present invention is to solve the above-mentioned problems, and to reduce the cost of the circuit system and to reduce the inverter current while keeping it small. To provide a method capable of detecting the

[0009]

In order to solve the above-mentioned technical problems, the inventor of the present invention uses a single sample-and-hold circuit, an A / D conversion circuit and the like to change a single-phase current value at a predetermined timing. Then, based on the result, it was found that the other two-phase current values not processed at this time should be calculated, and the following configuration was adopted.

That is, the first aspect of the present invention provides a voltage-type three-phase (U-phase, V-phase, and W-phase) composed of at least six pairs of upper and lower transistors and a feedback diode connected in antiparallel with the transistors. A) a current detection method in an output stage of a pulse width modulation inverter, wherein any two phases (for example,
When a resistor or a current transformer for detecting a current flowing through the transistor or the feedback diode connected to the U-phase and the V-phase is connected to the two phases (U-phase and V-phase), and the transistor is in an ON state. The two phases (U
, V-phase) are sampled and held in accordance with a predetermined order, the sampled and held detection values are A / D exchanged, written into a register, stored in a memory, and stored in a memory. The phase current value of the other phase (for example, V phase) of the (U phase, V phase) that was not detected at the time of the peak is one of the values of the other phase current stored in the memory. Approximate calculation is performed from two values (one of the previously detected V-phase currents), and the phase current value of the undetected phase (W-phase) other than the two-phase is calculated as the three-phase value. Is calculated from a relationship in which the sum of the respective phase currents flowing through is zero.

Here, "any two phases in either the upper stage or the lower stage" means that either the upper stage or the lower stage is selected (here, the lower stage is selected). Any two phases (here, U phase and V phase are selected) arbitrarily selected from the selected lower three phases (U phase, V phase, W phase). V selected instead
A phase and a W phase, and a U phase and a W phase are also applicable. Further, a similar selection may be made in the upper stage instead of the lower stage.

Here, "detection in accordance with a predetermined order" means that, when the U-phase and the V-phase are selected as in the above example, for example, the U-phase and the V-phase are alternately detected. It means that those current values are detected alternately in accordance with it. The “predetermined order” is not limited to “alternate”, but may be any regular one. As such an order, for example, the current value of the U-phase is detected twice consecutively, the V-phase is detected once, and then the U-phase is detected once, and then the V-phase is detected.
It is determined that the phase is detected twice, and this is repeated. In addition, "approximation calculation" in this specification
This method will be described in detail in the section of the embodiment of the invention.

A second aspect of the present invention adopts, in addition to the configuration of the first aspect, a configuration in which the two-phase currents (U-phase and V-phase) are alternately detected.

According to a third aspect of the present invention, there is provided a voltage-type three-phase (U-phase, V-phase, W-phase) pulse composed of at least six sets of upper and lower transistors and a feedback diode connected in antiparallel with the transistors. A current detection method in an output stage of a width modulation inverter, wherein a current flowing through a transistor or a feedback diode connected to a three-phase (U-phase, V-phase, or W-phase) in one of an upper stage and a lower stage is detected. To the three phases (U-phase, V-phase, W-phase), and the three-phase at the peak of any one of the peaks and valleys of the carrier wave when the transistor is on. (U-phase, V-phase, W-phase) phase currents are sampled and held for each phase according to a predetermined sequence, and the sampled and held detected values are A / D exchanged. Stored in a memory after writing in the register Te, the three phases (U phase, V phase, W phase) other two phases is not detected during the peak of the (eg, V-phase, W-
The current value of the phase) is calculated by an approximate calculation from any two values of the current values of the other two phases (V phase and W phase) stored in the memory.

According to a fourth aspect of the present invention, there is provided a method for detecting a current in an output stage of a voltage-type three-phase pulse width modulation inverter comprising at least six pairs of upper and lower transistors and a feedback diode connected in antiparallel with the transistors. Wherein a resistor or a current transformer for detecting a current flowing through the transistor or the feedback diode connected to the three phases of either the upper stage or the lower stage is connected to the three phases, and the transistor is connected to the three phases. Sample values of the phase currents of the three phases at the peak of any one of the peaks and valleys of the carrier wave in the ON state are sampled and held one by one according to a predetermined order, and the detected values obtained by the sample and hold are sampled and held. A / D exchange, write to register, store in memory, and detect at the peak of the three phases The current values of the other two phases that did not exist are approximated by the value of one phase current of the other two phases from any two of the values of the one phase current stored in the memory. A configuration is employed in which each of the other two phases is calculated by calculation, and the value of the other phase current is calculated from the relationship in which the sum of the phase currents flowing through the three phases becomes zero.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows a detection circuit for detecting a three-phase fundamental current, FIG. 2 shows a principle of three-phase fundamental current detection, and FIG. 3 shows a simulation of an error in three-phase fundamental current detection.

As shown in FIG. 1, the output stage 1 of the inverter
Is provided with a three-phase bridge circuit 2, through which three-phase alternating current (U-phase, V-phase, W-phase) is output to the load 20. The three-phase bridge circuit 2 basically includes transistors 3U, 3V, 3W and 5U, 5V, 5W, which are main switching elements, and feedback diodes 4U, 4V, 4W and 6U, 6V, 6W connected in anti-parallel. Have been. Resistors 7U and 7V are inserted into the U and V phases, respectively, so that the amount of current flowing through the transistors 5U and 5V or the feedback diodes 6U and 6V can be detected by the method already described in the section of the prior art. It has become.

The analog current amount detected in this way is sent to a sample-and-hold circuit 10b via an analog multiplexer 10a incorporated in the microcomputer 10, and the current analog amount is selected from the U-phase or V-phase selected by the former. Is held by the latter. Further, the analog current amount is converted into a digital amount by the A / D converter 10c, sent to the register circuit 10d, and stored in the memory 10e.

Next, the principle of detecting the three-phase basic current in this embodiment will be described with reference to FIG. As already described in the section of the prior art, by detecting the current at the timing when the current flows through the lower (or upper) transistor or the feedback diode among the peak points (peaks or valleys) of the carrier wave, the high frequency is detected. It is well known that an instantaneous value of a fundamental component of a required current can be obtained from an inverter output current containing many components.

Here, in order to perform vector operation control or the like, it is necessary to detect current values of any two phases out of three phases at the same time, and how the general-purpose microcomputer processes this detection. Is explained. In FIG. 2A, reference numeral 15 denotes a sine curve indicating a current fundamental wave component of the U phase, and n-3, n-2, n-1, n, n + 1, n +.
The current values at 2, n + 3 represent the phase current 23 at the peak point (peak or valley) 22 (FIG. 7A) of the carrier.

In this case, n-3, n-1, n +
1 and n + 3 are measured values of the U-phase current, and n
The values at −2, n, and n + 3 are theoretical values of the U-phase current. As understood from this, in the present embodiment, out of the three phases of the U phase, the V phase, and the W phase, the U phase and the V phase are selected as current detection targets, and as a result, the W phase is not detected. The target, that is, the calculation target. Then, the U-phase current and the V-phase current are detected alternately, and when the U-phase current is detected, V-phase current is detected.
The phase is not detected and is subjected to the approximate calculation. Conversely, if the V phase is detected, the U phase is not detected and the approximate calculation is performed.

Next, a method for performing an approximate calculation will be described with reference to FIGS. 2 (2) and 2 (3). Fig. 2 (2)
2 is a partially enlarged view of FIG. 2 (1), and FIG. 2 (3) is a view showing a relationship between an actually measured value and a calculated value of each phase current. FIG.
In (2), iUn-3 and iUn-1 are n-3 and n
-1 shows the measured values of the U-phase current, respectively.
iUn and iUn _- 2 are approximate calculated values of the U-phase current at n and n-2 (the current value of the V-phase is detected at this time)
Are respectively shown.

The current value thus measured is stored in the memory 10e (FIG. 1) as described above. In FIGS. 2 (2) and 2 (3), 〇 indicates an actually measured value, ● indicates a calculated value, and × indicates a true value, that is, a theoretical value (Sin
(Value of Θ).

Here, regarding the method of performing the approximate calculation, i
This will be described more specifically by taking Un (an approximate calculated value of the U-phase current at n) as an example. iUn is already measured and stored in memory 1
0e (iUn-3, iUn-1
) Is obtained from the following equation (Equation 1).

[0025]

## EQU1 ## iUn = iUn-1 + (iUn-1-iUn-
3) / 2

Similarly, iUn + 2, which is the U-phase current at n + 2, is obtained by the following equation (Equation 2).
The same applies to the case where the V-phase current value is calculated by the approximate calculation.

[0027]

## EQU2 ## iUn + 2 = iUn + 1 + (iUn + 1-iUn-
1) / 2

As described above, two of the three phases (U phase, V phase)
The current value of the phase (phase) has been obtained. Next, a method of obtaining the phase current of the undetected phase (W phase) will be described.
In this method, in the three-phase bridge circuit 2 as shown in FIG. 1, the sum of the current values flowing through the respective phases is zero (iU + iV + iW).
= 0). That is, since iU and iV among the three-phase current values have already been obtained, i
W is obtained by calculating the value of-(iU + iV). Similarly, when iU is selected as the undetected phase instead of iW,-(iV
+ IW), and when iW is selected,-(iU + iV).

As described above, the above-described method always requires any two current values actually measured. For this reason, as shown in FIG. 2C, in the case of iUn-2 and iVn-1, there is no actual measurement value, and therefore these values cannot be approximated. This means that the current values of the three phases cannot be obtained unless at least two actually measured values are provided (after the time point n). The period from the start of detection to the provision of at least two measured values is a very small period and can be ignored and does not hinder practical use.
3, n-1). By doing so, the period can be minimized, so that control can be started earlier. In addition, when performing an approximate calculation, such a latest value (n−
By adopting (3, n-1), the approximation accuracy can be further improved.

Next, the result of simulating the detection error of the three-phase fundamental current in the present embodiment will be described with reference to FIG. This result indicates that the sampling rate is 1
In the case of 80 times / cycle, a portion where the error is maximum (a portion where the curvature is maximum) in one cycle waveform of the fundamental wave current is shown. As is evident from the table of FIG. 3, the maximum error is only 0.18%, and such an error does not cause any problem in performing the control.
It can be understood that this detection method has sufficient practicality.

Next, another embodiment will be described with reference to FIGS. FIG. 4 shows a circuit for detecting a three-phase fundamental current according to the present embodiment, and FIG. 5 shows the principle of the detection. Note that, in the present embodiment, the same components as those in the previous embodiment are denoted by the same names and reference numerals, and description thereof is omitted.

The present embodiment differs from the previous embodiment in the following two points. First, in the above embodiment, the resistor (current transformer) is connected to only any two phases, so that it is connected to all three phases so that the current values of all phases can be detected. Is different from the present embodiment. Secondly, in the above embodiment, the current value of one of the two phases is approximated by detecting the current value of the other, and the remaining phase is calculated from the relationship with the previous two phases. This is different from the present embodiment in which the current value of any one phase is detected and the current values of the other two phases are obtained by approximate calculation.

In FIG. 5, reference numeral 16 denotes a sine curve indicating the current fundamental wave component of the U-phase as in the previous embodiment, and n-5, n-4,..., N,. n + 3, n
The current value at +4 represents the phase current 23 at the peak point (peak or valley) 22 (FIG. 7A) of the carrier. In the present embodiment, since the order of U, V, W is adopted as the predetermined order, n-4, n-
Assuming that the values at 1 and n + 2 are the measured values of the U-phase current, n-3, n and n + 3 are the theoretical values of the U-phase, and the V-phase at this time is the object to be measured. Also, n-5,
The values at n−2, n + 1 and n + 4 are also theoretical values of the U phase, and the W phase at this time is an object to be measured.

As described above, since the phase current of the U phase is detected at n + 2, the current values of the V phase and the W phase are not detected at this time, and the current values in the previous embodiment are different. Similarly, it can be obtained from the two latest measured values already detected. That is, the V-phase current value is approximately calculated based on the detection results at n and n-3, and the W-phase current value is approximately calculated based on the detection results at n + 1 and n-2. This can be expressed by the following mathematical expression (Equation 3).

[0035]

IUn + 2 = actual value iVn + 2 = iVn + 2 (iVn-iVn-3) / 3 iWn + 2 = iWn + 1 + (iWn + 1-iWn-2) / 3

Although the above description has been made on the case where the U-phase current is detected, it goes without saying that the same applies to the case of the V-phase current and the case of the W-phase current.

Finally, a modification of the above-described other embodiment will be described. This embodiment is different from the other embodiments in the following points. That is, in the other embodiments, in the other two-phase current values that were not detected, the two-phase current values that were not detected were calculated by approximation calculation from any two values. One phase current value is calculated by approximation calculation from any two values of one phase current value stored in the memory 10e, and the other phase current value is calculated for each phase current flowing through the three phases. Is different from the present embodiment, which is obtained by calculating from the relationship in which the sum of is zero. Since the method of the approximate calculation and the relationship where the sum of the respective phase currents is zero have already been described, only the mathematical formula is shown below (Equation 4), and the description of other detailed contents will be omitted.

## EQU4 ## iUn + 2 = actual value iVn + 2 = iVn + 2 (iVn-iVn-3) / 3 iWn + 2 =-(iUn + 2 + iVn + 2)

[0038]

According to the present invention, there is no need to provide an A / D conversion circuit system such as a sample-and-hold circuit outside the microcomputer, and only a single sample-and-hold circuit incorporated in the microcomputer simultaneously. An instantaneous value of the fundamental wave component of each of the three-phase currents can be obtained. Since it is not necessary to increase the number of components in this way, it is possible to detect the inverter current while keeping the circuit system small while suppressing the cost of the microcomputer.

[Brief description of the drawings]

FIG. 1 is a diagram showing a detection circuit for detecting a fundamental current according to an embodiment of the present invention.

FIG. 2 is a diagram and a chart showing the principle of three-phase fundamental current detection.

FIG. 3 is a table showing a simulation of an error in three-phase fundamental wave current detection.

FIG. 4 is a diagram showing a circuit for detecting a three-phase fundamental current according to another embodiment.

FIG. 5 is a diagram showing a principle of detecting a three-phase fundamental current according to another embodiment.

FIG. 6 is a diagram showing a conventional circuit for detecting a current of a three-phase fundamental wave.

FIG. 7 is a diagram showing a principle of detecting a current of a conventional three-phase fundamental wave.

[Explanation of symbols]

 1 Inverter output stage 2 Three-phase bridge circuit 3U transistor 3V transistor 3W transistor 4U feedback diode 4V feedback diode 4W feedback diode 5U transistor 5V transistor 5W transistor 6U feedback diode 6V feedback diode 6W feedback diode 7U resistor 7V resistor 9 load 10 10a Analog multiplexer 10b Sample hold circuit 10c A / D converter 10d Register circuit 10e Memory

Claims (4)

[Claims] 1. A method for detecting current in an output stage of a voltage type three-phase pulse width modulation inverter comprising at least six sets of upper and lower transistors and a feedback diode connected in anti-parallel with said transistors. When a resistor or a current transformer for detecting the current flowing through the transistor or the feedback diode connected to any one of the two phases in one of the lower stages is connected to the two phases, and the transistor is turned on. Sample-and-hold each value obtained by detecting the phase current of the two phases at the peak of either the peak or the valley of the carrier wave according to a predetermined order, and A / D-exchange the sampled and held detection value into a register. After writing, it is stored in memory, and the value of the other phase current of the two phases that was not detected at the peak Calculate by approximation calculation from any two values of the other phase current values stored in the memory, and calculate the phase current values of the undetected phases other than the two phases for each of the three phases. A current detection method in an output stage of an inverter, wherein the current is calculated from a relationship in which a sum of phase currents becomes zero. 2. The current detection method in an output stage of an inverter according to claim 1, wherein the two phase currents are alternately detected. 3. A current detection method in an output stage of a voltage type three-phase pulse width modulation inverter comprising at least six pairs of upper and lower transistors and a feedback diode connected in anti-parallel with said transistors. A resistor or a current transformer for detecting a current flowing through the transistor or the feedback diode connected to the three phases of any one of the lower stages is connected to the three phases, and the carrier wave when the transistor is in an ON state Sample-and-hold values obtained by detecting the phase currents of the three phases one by one in accordance with a predetermined order at the peak of any one of the peaks or valleys, and A / D exchange the sampled and held detection values. After writing to the register, store it in the memory, and among the three phases, the other two phases not detected at the peak A current value, the current detection in the output stage of the inverter and calculating the approximate calculation from each one of two values of the current values of the other two phases are stored in the memory. 4. A current detection method in an output stage of a voltage-type three-phase pulse width modulation inverter comprising at least six pairs of upper and lower transistors and a feedback diode connected in anti-parallel with said transistors. A resistor or a current transformer for detecting a current flowing through the transistor or the feedback diode connected to the three phases of any one of the lower stages is connected to the three phases, and the carrier wave when the transistor is in an ON state Sample-and-hold values obtained by detecting the phase currents of the three phases one by one in accordance with a predetermined order at the peak of any one of the peaks or valleys, and A / D exchange the sampled and held detection values. After writing to the register, store it in the memory, and among the three phases, the other two phases not detected at the peak Each current value is calculated by approximation calculation of one phase current value of the other two phases from any two values of the one phase current value stored in the memory. Wherein the value of the other phase current of the two phases is obtained by calculating from the relationship that the sum of the respective phase currents flowing through the three phases becomes zero.