JPH03230767A - Phase current detector in three-phase pwm inverter device - Google Patents

Abstract

PURPOSE:To detect a phase current surely by lengthening the maintenance time of the switching mode corresponding to any basic voltage vector other than zero vector than the sum of the dead time of an inverter main circuit and the time required for current detection. CONSTITUTION:A control cycle deciding means 16 decides the control cycle TSW in a three-phase PWM signal generating circuit 4, receiving a phase command value theta* and a voltage command value V*. When the maintenance time of the switching mode corresponding to any basic voltage vector other than zero vector, which is determined according to the phase command value theta*and the voltage command value V*, is longer than the sum of the dead time of a main inverter main circuit and the time required for the current detection by a hole CT9, a certain short control cycle TSW is selected, and when the maintenance time of the switching mode becomes shorter, the control cycle TSW is lengthened so that the maintenance time may be longer. Hereby, the current of each phase can be detected with one current detection means, and phase current can be detected surely.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a phase current detection device for detecting phase current in a three-phase PWM inverter device.

(Prior Art) In recent years, three-phase PWM inverter devices having the following configuration have been provided. 6 configuring the inverter main circuit
Six types of basic voltage vectors with phases different by π/3 are made to correspond to meaningful combinations of switching modes that can be taken by each switching element, and a zero vector is added to these. Then, the switching state of each switching element in the inverter main circuit is combined with a required switching mode among six switching modes corresponding to basic voltage vectors whose phases differ from each other by π/3 and switching modes corresponding to a zero vector. The time ratio control is performed every predetermined control period. As a result, the inverter main circuit supplies a sine wave output to the load with a rotating voltage vector.

In this case, in order to measure the phase current of each phase flowing from the inverter device to the load, it has conventionally been common to provide current detectors for two or three phases.

(Problem to be solved by the invention) However, since the current detector used in this type of inverter device needs to have excellent frequency characteristics, such as a Hall CT, it is necessary to use two or three current detectors. A configuration that requires a device has a large cost disadvantage.

Furthermore, in order to use only one current detector, it is conceivable to provide this on the DC bus side. However, with this configuration, it may become impossible to detect the current in each phase depending on the output voltage or phase. The reason is that when the output voltage is low, the zero vector ratio increases and the holding time of the switching mode corresponding to the basic voltage vector to which the voltage is actually applied becomes shorter, so the time required for current detection cannot be ensured, and if the output voltage vector has a phase close to the six types of basic voltage vectors, the holding time of the switching mode corresponding to the basic voltage vector that is far away in phase from the output voltage vector becomes shorter. This is because it becomes impossible to secure the time necessary for current detection.

The present invention has been made in view of the above circumstances.

Therefore, the object is to provide a phase current detection device for a three-phase PWM inverter device that can detect the current of each phase with one current detection means and can always detect the phase current reliably regardless of the output voltage or phase. It is in.

[Configuration of the Invention (Means for Solving the Problems) The phase current detection device of the present invention detects the switching state of each switching element in the inverter main circuit by 6 f-1
The switching mode from the inverter main circuit to the load is controlled by combining the required switching modes among the switching modes corresponding to basic voltage vectors having phases different from each other by π/3 and the switching modes corresponding to the zero vector. PWM designed to provide a sinusoidal output
In an inverter device for detecting phase current thereof, the inverter main circuit includes current detection means for detecting a current flowing in a DC bus of the inverter main circuit, and the inverter main circuit when a current is detected by the current detection means. A phase determination means is provided for determining which phase current value the detected current value corresponds to based on the switching mode of the current value, and the holding time of the switching mode corresponding to any basic voltage vector other than the zero vector is provided. The present invention is characterized in that it is configured to be longer than the sum of the dead time of the inverter main circuit and the time required for current detection by the current detection means.

(Function) According to the above-mentioned means, the currents of all phases can be detected by providing one current detecting means on the DC bus, so the number of current detecting means can be kept to a minimum. Moreover, the holding time in switching mode is always set to be longer than the sum of the dead time of the inverter main circuit and the time required for current detection by the current detection means, so current detection is possible no matter what voltage or phase. You can secure the time you need.

(Example) An example of the present invention will be described below with reference to the drawings.

First, the schematic configuration of the inverter main circuit in the three-phase PWM inverter device to which the present invention is applied is, as shown in FIG.
This is a well-known configuration in which 3v, 3w, 3x, 3y=32 are bridge-connected. Here, since either one of the upper and lower switching elements of each arm is turned on, there are 23-8 switching modes. Therefore, if we consider the phase difference of each phase to the output voltage of the inverter and imagine a voltage vector that is given an instantaneous vector expression corresponding to each switching mode, these will be mutually π as shown by the solid line in Figure 2. 6 types of basic voltage vectors and 2 types of zero vectors (
0,0,0), (11,1). Here, eight types of vectors (Sa, Sb, Sc)
corresponds to eight switching modes, and Sa when the positive side switching elements 3u, 3v, and 3w of each phase are on.

Sb and Sc are expressed as "1", and conversely, when the negative side switching elements 3x, 3y, and 3z are on, it is expressed as rOJ.

The three-phase PWM signal generating means 4 for controlling the switching state of each switching element generates three-phase PWM signals according to a so-called instantaneous magnetic flux control method. The instantaneous magnetic flux control method mentioned here is, for example,
``Technical Considerations for Improving Control Characteristics'' announced at the Tokai Branch Federation of Electrical Associations in 1986 or Patent Application 1986-224
No. 889 “Three-phase PWM signal generation circuit for inverter device”
This refers to the technology detailed in, etc. To explain this roughly,
The switching state of each switching element in the inverter main circuit is changed to a required switching mode among the switching mode corresponding to the basic voltage vector whose phase is different from each other by π/3 and the switching mode corresponding to the zero vector at a predetermined control period of 15 w. By performing time ratio control in which the required holding times are combined, a voltage vector of arbitrary magnitude and phase can be output. For example, to output a basic voltage vector (1, 0, 0) and a voltage vector between (1, 1, 0) that corresponds to the phase command value θ1 and the voltage command value V8,
Basic voltage vector (1,0,0), same (1,1,0)
and the holding time of each switching mode corresponding to the zero vector is 1. ．． 12°1o, the phase command value θ is obvious from the geometrical analysis shown in Figure 3.
Since the advance angle of the phase command value θ6 in the region to which 8 belongs is θ, the time ratio tl:t2:t that satisfies the following equation (1)
. is set.

1, :12 :1o error V"・Tsw-sin((yr/fi)-θ)
:V'・T 5w-5+nl(yr/B)
+θ) :T5W-V”・Tsw・[5jnl
(π/6)-θ)+5inl(π/6)10)] ...... (1) Three-phase PWM signal SU generated in this way.

Sv and Sw are input to the dead time generation circuit 5 and
Each switching signal B l for each switching element:
, B v, B w, B x, B v, B z
is generated. This dead time generating circuit 5 has a three-phase P
This is to generate switching signals for each switching element from the WM signal so that the upper and lower switching elements of each arm of the inverter main circuit are not turned on at the same time. ), it is configured to include a delay circuit 6, an AND gate 7, and an inverter gate 8. Figure 5 shows the voltage waveform diagram of each part. When the three-phase PWM signal Su shown in Figure 5 (a) is applied to the input side, the voltage waveforms shown in Figure 5 (B) and (C) are shown. Switching signals BU, Bx are generated.

tad shown in the figure corresponds to dead time.

Now, in order to detect the phase current of this inverter device, as shown in FIG. 1, one hole CT9 serving as current detection means is provided on the DC bus 2 of the inverter main circuit.

The detected current value 1dc from the Hall CT 9 is manually inputted to a phase determining circuit 10 which is a phase determining means for determining which phase current value the current value corresponds to. The information for judgment in this phase judgment circuit 10 is the detected current value ld. is the switching mode at the moment when the voltage vector (switching mode) and the DC bus 1,
The fact that the phase of the current flowing in the phase 2 corresponds to that shown in FIG. 6 is utilized for the determination. In addition, in the same figure, l,...
, lv, and 1w indicate the U-phase, ■-phase, and W-phase currents in order, and those with a negative sign indicate the defined direction of the current (see Figure 1).
means that it flows in the opposite direction. For example, if the switching element corresponds to the basic voltage vector (1, 0, 0), the switching elements 3u, 3 of the inverter main circuit
y, 3z are in the on state, switching elements 3v, 3
Since w and 3x are in the off state, the current flowing through the DC bus 1.2 at the moment of the switching mode is the U-phase current io. If two phases of the output current of 3 III can be determined, the remaining one phase can be calculated from the condition that the total current is zero, and therefore, the gold phase current can be detected every control cycle. In addition, the phase voltages Vu, Vv, Vw
The relationship between the current detection value 1dc and the current detection value 1dc is as shown in FIG.

The specific configuration of this phase opening/disconnecting circuit 10 is as shown in FIG. Delay time TDL of the delay circuit 11 shown in the figure
is the dead time t set in the inverter main circuit
dd and the switching time tow of the switching element or more (TDL > t 77 +t, .). A logic circuit composed of three inverters 12 and six AND gates 13 is the main part that determines which phase current value the detected current value 1de corresponds to, and is compatible with each switching mode. Based on the combination of the three-phase PWM signals Su, Sv, and SW, a signal is output from one of the eight-power terminals of each AND gate 13, and one of the six switches 15 is selected via the monostable multivibrator 14. is turned on. The signal line from the Hall CT 9 is connected to all of these switches 15, and six types of phase currents 1u, iVi, -i are output from each switch 15. , 'ly, I
The detected value of w is output.

Now, 16 shown in FIG. 1 is a control cycle determining means, which determines the control cycle T5W in the three-phase PWM signal generating circuit 4 in response to the phase command value θ8 and the voltage command value v8. Specifically, the control cycle determining means 16 includes a ROM that tabulates various control cycles corresponding to each phase command value θ1 and voltage command value V1, and determines the given phase command value θ and voltage command value. Control period T according to each part of v1
, W are read out and applied to the three-phase PWM signal generating means 4.

The control period Tsw determined here changes in length depending on the phase command value θ8 and voltage command value ■1, and is set to any one other than the zero vector determined according to the phase command value θ1 and voltage command value V8. The holding time of the switching mode corresponding to the fundamental voltage vector ([1 or j 2 )
j)' When the dead time jad of the inverter main circuit and the time tIf required for current detection by the Hall CT9 are longer than the sum, a certain short control period T5w is selected, and the holding time of the switching mode is the above-mentioned time (t
dd+tmy), the control period Tsw is lengthened so that it becomes longer than the holding time (Cda+t1.). Cases in which the holding time or time (L ad+ j , -) of any switching mode is shorter include cases where the output voltage is low and cases where the output voltage vector has a phase close to the six basic voltage vectors. Therefore, the region in which the output voltage vector like this exists is, for example, the same CI as the basic voltage vector (1,0°0).
, 1.0), it falls within the shaded area in FIG. That is, the control period determining means 16 determines from the phase command value θ1 and the voltage command value ■1 that the normal short control period TsW is used when outputting a voltage vector outside the shaded area in FIG. When selecting and outputting a voltage vector within the shaded area in Figure 8, select the basic voltage with the shorter holding time or shorter of the two basic voltage vectors for outputting that voltage vector. The control period Tsw is lengthened so that it is longer than the holding time of the switching mode corresponding to the vector or the time (t aa+t , , ).

In this case, if switching control is performed to output two types of basic voltage vectors once each when outputting a voltage vector with a phase different from the basic voltage vector, the time will be twice as long as the shorter holding time t1. (tad j sw). That is, the control period Tsw needs to be made long so as to satisfy the following equation (2).

2 V”・T 5w-5inl(yr/e)-
〇)>taa+i−−・・・・・・(2) Regarding the other fundamental voltage vector, in order to reduce the harmonic components included in the output voltage of the inverter, the zero vector is sandwiched in the middle and output. Therefore, the control periods T and W must satisfy the following equation (3).

■1 ・Tsw'SIn huge π/6) 10)> i
aa + t ay ...... (3) According to the above configuration, the currents of all phases can be detected by one hole CT9 provided in the DC bus 2, so the number of hole CT9s can be minimized, Manufacturing costs can be reduced. Moreover, depending on the phase command value θ1 and voltage command value vl+, the holding time of the switching motor is the dead time tdd of the inverter main circuit and the time t required for current detection by the Hall CT9.
If the control period TsW is likely to be shorter than the sum of The current can be reliably detected even in the case of

In the above embodiment, the control period TSW is lengthened in some areas according to the phase command value θ1 and the voltage command value v8, but the holding time of the switching mode is changed over time (while keeping the control period T5w constant). It is also possible to make it longer than tdd+t-). This is done by forcibly outputting a voltage vector outside that area when the command value of the voltage vector falls within the shaded area in Figure 8, and the subsequent switching mode is set within that area. It suffices to use something that corrects the external voltage vector.

In addition, the present invention is not limited to the embodiments described above and shown in the drawings, but can be implemented with various changes within the scope of the invention.

[Effects of the Invention] As described above, the present invention has the excellent effect of being able to detect the current of each phase with one current detection means, and also being able to always reliably detect the phase current regardless of the output voltage or phase. play.

[Brief explanation of drawings]

The drawings show one embodiment of the present invention, and FIG. 1 is a block diagram of the main parts together with the main circuit of an inverter device, FIG. 2 is a diagram showing basic voltage vectors, and FIG. 3 is a diagram showing phases in a certain region. Figure 4 is a block diagram showing the dead time generation circuit; Figure 5 is a waveform diagram of the circuit; Figure 6 is a correspondence diagram between basic voltage vectors and phase currents;
The figure shows the relationship between each phase voltage and the phase current, FIG. 8 is a block diagram showing the phase judgment circuit, and FIG. 9 is a vector diagram showing the region in which the control cycle is lengthened. In the drawing, 12 is a DC bus, 3u, 3v, 3w3x, 3y
, 3z is a switching element, 4 is a three-phase PWM signal generation means, 5 is a dead time generation circuit, 9 is a Hall CT (current detection means), 10 is a phase-specific cutoff circuit (continuation judgment means), and 16 is a control period determination means. It is.

Claims (1)

[Claims] 1. The switching state of each switching element in the inverter main circuit is combined with a required switching mode among six switching modes corresponding to basic voltage vectors whose phases differ from each other by π/3 and switching modes corresponding to a zero vector. In the three-phase PWM inverter device, the inverter main circuit supplies a sine wave output to the load by controlling the time ratio,
The device for detecting each phase current includes a current detection means for detecting the current flowing in the DC bus of the inverter main circuit, and a switching mode of the inverter main circuit when the current is detected by the current detection means. A phase determination means is provided to determine which phase current value the current value detected at that time corresponds to, and the holding time of the switching mode corresponding to any basic voltage vector other than the zero vector is the dead time of the inverter main circuit. A phase current detection device in a three-phase PWM inverter device, characterized in that the phase current detection device is configured to be longer than the sum of the time required for current detection by the current detection means.