JP2005102349A - Current detector - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a current detector capable of precisely detecting a phase current at a low cost, in an inverter device for PWM driving. <P>SOLUTION: A multi-phase inverter comprises three arms of two switching elements (Q1 and Q2, Q3 and Q4, Q5 and Q6) connected in series, and the three arms are connected in parallel to a DC power supply 1. Each switching element is PWM-driven by a switching signal generating means 13. A sampling means 6 generates a sampling signal PA in synchronous with such timing as all switching elements on lower side are on states. A phase current detecting means receives inputting of the PA signal and calculates phase current signals (PIU, PIV, PIW) from the voltage detected from the output terminal of the multi-phase inverter (a voltage occurring at on-resistance). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a device for detecting an output current of a PWM inverter, and is mainly used for a motor drive device.

  In recent years, PWM inverters are mainly used to increase efficiency in inverters that drive motors. In addition, in order to drive the motor stably and with high efficiency, it is necessary to prevent overcurrent and to match the phase of the back electromotive force and current of the motor. For this reason, motor current information is indispensable. It becomes.

  As a conventional technique for obtaining this current information, a method is well known in which a shunt resistor is inserted in a DC circuit section and the voltage drop is used as current information. As an example, Patent Document 1 discloses a method in which a voltage between shunt resistors is sampled and held by a switching mode of an inverter unit, and the voltage value is used as phase current information. Although this method can detect the phase current of the motor without requiring a special current sensor, the cost can be reduced. However, there is a problem that a loss is caused by the shunt resistor and the overall efficiency is lowered.

  As another conventional technique for obtaining current information, a shunt resistor as described above is not used, but a field effect transistor is used for each arm constituting the inverter to detect its on-resistance. There is a method to use. As an example, the technique is disclosed in Patent Document 2, and will be described with reference to FIG.

  In FIG. 18, six field effect transistors (hereinafter referred to as FETs) Q <b> 11 to Q <b> 16 are connected to a full bridge and connected to a DC power source 101. Each phase of the stator winding of the brushless motor 102 is connected to a connection point (U, V, W) between the upper arm and the lower arm of the FET. The drive circuit 103 controls the rotation of the brushless motor 102 by turning on and off the gates of the FETs (Q11 to Q16) based on the signal of the rotor position detection circuit 104 that detects the rotor position of the brushless motor 102.

  Here, the current detection circuit 107 is configured to detect the voltage at the connection point (U, V, W) and control the gate terminal of the lower arm FET (Q12, Q14, Q16). The current detection circuit 107 has a comparator (not shown). When the voltage at the connection point (U, V, W) becomes higher than a certain value, the output of the comparator becomes “L”. The lower arm FETs (Q12, Q14, Q16) are forcibly turned off.

That is, when the current flowing through each FET becomes larger than a certain value, the voltage drop due to the on-resistance of the FET becomes large, and the operation is performed to detect this and cut off the current. In other words, the on-resistance of the FET is used to provide an overcurrent protection function. Therefore, the current detected by the current detection circuit 107 can be understood only from the magnitude relationship. In addition, this method has the advantage of not using a shunt resistor that causes a reduction in efficiency as described above. However, switching is not performed at a high frequency and the driving is performed with an electrical angle of less than 120 °. It has the problem of being limited.
JP 2-197295 A JP-A 64-8897

  However, the above conventional techniques have the following problems. First, in the method using a shunt resistor, a loss due to the shunt resistor is generated, leading to a decrease in efficiency, and the current to be detected is switched according to the conduction state of the upper and lower switching elements of the inverter. The occurrence of a continuous part. Specifically, for example, in an inverter that drives a three-phase motor, the current that can be detected by the shunt resistor when the upper side of the U phase, the lower side of the V phase, and the lower side of the W phase are in a conductive state, It is limited to an electrical angle of less than 120 ° flowing into Similarly, in other switching states, a current having an electrical angle of less than 120 ° for each phase can be detected. If these detection currents are combined, the current of all electrical angles can be detected theoretically.

  However, in actuality, for example, in an information apparatus driving motor represented by an optical disk motor, relatively high frequency switching (20 to 100 kHz) is performed, and further, a switching noise is removed to detect a current. The detectable section in one switching state is significantly below 120 °. Therefore, even if the respective detected currents are combined, only a current waveform including a discontinuous portion can be obtained.

  Next, in the method for detecting the on-resistance of the FET, if one of the upper and lower switching elements of all three phases is always in a conductive state such as 180 ° energization, the switching state is switched in a short time. It is affected and cannot detect stable current. That is, in order to detect a stable current by this method, the driving is substantially limited to energization driving with an electrical angle of less than 120 ° or driving without high-frequency switching.

  An object of the present invention is to provide a current detection device that can detect a phase current of a motor only by a switching state of a lower or upper FET without using a sensor or a shunt resistor.

  The current detection device of the present invention includes a multi-phase inverter in which an arm composed of two switching elements connected in series is connected to a DC power supply in parallel with the number of output phases, and a switching signal generation for PWM driving the switching elements. Sampling means for outputting a sampling signal in synchronization with the timing when all of the lower or upper switching elements in the multiphase inverter are turned on, and the sampling based on the voltage detected from the output terminal of the multiphase inverter Phase current detection means for calculating a phase current signal in synchronization with the signal.

  As described above, according to the current detection device of the present invention, in the PWM driven inverter, the phase current of the motor can be detected only by the switching state of the lower or upper switching element without using a sensor or a shunt resistor. Therefore, it is possible to realize cost reduction without causing a loss and an increase in the number of parts. Moreover, there is no discontinuous part in the current detection, and the entire section can be detected, and it can be applied to energization exceeding 120 ° electrical angle and high-frequency switching. Furthermore, by adding a current detector as an auxiliary, variation in on-resistance of the switching element can be removed, and more accurate current detection can be realized.

Hereinafter, the current detection device of the present invention will be described in detail according to a preferred embodiment with reference to the drawings.
(Embodiment 1)
FIG. 1 is a circuit diagram showing Embodiment 1 of the present invention. In FIG. 1, Q1 to Q6 are all field effect transistors (FETs), Q1 and Q2, Q3 and Q4, and Q5 and Q6 are connected in series, respectively. It is connected to the. Here, a U-phase arm is constituted by a series circuit of two FETs Q1 and Q2, a V-phase arm is constituted by a series circuit of two FETs Q3 and Q4, and a series circuit of two FETs Q5 and Q6. Constitutes the W-phase arm. Further, the upper FET is constituted by three FETs Q1, Q3, and Q5, and the lower arm is constituted by three FETs Q2, Q4, and Q6.

  The brushless motor 2 has a U-phase winding LU, a V-phase winding LV, and a W-phase winding LW on its stator, and one end thereof is commonly connected. On the other hand, at the other end of each winding, the connection point U between Q1 and Q2 is the U-phase winding, the connection point V between Q3 and Q4 is the V-phase winding, and the connection point W between Q5 and Q6 is the W-phase winding. It is connected to the. Further, flywheel diodes D1 to D6 are connected in parallel to the respective FETs (Q1 to Q6). The flywheel diodes D1 to D6 can be omitted by using a parasitic diode of each FET.

  The signal wave generating means 4, the carrier wave generating means 5, and the drive signal generating means 3 constitute a switching signal generating means 13. The drive signal generating means 3 receives the signals generated by the signal wave generating means 4 and the carrier wave generating means 5, synthesizes predetermined PWM signals, and forms signals PQ1 to PQ6 at the gates of the FETs (Q1 to Q6). input. Sampling means 6 receives signals PQ 2, PQ 4, and PQ 6 and inputs sampling signal PA to phase current detection means 7. The phase current detection means 7 receives the sampling signal PA and the voltages at points U, V, and W, and outputs PIU, PIV, and PIW as phase current signals.

  FIG. 2 shows a specific circuit diagram of the drive signal generating means 3. Three signals PSU, PSV, and PSW from the signal wave generating means 4 are input to the non-inverting terminals of the comparators 301, 302, and 303, respectively, and compared with the signal PH from the carrier wave generating means 5. The output of this comparator is the drive signals PQ1, PQ3, PQ5 for the upper switching element. At the same time, these signals are inverted by inverter elements 304, 305 and 306, respectively, and PQ2. PQ4 and PQ6.

  FIG. 3 shows a circuit diagram of the sampling means 6. In FIG. 3, PQ2, PQ4, and PQ6, which are driving signals for the lower FET, are input to an AND element 601, and the logical product output P6A is provided with a delay element by a one-shot multivibrator 603, and then an inverter element. It is inverted at 604 to become a signal P6C. The P6C and the signal P6A are input to the AND element 602, and a sampling signal PA which is a logical product is obtained and input to the phase current detection means 7. The one-shot multivibrator 603 can be replaced with a delay element by other means such as an RC delay circuit.

  FIG. 4 shows a circuit diagram of the phase current detection means 7. In FIG. 4, when the above-described sampling signal PA is input, the analog switches AS1, AS2, and AS3 are turned on, and the voltages at the points U, V, and W are sampled and held in the capacitors C1, C2, and C3, respectively. Output as phase current signals PIU, PIV, and PIW.

  Next, the operation of the first embodiment will be described in detail with reference to FIGS. FIG. 5 schematically shows a state in which the drive signal generator 3 generates a PWM signal in response to signals from the signal wave generator 4 and the carrier wave generator 5.

  The signal wave generating means 4 has a D / A conversion circuit inside (not shown), and generates three sinusoidal signal waves PSU, PSV, PSW having a 120 ° phase difference from an externally input digital signal. Generated and input to the drive signal generating means 3. The signal waves PSU, PSV, and PSW are not limited to sinusoidal signals. Similarly, the carrier wave generation means 5 generates a triangular wave PH having a predetermined frequency and inputs it to the drive signal generation means 3.

  The drive signal generating means 3 compares the signal wave PSU and the carrier wave PH, and outputs a signal PQ1 and its inverted signal PQ2. Similarly, the signal wave PSV and the carrier wave PH are compared to output the signal PQ3 and its inverted signal PQ4, and the signal wave PSW and the carrier wave PH are compared to determine the signal PQ5 and its inverted signal PQ6. Output. As a result, the output signals PQ1 to PQ6 of the drive signal generating means 3 become the pulse train shown in FIG. 5 and are supplied to the gates of the FETs (PQ1 to PQ6), and the FETs of Q1 to Q6 are switched and driven. The brushless motor 2 is driven with a predetermined torque.

  As is well known, by changing the amplitudes of the signal waves PSU, PSU, and PSW, the duty of each pulse train of PQ1 to PQ6 changes, and the torque generated by the motor 2 can be changed. At the time when the upper FET and the lower FET are switched, it is necessary to provide an upper and lower FET off period of about several tens to several hundreds ns to prevent a short circuit. However, in order to simplify the description, this short circuit prevention time is omitted. ing.

  The time chart shown in FIG. 6 is obtained by enlarging the time axis of the Ta part in FIG. In FIG. 6, PQ2, PQ4, and PQ6 are driving signals for the lower FET, P6A, P6B, and P6C are the respective signals of the sampling means 6, PA is the output signal of the sampling means 6, PIU, PIV, PIW Is an output signal of the phase current detection means 7. As is apparent from this figure, the sampling signal PA is a pulse signal that rises with a delay time Td delayed from the logical product signal P6A of the input signals PQ2, PQ4, and PQ6.

  Therefore, the sampling means 6 rises with a delay of time Td after all the lower FETs Q2, Q4, Q6 are turned on, and falls when any of the lower FETs Q2, Q4, Q6 is turned off. Is input to the phase current detection means 7. The purpose of providing this delay time Td is that immediately after the upper FET is turned on from the upper FET, the current flowing through the lower FET is also unstable due to the influence of high-frequency switching, etc. This is because the current detection is performed by removing.

  Here, as shown in FIG. 6, the time T1 when the FETs (Q2, Q6) are on and the FET (Q4) is off (that is, Q3 is on) will be considered. In this case, as shown in FIG. 7, the V-phase current IV flows into the motor 2 from the DC power supply 1 through the FET (Q3) and the V point. On the other hand, a U-phase current IU passing through the U point and the FET (Q2) and a W-phase current IW passing through the W point and the FET (Q6) flow out from the motor 2. As is well known, the relationship between these currents is IV = IU + IW.

  On the other hand, an arbitrary time T2 in the output period of the sampling signal PA will be considered. At this time T2, as shown in FIG. 8, the FETs (Q2, Q4, Q6) are on. That is, all the lower FETs are on. Since the FET (Q3) is turned off and the FET (Q4) is turned on, the V-phase current IV flows through the FET (Q4) in the reverse direction. At this point in time, the relationship IV = IU + IW is established as described above. In this case, the on-resistance of FET (Q2) is RQ2, the on-resistance of FET (Q4) is RQ4, and the on-resistance of FET (Q6) is If RQ6, the following relationship is further established.

U point potential = IU x RQ2
V-point potential = -IV x RQ4
W point potential = IW x RQ6

  That is, by observing the potential at the U point, the V point, and the W point, the U phase, V phase, and W phase currents can be measured. As apparent from FIG. 6, when the sampling signal PA is output, PIU, PIV, and PIW are output from the phase current detection means 7 as U-phase, V-phase, and W-phase current signals. Various control of the motor can be executed using the current signal.

(Embodiment 2)
Next, FIG. 9 is a circuit diagram showing Embodiment 2 of the present invention. The difference from the first embodiment is that the input to the sampling means 6 is PQ1, PQ3, PQ5. Therefore, the sampling signal PA is output at the timing when all the upper FETs are turned on. Here, assuming that the voltage of the DC power source 1 is E, the on-resistance of the FET (Q1) is RQ1, the on-resistance of the FET (Q3) is RQ3, and the on-resistance of the FET (Q5) is RQ5, the U when Q1 is on The point potential is
U point potential = E-IU x RQ1
It becomes. Similarly, the V point potential and the W point potential when Q2 and Q3 are on are respectively
V point potential = E-IV x RQ3
W point potential = E-IW x RQ5
It becomes.

  As in the first embodiment, when the sampling signal PA is output, PIU, PIV, and PIW are output as U-phase, V-phase, and W-phase current signals from the phase current detection means 7.

(Embodiment 3)
Next, FIG. 10 is a circuit diagram showing Embodiment 3 of the present invention. In FIG. 10, since the inverter unit, the switching signal generating unit 13, the sampling unit 6, and the phase current detecting unit 7 are all the same as those in the first embodiment, the description thereof is omitted. As in the first embodiment, the voltage at the U point, the V point, and the W point is output to the phase current detection unit 7 as phase current signals PIU, PIV, and PIW, respectively. At this time, if there is a variation in the on-resistances RQ2, RQ4, RQ6 of each FET, this variation is reflected as it is in the phase current signals PIU, PIV, PIW. In the third embodiment, the variation in the on-resistance of the FET is corrected by a current detector (shunt resistor) R0 inserted in the DC power supply.

  A shunt resistor R0 is inserted in series with the DC power source 1, and a voltage signal between both ends thereof is input to the correction information output means 8. As is well known, the following relationship exists between the phase current flowing into the motor and the current IR0 flowing through the shunt resistor.

When Q1, Q4 and Q6 are on ... IR0 = IU
When Q2, Q3 and Q6 are on ... IR0 = IV
When Q2, Q4 and Q5 are ON ... IR0 = IW

  The correction information output means 8 inputs the IR0 information as the correction information PC to the phase current correction means 9. The phase current correction means 9 converts the phase current signals PIU, PIV, and PIW including the FET on-resistance variation into phase currents PJU, PJV, and PJW in which the amplitude of the detected current is corrected using the above relational expression. By using the corrected phase current signal, various types of control of the motor with higher accuracy can be performed. Note that the shunt resistor R0 is not limited to a resistor, and other current detectors such as a CT can also be applied.

(Embodiment 4)
Next, FIG. 11 is a circuit diagram showing Embodiment 4 of the present invention. In FIG. 11, the drive signal generation means 3, the sampling means 6, and the phase current detection means 7 are all the same as those in the first embodiment, and thus the description thereof is omitted. The difference from the first embodiment is that shunt resistors R1, R2, and R3 are inserted in series in each arm of the switching elements connected in series. These shunt resistors R1, R2, and R3 are selected to be accurate and free from variations and have good temperature characteristics. The voltage signals of the shunt resistors R1, R2, and R3 are input to the phase current detection means 7. Since accurate shunt resistors R1, R2, and R3 are used instead of the on-resistance of the FET in the first embodiment, more accurate phase current signals PIU, PIV, and PIW can be obtained.

(Embodiment 5)
Next, FIG. 12 is a circuit diagram showing Embodiment 5 of the present invention. In FIG. 12, since the inverter unit, the switching signal generating unit 13, and the sampling unit 6 are all the same as those in the first embodiment, description thereof is omitted. The difference from the first embodiment is that an amplitude determining unit 10 is provided. The amplitude determining means 10 compares the amplitudes of the signal waves PSU, PSV, and PSW with the amplitude of the carrier wave PH. When the amplitude of the signal wave is smaller, the amplitude determination signals PDU, PDV, and PDW input “H” level signals to the phase current detector 7A. A specific circuit of the phase current detection means 7A is shown in FIG.

  When the sampling signal PA and the U-phase determination signal PDU of the amplitude determination means 10 are input to the AND element 71 and the logical product signal is input to the analog switch AS1, and the amplitude of the signal wave is smaller than the amplitude of the carrier wave, the sampling signal The phase current signal PIU is output in synchronization with. Similarly, when the sampling signal PA and the V-phase determination signal PDV of the amplitude determination means 10 are input to the AND element 72 and the logical product signal is input to the analog switch AS2, the amplitude of the signal wave is smaller than the amplitude of the carrier wave. The phase current signal PIV is output in synchronization with the sampling signal. Similarly, when the sampling signal PA and the W-phase determination signal PDW of the amplitude determination means 10 are input to the AND element 73 and the logical product signal is input to the analog switch AS3, the amplitude of the signal wave is smaller than the amplitude of the carrier wave. The phase current signal PIW is output in synchronization with the sampling signal.

  When the amplitudes of the signal waves PSU, PSV, and PSW are larger than the amplitude of the carrier wave PH, the pulse train as shown in FIG. 5 is not output, and the phase current is the same for the period in which the pulse train is not output. If detection is performed, accurate phase current detection cannot be performed. However, according to the function described here, only when the amplitude of the signal wave is smaller than the amplitude of the carrier wave and the sampling signal PA is output, the phase current is detected and the phase current signals PIU, PIV, PIW are obtained. Since it outputs, accurate phase current detection can be performed.

(Embodiment 6)
Next, FIG. 14 is a circuit diagram showing Embodiment 6 of the present invention. In FIG. 14, the inverter unit, sampling unit 6, and phase current detection unit 7 are all the same as those in the first embodiment, and thus description thereof is omitted. The difference from the first embodiment is that it has an amplitude determining means 10A, and the difference from the fifth embodiment is that the output of the amplitude determining means 10A is input to the drive signal generating means 3A.

  FIG. 15 shows a circuit diagram of the drive signal generating means 3A. In FIG. 15, three signals PSU, PSV, PSW from the signal wave generating means 4 are input to the non-inverting terminals of the comparators 301, 302, 303, respectively, and compared with the signal PH from the carrier wave generating means 5, and AND The signal is input to one input terminal of each of the elements 307, 308, and 309. Further, the output signals PEU, PEV, PEW of the amplitude judging means 10A are inputted to the other input terminal of the AND element.

  If the amplitudes of the signal waves PSU, PSV, and PSW are larger than the amplitude of the carrier wave PH, the pulse train as shown in FIG. 5 is not generated, and therefore current detection cannot be performed. The determination means 10A inputs forced current detection signals PEU, PEV, PEW to the drive signal generation means 3A. The drive signal generating means 3A outputs a forced current detection signal to the PQ1 to PQ6 via the AND elements 307 to 309, so that current detection is possible.

  FIG. 16 shows a time chart of the sixth embodiment. FIG. 16 shows a state in which the amplitude of the signal wave is larger than the amplitude of the carrier wave at time T3. Prior to time T3, as described in the first embodiment, forced current detection signals PEU, PEV, and PEW are not output. When the signal wave amplitude increases at time T3, forced current detection signals PEU, PEV, and PEW are output and input to the drive signal generating means 3A. The drive signal generating means 3A outputs the lower FET drive signals PQ2, PQ4, and PQ6 and inputs them to the sampling means 6, so that the sampling signal PA is generated and the current can be detected. This function makes it possible to detect the phase current even when the amplitude of the signal wave is larger than the amplitude of the carrier wave, such as when starting up or when the load is large.

(Embodiment 7)
Next, FIG. 17 is a circuit diagram showing Embodiment 7 of the present invention. In FIG. 17, the inverter unit, the switching signal generation unit 13, the sampling unit 6, and the phase current detection unit 7 are all the same as those in the first embodiment, and thus the description thereof is omitted. The difference from the first embodiment is that it has a magnetoelectric conversion element 11 that detects the magnetic flux of the rotor magnet of the motor. The signal wave generating unit 4A does not require a D / A conversion circuit unlike the signal wave generating unit 4 in the first embodiment, and directly generates a signal wave from the magnetoelectric conversion element 11. In order to detect the magnetic pole position of the motor, since a magnetoelectric conversion element such as a hall element is usually installed, this signal can be used. A three-phase sine wave having a necessary 120 ° phase difference may be generated from a signal from one magnetoelectric conversion element, or a three-phase sine wave may be generated from three magnetoelectric conversion elements.

  The present invention is not limited to the three-phase inverter described in the above embodiment, but can be applied to all multi-phase inverters such as a two-phase inverter. The switching element is not limited to a field effect transistor, and can be applied to other switching elements.

The circuit block diagram of the electric current detection apparatus which shows Embodiment 1 of this invention FIG. 3 is a partial circuit diagram (drive signal generating means) of the current detection device showing the first embodiment of the present invention. Partial circuit diagram (sampling means) of the current detection device showing the first embodiment of the present invention Partial circuit diagram (phase current detection means) of the current detection device showing the first embodiment of the present invention Timing chart of current detection device showing embodiment 1 of the present invention Detailed timing chart of current detection device showing embodiment 1 of the present invention FIG. 3 is a partial circuit diagram for explaining the current detection device according to the first embodiment of the present invention. FIG. 3 is a partial circuit diagram for explaining the current detection device according to the first embodiment of the present invention. The circuit block diagram of the electric current detection apparatus which shows Embodiment 2 of this invention The circuit block diagram of the electric current detection apparatus which shows Embodiment 3 of this invention The circuit block diagram of the electric current detection apparatus which shows Embodiment 4 of this invention The circuit block diagram of the electric current detection apparatus which shows Embodiment 5 of this invention Partial circuit diagram (phase current detection means) of the current detection device showing Embodiment 5 of the present invention The circuit block diagram of the electric current detection apparatus which shows Embodiment 6 of this invention Partial circuit diagram of the current detection device (drive signal generation means) showing Embodiment 6 of the present invention Timing chart of current detection device showing embodiment 6 of the present invention. The circuit block diagram of the current detection apparatus which shows Embodiment 7 of this invention Circuit configuration diagram showing a conventional current detection device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 DC power supply 2 Brushless motor 3 Drive signal generation means 4 Signal wave generation means 5 Carrier wave generation means 6 Sampling means 7 Phase current detection means 8 Correction information output means 9 Phase current correction means 10 Amplitude judgment means 13 Switching signal generation means Q1 ~ Q6 Switching element R0, R1-R3 Current detector PA Sampling signal

Claims (10)

  In the multiphase inverter, a multiphase inverter formed by connecting an arm composed of two switching elements connected in series to a DC power supply in parallel with the number of output phases, switching signal generating means for PWM driving the switching elements, and the multiphase inverter Based on the sampling means for outputting the sampling signal in synchronization with the timing when all of the lower switching elements are turned on, and the voltage detected from the output terminal of the multiphase inverter, the phase current signal is calculated in synchronization with the sampling signal. And a phase current detecting means.   In the multiphase inverter, an arm composed of two switching elements connected in series is connected to a DC power source in parallel with the number of output phases, switching signal generating means for PWM driving the switching elements, and the multiphase inverter A phase current signal is calculated in synchronization with the sampling signal based on sampling means for outputting a sampling signal in synchronization with the timing when all the upper switching elements are in an ON state and a voltage detected from the output terminal of the multiphase inverter. A current detection device comprising phase current detection means.   A current detector for detecting a current flowing on the input side of the multi-phase inverter; a correction information output means for outputting correction information by a voltage signal of the current detector; and the phase current detection means by a signal of the correction information output means The current detection device according to claim 1, further comprising: a phase current correction unit that corrects the output of the current.   In the multiphase inverter, an arm composed of two switching elements connected in series is connected to a DC power source in parallel with the number of output phases, switching signal generating means for PWM driving the switching elements, and the multiphase inverter Current detectors inserted between the lower switching element and the negative side of the DC power source, sampling means for outputting a sampling signal in synchronization with the timing when all of the lower switching elements are on, and each of the above A current detection device comprising: phase current detection means for calculating a phase current signal in synchronization with the sampling signal based on a voltage between both ends detected from a current detector.   The current detection device according to claim 1, wherein the sampling unit includes a delay unit, and outputs the sampling signal through the delay unit.   The switching signal generating means includes a signal wave generating means for generating signal waves of several output phases, a carrier wave generating means for generating a carrier wave of a predetermined frequency, a PWM signal to the switching element by comparing the signal wave and the carrier wave. 6. The current detection device according to claim 1, further comprising drive signal generation means for supplying a signal.   An amplitude determination means for comparing the amplitude of the signal wave with the amplitude of the carrier wave, wherein the output of the phase current detection means is validated when the amplitude of the signal wave is smaller. 6. The current detection device according to 6.   It further comprises amplitude determining means for comparing the amplitude of the signal wave and the amplitude of the carrier wave, and when the amplitude of the signal wave is larger, the switching signal generating means outputs a current forced detection signal having a predetermined frequency. The current detection device according to claim 6.   The current detection device according to claim 6, wherein the signal wave generation unit further includes a D / A conversion circuit, and generates a signal wave based on an output of the D / A conversion circuit.   The current detection device according to claim 6, wherein the signal wave generating unit generates a signal wave by a magnetoelectric conversion element that converts a magnetic flux into a voltage by applying a voltage.

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