JPH1031036A - Wave-form recorder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To display input level of input data in particular, when its sampling speed is set slow without being effected by the sampling speed of a storage controller. SOLUTION: A recorder is constituted such that A/D converted input data is supplied to a level monitor controller 4 and a storage controller 2 according to a predetermined sampling signal and this input data is stored in a memory means 3 as well as the input level of this input data is displayed in a monitor 6. In this case, when the sampling signal to the storage controller 2 for storing this input data in the memory means 3 is set as a signal slower than predetermined sampling speed, a high speed sampling signal higher than the sampling speed to the storage controller 2 is supplied to the level monitor controller 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a waveform recorder,
More specifically, the input level of the input data is set to CRT.
The present invention relates to a waveform recorder in which input data is written to a storage means such as a storage memory while being displayed on a monitor (display).

[0002]

2. Description of the Related Art For example, when an input signal (measured signal) is recorded in real time, there is a demand for knowing the level of input data currently taken in.

Therefore, in a conventional waveform recorder, as shown in FIG. 2, when input data converted into digital data by an A / D converter 1 is written into a memory 3 via a storage controller 2. , The input data is also given to the level monitor controller 4,
The information is displayed on a display 6 as a monitor via a display circuit 5.

According to this, as shown in FIG. 3, for example, the maximum value (M
AX) and the minimum value (MIN) are displayed, for example, in the form of a bar graph, so that the user can know the level of the input data currently loaded in the memory 3.

[0005]

Conventionally, the storage controller 2 and the level monitor controller 4 are both controlled by a sampling signal (sampling clock) from a sampling counter 8 set by the CPU 7. That is, a single sampling counter 8 samples the data of each of the level monitor and the storage.

For this reason, for example, an operating unit (not shown)
If the sampling signal of the storage controller 2 is set to a slow signal via the PU 7, the sampling signal of the level monitor controller 4 is also slowed accordingly, so that the function as the level monitor does not work sufficiently.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is not to be influenced by the sampling speed of a storage controller, and particularly, even when the sampling speed is set to be low, an input signal is not required. An object of the present invention is to provide a waveform recorder capable of accurately displaying an input level of data.

[0008]

In order to achieve the above object, the invention of claim 1 includes a level monitor controller, a storage controller, and a CPU (Central Processing Unit) for controlling both of these controllers.
A waveform recorder which supplies the converted input data to the level monitor controller and the storage controller in accordance with a predetermined sampling signal, and stores the input data in a storage means while displaying the input level of the input data on a monitor. Wherein the CPU gives the level monitor controller a sampling signal faster than the sampling speed for the storage controller when the sampling signal for the storage controller is set to a signal lower than a predetermined sampling speed. I have.

According to a second aspect of the present invention, a first sampling counter for supplying a first sampling signal to the level monitor controller and a second sampling signal slower than the first sampling signal for the storage controller are provided. And a second sampling counter for supplying the storage controller together with the level monitor controller with the first sampling signal when the sampling signal for the storage controller is set to a signal faster than a predetermined sampling rate. Operate, and when the sampling signal to the storage controller is set to a signal lower than a predetermined sampling rate, the second
By operating a sampling counter, the second sampling counter sends the second value to the storage controller.
It is characterized by supplying a sampling signal.

According to a third aspect of the present invention, the second sampling counter has a frequency dividing function for reducing the frequency of the first sampling signal, and a cycle of the second sampling signal is an integral multiple of the first sampling signal. It is characterized by that.

According to this waveform recorder, even if the sampling speed for the storage controller is set to be slow due to, for example, the relationship with the storage capacity of the memory during long-time recording, a higher-speed sampling signal is supplied to the level monitor controller. , The appropriate level display state is maintained.

According to the second aspect of the present invention, when the sampling speed for the storage controller is set to be low, the CPU only needs to operate the second sampling counter, and the processing load does not increase.

Furthermore, according to the third aspect of the present invention, the first sampling signal for the level monitor controller and the second sampling signal for the storage controller are periodically stored in a proportional relationship of an integral multiple, so that they are stored. The correlation between the input data and the data indicated by the level is maintained.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, in order to better understand the technical concept of the present invention, an embodiment will be described with reference to FIG. In this embodiment, the same reference numerals are used for portions which are the same as or are deemed to be the same as those in the conventional example of FIG.

In this embodiment, two sampling counters, a first sampling counter 11 for the level monitor controller 4 and a second sampling counter 12 for the storage controller 2, are provided as sampling counters.

These sampling counters 11, 12
Are both controlled by a CPU (Central Processing Unit) 7. The first sampling counter 11 outputs a level monitor sampling clock (first sampling signal) to the level monitor controller 4. In this embodiment, the level monitor sampling clock is the second sampling counter 1.
2 is also given.

The second sampling counter 12 has a frequency dividing function for reducing the level monitor sampling clock at a predetermined frequency. The operation of this frequency dividing function is turned on and off by an instruction signal from the CPU 7, and when the operation is turned off, the level monitoring sampling clock is output as it is from the second sampling counter 12 to the storage controller 2 as the storage sampling clock. You.

On the other hand, when the frequency dividing function is ON, a storage sampling clock (second sampling signal) obtained by dividing the level monitor sampling clock by a predetermined frequency from the second sampling counter 12 is sent to the storage controller 2. Output.

In this embodiment, the reference sampling speed at which the CPU 7 turns on and off the frequency dividing function of the second sampling counter 12 is set to 10 kHz. The sampling speed when storing data is set arbitrarily by the user from an operation unit (not shown),
When the sampling rate is 10 kHz or more, C
The PU 7 causes the first sampling counter 11 to output a sampling clock of a predetermined speed set by the user, and turns off the frequency dividing function of the second sampling counter 12.

As a result, the sampling clock set by the user is supplied to the storage controller 2 through the second sampling counter 12, so that the level monitor controller 4 and the storage controller 2 operate with the same sampling clock. That is, input data input via the A / D converter 1 is captured by the level monitor controller 4 and the storage controller 2 with the same sampling clock.

On the other hand, when the sampling clock set by the user is less than 10 kHz, the CPU 7 fixes the sampling clock output from the first sampling counter 11 to 10 kHz and sets the frequency dividing function of the second sampling counter 12 to be lower. Turn on the operation of.
Thus, the level monitor controller 4 has 10 kHz.
The sampling clock of z is supplied, and the storage controller 2 is supplied with a sampling clock obtained by dividing the sampling clock by a predetermined frequency.

Therefore, even though the sampling cycle of the actual storage data by the storage controller 2 is slow, the level monitor controller 4 performs sampling faster than the sampling cycle. , The input level is appropriately displayed on the display 6.

In the above embodiment, the second sampling counter 12 is provided with a frequency dividing function for reducing the sampling clock from the first sampling counter to a predetermined value, and the first sampling signal for the level monitor controller and the second sampling signal for the storage controller are provided. Since the two sampling signals are periodically proportional to an integral multiple, the correlation between the stored input data and the data displayed as a level is maintained, but the present invention is not limited to this. Absent.

That is, when the sampling clock set by the user for the storage controller 2 is lower than a predetermined speed (for example, 10 kHz), the sampling clock for the level monitor is kept constant in the above embodiment, and the sampling clock for the storage is automatically set. The sampling clock for level monitoring is set to a frequency obtained by dividing the sampling clock for level monitoring. However, the sampling clock for storage does not necessarily need to be obtained by dividing the sampling clock for level monitoring. The sampling clock itself set by the user may be output.

[0025]

As described above, according to the present invention,
A / D-converted input data is supplied to a level monitor controller and a storage controller in accordance with a predetermined sampling signal to display the input level of the input data on a monitor while storing the input data in storage means. When the sampling signal for the controller is set to a signal lower than the predetermined sampling rate, the sampling rate of the actual storage data is increased by giving the level monitor controller a sampling signal faster than the sampling rate for the storage controller. , The appropriate level display state is maintained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a waveform recorder according to the present invention.

FIG. 2 is a block diagram showing an example of a conventional waveform recorder.

FIG. 3 is a schematic diagram showing an example of a level display displayed on a monitor during input data storage.

[Explanation of symbols]

 Reference Signs List 1 A / D converter 2 Storage controller 3 Memory 4 Level monitor controller 5 Display circuit 6 Display 7 CPU 11 First sampling counter 12 Second sampling counter

Claims (3)

[Claims] 1. A level monitor controller, a storage controller and a C for controlling both controllers.
A PU (Central Processing Unit) is provided, and the A / D-converted input data is supplied to the level monitor controller and the storage controller in accordance with a predetermined sampling signal, and the input level of the input data is displayed on a monitor. In the waveform recorder for storing the input data in the storage means, when the sampling signal for the storage controller is set to a signal slower than a predetermined sampling rate, the CPU controls the level monitor controller to perform sampling for the storage controller. Waveform recorder characterized by giving a sampling signal faster than the speed. 2. A first sampling counter for supplying a first sampling signal to the level monitor controller, and a first sampling counter for supplying a first sampling signal to the storage controller.
A second sampling counter that supplies a second sampling signal that is slower than the sampling signal;
When the sampling signal for the storage controller is set to a signal faster than a predetermined sampling rate, the storage controller is operated together with the level monitor controller by the first sampling signal, and the sampling signal for the storage controller is set to a predetermined value. 2. The system according to claim 1, wherein when the signal is set to a signal lower than the sampling speed, the second sampling counter is operated, and the second sampling signal is supplied from the second sampling counter to the storage controller. Waveform recorder. 3. The method according to claim 2, wherein the second sampling counter has a frequency dividing function for reducing the frequency of the first sampling signal, and a cycle of the second sampling signal is an integral multiple of the first sampling signal. The waveform recorder according to claim 2.