JP2006013141A - Substrate and method for plasma charge evaluation and method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To evaluate whether the amount of plasma charge is larger than a reference value with a small amount of labor. <P>SOLUTION: A plasma charge evaluation method comprises a process for exposing a plasma charge evaluation substrate to plasma used in the manufacturing process of a semiconductor device; and a process for evaluating the amount of plasma charge given to the substrate by plasma, by examining the plasma charge evaluation substrate. The plasma charge evaluation substrate comprises a discharge region 1a formed on a semiconductor substrate 1; an interlayer insulating film 2 formed on the semiconductor substrate 1; a connection hole 2a that is formed on the interlayer insulating film 2, and is positioned on the discharge region 1a; a conductive film 3 for antennas formed on the interlayer insulating film 2; and wiring 4 for fuses that is formed on the interlayer insulating film 2, and connects the conductive film 3 for antennas and the discharge region 1a via the connection hole 2a. When the wiring 4 for fuses has been fused, it is evaluated that the amount of plasma charge is larger than the reference value. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a plasma charge evaluation substrate, a plasma charge evaluation method, and a semiconductor device manufacturing method. In particular, the present invention relates to a plasma charge evaluation substrate, a plasma charge evaluation method, and a method for manufacturing a semiconductor device, which can evaluate whether or not the amount of plasma charge is larger than a reference value with little effort.

  In a manufacturing process of a semiconductor device including a transistor, a wiring or a pad connected to the gate electrode may be charged from plasma. In this case, the charged charge is transmitted to the gate electrode, and a defect may be caused in the gate insulating film located under the gate electrode.

  On the other hand, the power saving of semiconductor devices has progressed, and the gate insulating film of transistors has also become thinner. For this reason, the gate insulating film is likely to be defective due to the plasma charge. Therefore, in the semiconductor manufacturing process, it is necessary to evaluate the plasma charge amount received by the wiring and the pad, and to set the plasma generation condition so that the gate insulating film does not have a defect due to the plasma charge.

  FIG. 10A is a schematic plan view of a plasma charge evaluation element used in a conventional plasma charge evaluation method, and FIG. 10B is a cross-sectional view taken along line AA in FIG. In this plasma charge evaluation element, an element isolation film 102 is formed on the silicon substrate 1. A MOS transistor is formed in the opening 102 a of the element isolation film 102.

  This MOS transistor has a gate oxide film 103 formed on the surface of the silicon substrate 101, a gate electrode 104 located on the gate oxide film 103, and impurity regions 107a and 107b functioning as a source and a drain. The MOS transistor is covered with an interlayer insulating film 108. A connection hole 108 a located on the gate electrode 104 is formed in the interlayer insulating film 108.

  On the interlayer insulating film 108, a large area conductive film 109 made of an Al alloy film is formed. A portion of the antenna conductive film 109 is connected to the gate electrode 104 by being embedded in the connection hole 108a.

When this plasma charge evaluation element is exposed to the plasma to be evaluated, the antenna conductive film 108 receives a plasma charge. The charged charge is transmitted to the gate electrode 104. If the amount of charge charged is larger than the reference value, a defect occurs in the gate oxide film 103 located under the gate electrode 104, and the electrical characteristics of the MOS transistor change. For this reason, it is possible to evaluate whether or not the plasma charge amount is larger than the reference value by evaluating the change in the electrical characteristics of the MOS transistor.
A similar technique is disclosed in Patent Document 1.
Japanese Patent No. 3254549 (paragraphs 58 to 60, FIG. 5)

  When the plasma charge evaluation element as described above is formed on the monitor substrate to evaluate the plasma charge, it is necessary to form a MOS transistor on the monitor substrate. For this reason, it took a long time (for example, 10 to 14 days) to produce a monitor substrate. Thus, conventionally, labor has been required for evaluating plasma charge.

  Further, when the plasma charge evaluation element is formed on a scribe line of a wafer that is an actual product, the silicon substrate is heated in the manufacturing process after the plasma exposure, and heat may be applied to the plasma charge evaluation element. In this case, defects in the gate insulating film are recovered by heat, and it may be impossible to accurately evaluate whether or not the plasma charge amount is larger than the reference value.

  The present invention has been made in consideration of the above-described circumstances, and an object of the present invention is to provide a plasma charge evaluation substrate and a plasma charge evaluation capable of evaluating whether or not the amount of plasma charge is larger than a reference value with little effort. A method and a method for manufacturing a semiconductor device are provided. Another object of the present invention is to provide a method of manufacturing a semiconductor device that can accurately evaluate whether or not the plasma charge amount is larger than a reference value as compared with the conventional case.

In order to solve the above problems, a plasma charge evaluation substrate according to the present invention is:
A semiconductor substrate;
A discharge region formed in the semiconductor substrate;
An interlayer insulating film formed on the semiconductor substrate;
A connection hole formed in the interlayer insulating film and located on the discharge region;
An antenna conductive film formed on the interlayer insulating film;
A fuse wiring formed on the interlayer insulating film and connecting the antenna conductive film and the discharge region through the connection hole;

  When this plasma charge evaluation substrate is exposed to plasma, the antenna conductive film receives plasma charge. The charged electric charge is discharged to the discharge region via the fuse wiring, but if the amount of this charge is too large, the fuse wiring is melted. Therefore, it is possible to evaluate whether or not the amount of plasma charge is larger than the reference value by examining whether or not the fuse wiring is blown.

As described above, the plasma charge evaluation substrate according to the present invention can evaluate the plasma charge amount even if the transistor is not included. Therefore, the plasma charge evaluation substrate can be manufactured in a significantly shorter time than the conventional one.
The discharge region is, for example, an impurity region formed on the semiconductor substrate, but may be a metal layer formed on the semiconductor substrate (for example, on the entire surface).

  Further, the fuse wiring preferably has a portion located on the connection hole wider than the main body. In order to check whether or not the fuse wiring is blown, there is a method of measuring the resistance of the fuse wiring. If the portion of the fuse wiring located on the connection hole is wide, it becomes possible to contact a terminal for measuring resistance.

Another plasma charge evaluation board according to the present invention is:
A conductive film for an antenna formed on an insulating layer;
A fuse wiring formed on the insulating layer and connected to the antenna conductive film;
And a discharge region connected to the fuse wiring and from which electric charges charged in the antenna conductive film are discharged.

Another plasma charge evaluation board according to the present invention is:
A plurality of conductive films for antenna formed on an insulating layer;
A plurality of fuse wirings formed on the insulating layer and connected to each of the plurality of antenna conductive films;
A discharge region that is connected to each of the plurality of fuse wirings and discharges the electric charge charged in the antenna conductive film;
Each of the plurality of fuse wirings has a different width.

  According to this plasma charge evaluation board, each fuse wiring differs in the amount of current necessary for fusing, that is, the amount of plasma charge. For this reason, the amount of plasma charge can be examined in detail by checking which fuse wiring is blown.

Another plasma charge evaluation board according to the present invention is:
A plurality of antenna conductive films formed on an insulating layer and having different areas from each other;
A plurality of fuse wirings formed on the insulating layer and respectively connected to the plurality of antenna conductive films;
A discharge region that is connected to each of the plurality of fuse wirings and that discharges electric charges charged in the antenna conductive film.

  According to this plasma charge evaluation substrate, the area of each conductive film for antenna is different, so that the amount of plasma charge is different for each conductive film for antenna. For this reason, each fuse wiring differs in the amount of plasma charge per unit area required for fusing. Therefore, by checking which fuse wiring is blown, the amount of plasma charge per unit area can be examined in detail.

  In the plasma charge evaluation board described above, the fuse wiring is preferably made of an Al alloy film.

The plasma charge evaluation method according to the present invention includes:
Exposing a plasma charge evaluation substrate to plasma used in a semiconductor device manufacturing process;
Examining the plasma charge evaluation substrate, and evaluating the amount of plasma charge the plasma gives to the substrate,
The plasma charge evaluation substrate is:
A semiconductor substrate;
A discharge region formed in the semiconductor substrate;
An interlayer insulating film formed on the semiconductor substrate;
A connection hole formed in the interlayer insulating film and located on the discharge region;
An antenna conductive film formed on the interlayer insulating film;
A fuse wiring formed on the interlayer insulating film and connecting the antenna conductive film and the discharge region through the connection hole;
The step of evaluating the plasma charge amount determines that the plasma charge amount is larger than a reference value when the fuse wiring is blown, and the plasma charge amount when the fuse wiring is not blown. Is a step of determining that is less than the reference value.

A method for manufacturing a semiconductor device according to the present invention includes:
A step of evaluating a plasma charge amount given to the semiconductor substrate by the plasma and setting a plasma generation condition;
Generating plasma based on the plasma generation conditions, and manufacturing a semiconductor device using the plasma,
The step of setting the plasma generation conditions includes:
Exposing a plasma charge evaluation substrate to plasma used in a semiconductor device manufacturing process;
Examining the plasma charge evaluation substrate to evaluate the amount of plasma charge the plasma imparts to the substrate;
When the plasma charge amount is larger than the reference value, the method includes changing the plasma generation conditions so as to reduce the plasma charge amount,
The plasma charge evaluation substrate is:
A semiconductor substrate;
A discharge region formed in the semiconductor substrate;
An interlayer insulating film formed on the semiconductor substrate;
A connection hole formed in the interlayer insulating film and located on the discharge region;
An antenna conductive film formed on the interlayer insulating film;
A fuse wiring formed on the interlayer insulating film and connecting the antenna conductive film and the discharge region through the connection hole;
The step of evaluating the plasma charge amount determines that the plasma charge amount is large when the fuse wiring is blown, and the plasma charge amount is the reference when the fuse wiring is not blown. This is a step of determining that the value is less than the value.

Another method of manufacturing a semiconductor device according to the present invention is as follows.
Forming a conductive film on the insulating film;
By patterning the conductive film, a wiring located in the chip region is formed on the insulating film, and the antenna conductive film located on the scribe line and the antenna conductive film are charged on the insulating film. Forming a fuse wiring for discharging the generated charge;
Forming a second insulating film on the interlayer insulating film, the antenna conductive film, and the fuse wiring using plasma;
And a step of evaluating the plasma charge amount by the plasma by checking whether or not the fuse wiring is blown.
The second insulating film may be an interlayer insulating film or a passivation film.

  The method for manufacturing a semiconductor device may further include a step of applying heat to the semiconductor substrate. Whether or not the fuse wiring is blown does not change even when heat is applied to the semiconductor substrate. Therefore, it is possible to accurately determine whether or not the plasma charge amount exceeds the reference value as compared with the conventional method using a MOS transistor.

  Further, a step of removing the second insulating film from the fuse wiring may be further included between the step of forming the second insulating film and the step of evaluating the plasma charge amount.

BEST MODE FOR CARRYING OUT THE INVENTION

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Each drawing in FIG. 1 is a cross-sectional view showing a method for manufacturing a plasma charge evaluation substrate according to the first embodiment. This plasma charge evaluation substrate is used to evaluate the amount of plasma charge received while a semiconductor device as a product is exposed to plasma in a semiconductor manufacturing apparatus. Note that in a semiconductor device, plasma charge is generated in a wiring included in the semiconductor device, but the amount of the plasma charge varies depending on the wiring layer. Therefore, it is necessary to form a plasma charge evaluation substrate for each wiring layer.

  First, as shown in FIG. 1A, a photoresist film is applied to the surface of the silicon substrate 1, and this photoresist film is exposed and developed. Thereby, a resist pattern 50 is formed on the surface of the silicon substrate 1. Next, impurity ions are implanted into the silicon substrate 1 using the resist pattern 50 as a mask. As a result, a discharge impurity region 1 a is formed in the silicon substrate 1.

  Thereafter, as shown in FIG. 1B, the resist pattern 50 is removed. Next, an interlayer insulating film 2 containing, for example, silicon oxide as a main component is formed on the silicon substrate 1 by a CVD method. Next, a photoresist film (not shown) is applied on the interlayer insulating film 2, and this photoresist film is exposed and developed. As a result, a resist pattern is formed on the interlayer insulating film 2. Next, the interlayer insulating film 2 is etched using this resist pattern as a mask. As a result, a connection hole 2 a located on the impurity region 1 a is formed in the interlayer insulating film 2. Thereafter, the resist pattern is removed.

Next, as shown in FIG. 1C, a film in which a TiN film and an Al alloy film are laminated in this order in the connection hole 2a and on the interlayer insulating film 2 is formed by a sputtering method. The TiN film functions as a barrier film. Next, a photoresist film (not shown) is applied on the laminated film, and the photoresist film is exposed and developed. As a result, a resist pattern is formed on the interlayer insulating film 2. Next, the laminated film is etched using this resist pattern as a mask. Thereby, a plasma charge evaluation pattern is formed on the interlayer insulating film 2. Thereafter, the resist pattern is removed.
In this way, a plasma charge evaluation substrate can be manufactured. The time required for this production is 1-2 days.

  FIG. 2 is a schematic plan view of the plasma charge evaluation substrate in the state of FIG. The plasma charge evaluation pattern included in the plasma charge evaluation substrate includes an antenna conductive film 3, a fuse wiring 4, and a contact portion 5. The fuse wiring 4 connects the antenna conductive film 3 and the contact portion 5. The contact portion 5 is located on the connection hole 2a, and is partially connected to the impurity region 1a by being embedded in the connection hole 2a. Thus, the antenna conductive film 3 is connected to the impurity region 1 a via the fuse wiring 4 and the contact portion 5.

  The antenna conductive film 3 is, for example, substantially rectangular. The area of the antenna conductive film 3 is approximately equal to the sum of the areas of the wiring and pads connected to the semiconductor element (for example, a transistor or a capacitor) in the wiring layer whose plasma charge amount is to be evaluated, or the sum of the areas. It is preferable to make it slightly larger.

When the antenna conductive film 3 is plasma charged, the charged charge is discharged in the impurity region 1 a via the fuse wiring 4 and the contact portion 5. The thickness of the fuse wiring 4 is set so that the fuse wiring 4 is blown when the plasma charge amount received by the antenna conductive film 3 exceeds the plasma charge amount (that is, the reference value) allowable by the semiconductor device. .
For this reason, the thickness of the fuse wiring 4 becomes thinner as the amount of plasma charge allowed by the semiconductor element decreases. For example, in the case where the semiconductor element is a transistor, the fuse wiring 4 becomes thinner as the transistor becomes smaller or as the gate insulating film of the transistor becomes thinner.

  Further, the contact portion 5 is wider than the fuse wiring 4. For this reason, the position of the contact part 5 is hard to come off from the connection hole 2a.

3 is a cross-sectional view for explaining a method for evaluating the amount of plasma charge received by a semiconductor device in the manufacturing process of the semiconductor device using the plasma charge evaluation substrate shown in FIGS. 1 and 2. .
First, as shown in FIG. 3A, the plasma charge evaluation substrate is exposed to plasma generated by the semiconductor manufacturing apparatus. This plasma is, for example, plasma used in a plasma CVD method (for example, plasma for forming an interlayer insulating film or a passivation film), but may be plasma other than these. Further, the plasma generation conditions are matched with the conditions for manufacturing a semiconductor device as a product.

At this time, electric charges are charged in the conductive film 3 for the antenna. The charged charge is discharged in the impurity region 1 a of the silicon substrate 1 through the fuse wiring 4 and the contact portion 5. At this time, if the charge amount is larger than the reference value, the fuse wiring 4 made of an Al alloy is blown out.
By exposure to plasma, a film 6 such as an insulating film is formed on the plasma charge evaluation substrate. The interlayer insulating film 2, the antenna conductive film 3, the fuse wiring 4 and the contact portion 5 are respectively , Covered by the membrane 6.

  Thereafter, as shown in FIG. 3B, the formed film 6 is removed, and the conductive film 3 for antenna, the wiring 4 for fuse, and the contact portion 5 are exposed. Next, it is inspected whether or not the fuse wiring 4 is blown. At this time, it may be directly confirmed whether or not the fuse wiring 4 is blown using an electron microscope or the like, or a terminal is brought into contact with each of the conductive film 3 for antenna and the contact portion 5 to insulate between them. It may be confirmed whether or not the fuse wiring 4 is blown by confirming whether or not this is done. In the latter case, since the contact portion 5 is wider than the fuse wiring 4, the terminal can be brought into contact with the contact portion 5.

  FIG. 4 is a schematic plan view of the plasma charge evaluation substrate in the state of FIG. As shown in the schematic plan view of FIG. 4, when the fuse wiring 4 is blown, it is determined that there is too much plasma charge, and the plasma generation conditions of the semiconductor manufacturing apparatus are changed in a direction to reduce the plasma charge, and Evaluate plasma charge.

  When the fuse wiring 4 is not blown, it is determined that the plasma generation conditions are appropriate, the plasma generation conditions of the semiconductor manufacturing apparatus are maintained as they are, and the semiconductor device is generated using the plasma generated by the semiconductor manufacturing apparatus. Manufacture.

  As described above, according to the present embodiment, the discharge impurity region 1 a is formed on the silicon substrate 1, the interlayer insulating film 2 and the connection hole 2 a are formed on the silicon substrate 1, and the antenna is formed on the interlayer insulating film 2. By forming the conductive film 3, the fuse wiring 4, and the contact portion 5, a plasma charge evaluation substrate can be manufactured. For this reason, the period required for the production of the plasma charge evaluation substrate is 1 to 2 days, which is significantly shorter than the conventional one.

  Further, a plasma charge evaluation pattern is formed by patterning the Al alloy film, and the characteristics of this pattern are determined by the shapes of the conductive film 3 for antenna and the wiring 4 for fuse. For this reason, the variation can be reduced as compared with the conventional evaluation pattern using the MOS transistor.

FIG. 5 is a schematic plan view of a plasma charge evaluation substrate according to the second embodiment. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
First, a plurality of impurity regions for discharge (not shown) are formed on a silicon substrate (not shown) by the same method as in the first embodiment, and an interlayer insulating film 2 is further formed. Next, connection holes 2 a are formed in the interlayer insulating film 2 on each of the plurality of impurity regions for discharge. These forming methods are the same as those in the first embodiment.

Next, a laminated film in which a TiN film and an Al alloy film are laminated in this order is formed on the interlayer insulating film 2 and each of the plurality of connection holes 2a. Next, a resist pattern is formed on the laminated film, and the laminated film is etched using the resist pattern as a mask. Thereby, a plurality of plasma charge evaluation patterns are formed on the interlayer insulating film 2. Thereafter, the resist pattern is removed.
In this way, a plasma charge evaluation substrate is formed.

Each plasma charge evaluation pattern includes an antenna conductive film 3, a fuse wiring 4, and a contact portion 5. Each contact portion 5 is connected to different discharge impurity regions by being partially embedded in different connection holes 2a.
Further, the thicknesses of the fuse wiring 4 are different from each other in each plasma charge evaluation pattern. For this reason, the plasma charge evaluation patterns are different from each other in the amount of plasma charge required for fusing the fuse wiring 4. The area of all the conductive films 3 for antennas is the same as that of the first embodiment.

The plasma charge evaluation method using this plasma charge evaluation substrate is the same as in the first embodiment. For this reason, also by this embodiment, the same effect as a 1st embodiment can be acquired.
Further, since a plurality of plasma charge evaluation patterns are provided and the thicknesses of the fuse wirings 4 included in these patterns are mutually changed, it is possible to finely determine the magnitude of the plasma charge amount by checking which fuse wiring 4 is blown. You can investigate.

FIG. 6 is a schematic plan view of a plasma charge evaluation substrate according to the third embodiment. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
First, a plurality of discharge impurity regions (not shown) are formed on a silicon substrate (not shown) by the same method as in the first embodiment, and an interlayer insulating film 2 is further formed. Next, connection holes 2 a are formed in the interlayer insulating film 2 on each of the plurality of impurity regions for discharge. These forming methods are the same as those in the first embodiment.

Next, a laminated film in which a TiN film and an Al alloy film are laminated in this order is formed on the interlayer insulating film 2 and each of the plurality of connection holes 2a. Next, a resist pattern is formed on the laminated film, and the laminated film is etched using the resist pattern as a mask. Thereby, a plurality of plasma charge evaluation patterns are formed on the interlayer insulating film 2. Thereafter, the resist pattern is removed.
In this way, a plasma charge evaluation substrate is formed.

Each plasma charge evaluation pattern includes an antenna conductive film 3, a fuse wiring 4, and a contact portion 5. Each contact portion 5 is connected to different discharge impurity regions by being partially embedded in different connection holes 2a.
In each plasma charge evaluation pattern, the area of the conductive film for antenna 3 is different from each other, but the thickness of the fuse wiring 4 is the same. For this reason, the plasma charge evaluation patterns are different from each other in the amount of plasma charge per unit area necessary for fusing the fuse wiring 4.

The plasma charge evaluation method using this plasma charge evaluation substrate is the same as in the first embodiment. For this reason, also by this embodiment, the same effect as a 1st embodiment can be acquired.
In addition, since a plurality of plasma charge evaluation patterns are provided and the areas of the conductive film 3 for antennas included in these patterns are changed from each other, by checking which fuse wiring 4 is blown, it is possible to obtain a per unit area of plasma charge amount. The size of can be examined in detail.

  Each drawing in FIG. 7 is a cross-sectional view for explaining the fourth embodiment. This embodiment is a method of manufacturing a semiconductor device. Then, by forming a plasma charge evaluation pattern on the scribe line, it is possible to evaluate whether or not the plasma charge amount when manufacturing an actual semiconductor device exceeds a reference value.

  First, as shown in FIG. 7A, an element isolation film 12 is formed on a silicon substrate 11. The element isolation film 12 is formed by, for example, the LOCOS method, and has openings 12a and 12b in the chip region 10a and the scribe line 10b, respectively. Next, the silicon substrate 11 is thermally oxidized. As a result, a gate oxide film 13a is formed in the opening 12a of the chip region 10a. An oxide film 13b is also formed in the opening 12b of the scribe line 10b.

  Next, a polysilicon film is formed on the entire surface including the gate oxide film 13a, and this polysilicon film is patterned. Thereby, the gate electrode 14 is formed on the gate oxide film 13a. Next, impurity ions are implanted into the silicon substrate 11 using the element isolation film 12 and the gate electrode 14 as a mask. Thereby, low-concentration impurity regions 16a and 16b are formed in the silicon substrate 11 located in the opening 12a. At this time, impurity ions are also implanted into the silicon substrate 1 located in the opening 12b.

Next, a silicon oxide film is formed on the entire surface including on the gate electrode 14, and this silicon oxide film is etched back. Thereby, a sidewall 15 is formed on the sidewall of the gate electrode 14.
Next, impurity ions are implanted into the silicon substrate 11 using the element isolation film 12, the gate electrode 14 and the sidewall 15 as a mask. As a result, impurity regions 17a and 17b serving as a source and a drain are formed in the silicon substrate 11 located in the opening 12a. At this time, impurity ions are also implanted into the silicon substrate 1 located in the opening 12b, and a discharge impurity region 17d is formed.
In this way, a transistor is formed in the chip region 10a.

Next, an interlayer insulating film 18 is formed on the entire surface including the transistor in the chip region 10a and the oxide film 13b in the scribe line 10b. Next, a photoresist film (not shown) is applied on the interlayer insulating film 18, and this photoresist film is exposed and developed. As a result, a resist pattern is formed on the interlayer insulating film 18. Next, the interlayer insulating film 18 is etched using this resist pattern as a mask. Thereby, in the interlayer insulating film 18, connection holes 18a, 18b, and 18d located above the impurity regions 17a, 17b, and 17d are formed, and a connection hole 18c located on the gate electrode 14 is also formed. .
Thereafter, the resist pattern is removed.

  Next, a tungsten (W) film is formed in each of the connection holes and on the interlayer insulating film 18. Next, the tungsten film located on the interlayer insulating film 18 is removed by CMP or etch back. Thereby, W plugs 19a, 19b, 19c, and 19d are embedded in the connection holes 18a, 18b, 18c, and 18d, respectively.

  Next, a laminated film in which a TiN film, an Al alloy film, a Ti film, and a TiN film are laminated in this order on each of the W plugs and on the interlayer insulating film 18 is formed by, for example, a sputtering method. Next, a photoresist film is applied on the laminated film, and the photoresist film is exposed and developed. Thereby, a resist pattern is formed on the laminated film. Next, the laminated film is etched using this resist pattern as a mask. As a result, wirings 31a, 31b, 31c located in the chip region 10a are formed on the interlayer insulating film 18, and a plasma charge evaluation pattern 20 located in the scribe line 10b is formed. The wirings 31a, 31b and 31c are connected to the impurity regions 17a and 17b serving as the source and drain via the W plugs 19a and 19b, respectively, and the wiring 31c is connected to the gate electrode 14 via the W plug 19c. Yes.

Here, the shape of the plasma charge evaluation pattern 20 will be described with reference to FIG. FIG. 8 is a schematic plan view of the semiconductor device in the state of FIG.
The plasma charge evaluation pattern 20 includes an antenna conductive film 21, a fuse wiring 22, and a contact portion 23. The antenna conductive film 21 has, for example, a substantially rectangular shape.

  The contact portion 23 is connected to the impurity region 17d through the W plug 19d. The fuse wiring 22 connects the antenna conductive film 21 and the contact portion 23. In this way, the antenna conductive film 21 is connected to the discharge impurity region 17d via the fuse wiring 22, the contact portion 23, and the W plug 19d.

  The plasma charge received by the antenna conductive film 21 flows to the impurity region 17d via the fuse wiring 22 and the contact portion 23 and is discharged. Note that the thickness of the fuse wiring 22 is set so as to blow when the amount of plasma charge received by the antenna conductive film 21 exceeds a reference value. This reference value is equal to the plasma charge received by the antenna conductive film 21 when the amount of plasma charge received by the wiring 31c is equal to or slightly smaller than the allowable amount of the gate oxide film 13a of the transistor. Amount.

Returning to the description of the semiconductor device manufacturing method.
Thereafter, as shown in FIG. 7C, a second interlayer insulating film 32 is formed on the entire surface including the interlayer insulating film 18, the wirings 31 a to 31 c, and the plasma charge evaluation pattern 20. A plasma CVD method is used to form the second interlayer insulating film 32.

At this time, each of the antenna conductive film 21 and the wiring 31c receives plasma charge. The plasma charge received by the wiring 31c flows to the gate electrode 14 through the W plug 19c.
As described above, in the step of forming the second interlayer insulating film 32, when the amount of plasma charge received by the wiring 31c exceeds (or is likely to exceed) the allowable amount of the gate oxide film 13a, the antenna The amount of plasma charge received by the conductive film 21 exceeds the reference value of the fuse wiring 22. For this reason, the fuse wiring 22 is melted.

Thereafter, in the semiconductor device, an upper wiring layer is formed, and further, an interlayer insulating film and a passivation film are formed. At this time, the silicon substrate 1 is heated, but whether or not the fuse wiring 22 is blown does not change depending on the heat treatment.
In this way, the semiconductor device is manufactured.

  FIG. 9A illustrates a method for evaluating the amount of plasma charge received by the gate oxide film 13a in the step of forming the second interlayer insulating film 32 in the semiconductor device shown in FIGS. FIG. 9B is a cross-sectional view of the semiconductor device, and FIG. 9B is a schematic plan view of the semiconductor device in the state of FIG.

  When evaluating the amount of plasma charge, as shown in FIG. 9A, the second interlayer insulating film 32 is removed from the semiconductor device, and the plasma charge evaluation pattern 20 is exposed. Next, it is inspected whether or not the fuse wiring 22 is blown. This inspection method is the same as in the first embodiment.

  If the fuse wiring 22 is blown, it is determined that there is too much plasma charge, and the plasma generation conditions of the apparatus for forming the second interlayer insulating film 32 are changed in a direction that reduces the plasma charge. If the fuse wiring 4 is not blown, it is determined that the plasma generation conditions are appropriate, and the plasma generation conditions are maintained as they are.

  As described above, according to the present embodiment, it is possible to evaluate the plasma charge amount by examining whether or not the fuse wiring 22 is blown. Whether or not the fuse wiring 22 is blown is less likely to change even if heat is applied to the semiconductor device after the second interlayer insulating film 32 is formed. For this reason, in the actual manufacturing process of a semiconductor device, it is possible to accurately evaluate whether or not the plasma charge amount exceeds the allowable value as compared with the conventional case.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

(A) is sectional drawing for demonstrating the manufacturing method of the plasma charge evaluation board | substrate which concerns on 1st Embodiment, (B) is sectional drawing for demonstrating the next process of (A), (C) is ( Sectional drawing for demonstrating the next process of B). FIG. 2 is a schematic plan view of a plasma charge evaluation substrate in the state of FIG. (A) is sectional drawing for demonstrating the method of evaluating the quantity of the plasma charge which a semiconductor device receives, (B) is sectional drawing for demonstrating the next process of (A). FIG. 4 is a schematic plan view of a plasma charge evaluation substrate in the state of FIG. The plane schematic diagram of the plasma charge evaluation board concerning a 2nd embodiment. The plane schematic diagram of the plasma charge evaluation board concerning a 3rd embodiment. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 4th Embodiment, (B) is sectional drawing for demonstrating the next process of (A), (C) is the next process of (B). Sectional drawing for demonstrating. FIG. 8 is a schematic plan view of the semiconductor device in the state of FIG. (A) is sectional drawing for demonstrating the method to evaluate the quantity of the plasma charge which the gate oxide film 13a received, (B) is the plane schematic diagram of the semiconductor device in the state of (A). (A) is the plane schematic diagram of the monitor board | substrate used for the conventional plasma charge evaluation method, (B) is AA sectional drawing of (A).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,11,101 ... Silicon substrate, 1a, 17d ... Impurity region for discharge, 2, 18, 108 ... Interlayer insulating film, 2a, 18a, 18b, 18c, 18d, 108a ... Connection hole, 3, 21, 109 ... Antenna conductive film 4, 22 ... fuse wiring, 5, 23 ... contact part, 6 ... film, 17a, 17b, 107a, 107b ... impurity region, 10a ... chip region, 10b ... scribe line, 12, 102 ... element Isolation film, 12a, 12b, 102a ... opening, 13a, 103 ... gate oxide film, 13b ... oxide film, 14, 104 ... gate electrode, 15 ... sidewall, 16a, 16b ... low concentration impurity region, 19a, 19b, 19c, 19d ... W plug, 20 ... plasma charge evaluation pattern, 31a, 31b, 31c ... wiring, 32 ... second interlayer insulating film, 50 ... Resist pattern

Claims (11)

A semiconductor substrate;
A discharge region formed in the semiconductor substrate;
An interlayer insulating film formed on the semiconductor substrate;
A connection hole formed in the interlayer insulating film and located on the discharge region;
An antenna conductive film formed on the interlayer insulating film;
A plasma charge evaluation substrate, comprising: a fuse wiring formed on the interlayer insulating film and connecting the antenna conductive film and the discharge region through the connection hole.   The plasma charge evaluation substrate according to claim 1, wherein the discharge region is an impurity region formed in the semiconductor substrate. A conductive film for an antenna formed on an insulating layer;
A fuse wiring formed on the insulating layer and connected to the antenna conductive film;
A plasma charge evaluation substrate comprising: a discharge region connected to the fuse wiring and from which electric charges charged in the antenna conductive film are discharged. A plurality of conductive films for antenna formed on an insulating layer;
A plurality of fuse wirings formed on the insulating layer and connected to each of the plurality of antenna conductive films;
A discharge region that is connected to each of the plurality of fuse wirings and discharges the electric charge charged in the antenna conductive film;
Each of the plurality of fuse wirings is a plasma charge evaluation board having a different width. A plurality of antenna conductive films formed on an insulating layer and having different areas from each other;
A plurality of fuse wirings formed on the insulating layer and respectively connected to the plurality of antenna conductive films;
A plasma charge evaluation board, comprising: a discharge region connected to each of the plurality of fuse wirings and discharging the charge charged in the antenna conductive film.   The plasma charge evaluation board according to claim 1, wherein the fuse wiring is made of an Al alloy film. Exposing a plasma charge evaluation substrate to plasma used in a semiconductor device manufacturing process;
Examining the plasma charge evaluation substrate, and evaluating the amount of plasma charge the plasma gives to the substrate,
The plasma charge evaluation substrate is:
A semiconductor substrate;
A discharge region formed in the semiconductor substrate;
An interlayer insulating film formed on the semiconductor substrate;
A connection hole formed in the interlayer insulating film and located on the discharge region;
An antenna conductive film formed on the interlayer insulating film;
A fuse wiring formed on the interlayer insulating film and connecting the antenna conductive film and the discharge region through the connection hole;
The step of evaluating the plasma charge amount determines that the plasma charge amount is larger than a reference value when the fuse wiring is blown, and the plasma charge amount is determined when the fuse wiring is not blown. A plasma charge evaluation method, which is a step of determining that the amount is less than the reference value. A step of evaluating a plasma charge amount given to the semiconductor substrate by the plasma and setting a plasma generation condition;
Generating plasma based on the plasma generation conditions, and manufacturing a semiconductor device using the plasma,
The step of setting the plasma generation conditions includes:
Exposing a plasma charge evaluation substrate to plasma used in a semiconductor device manufacturing process;
Examining the plasma charge evaluation substrate to evaluate the amount of plasma charge the plasma imparts to the substrate;
When the plasma charge amount is larger than the reference value, the method includes changing the plasma generation conditions so as to reduce the plasma charge amount,
The plasma charge evaluation substrate is:
A semiconductor substrate;
A discharge region formed in the semiconductor substrate;
An interlayer insulating film formed on the semiconductor substrate;
A connection hole formed in the interlayer insulating film and located on the discharge region;
An antenna conductive film formed on the interlayer insulating film;
A fuse wiring formed on the interlayer insulating film and connecting the antenna conductive film and the discharge region through the connection hole;
The step of evaluating the plasma charge amount determines that the plasma charge amount is larger than a reference value when the fuse wiring is blown, and the plasma charge amount is determined when the fuse wiring is not blown. A method for manufacturing a semiconductor device, the step of determining that the value is less than the reference value. Forming an insulating film above the semiconductor substrate;
Forming a conductive film on the insulating film;
By patterning the conductive film, a wiring located in the chip region is formed on the insulating film, and the antenna conductive film located on the scribe line and the antenna conductive film are charged on the insulating film. Forming a fuse wiring for discharging the generated charge;
Forming a second insulating film on the interlayer insulating film, the antenna conductive film, and the fuse wiring using plasma;
And a step of evaluating the plasma charge amount by the plasma by checking whether or not the fuse wiring is blown.   The method for manufacturing a semiconductor device according to claim 11, further comprising a step of applying heat to the semiconductor substrate between the step of forming the second insulating film and the step of evaluating the plasma charge amount.   11. The method according to claim 9, further comprising a step of removing the second insulating film from the fuse wiring between the step of forming the second insulating film and the step of evaluating the plasma charge amount. The manufacturing method of the semiconductor device of description.

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