KR100446117B1 - Post-fuse blow corrosion prevention structure for copper fuses - Google Patents

Abstract

In the present invention, the structure and method of a semiconductor resistant metal fuse corrosion line 114c including a refractory liner 114b, 114d that can also act as a resistor are known. . The manufacture is made using a damascene process. The metal structure can be formed on a semiconductor substrate comprising a first portion comprising a first layer and a second layer, the first layer having a higher resistance than the second layer, and the second layer being formed of a first layer in the first portion. Having a horizontal and vertical surface that makes contact with the first layer, the second portion is coupled to the first portion, the second portion comprises the first layer, and the first layer is the horizontal and vertical of the second layer in the second portion Do not make contact with the surface. The metal structure can be used as a corrosion resistance fuse. The metal structure can also be used as a resistance element.

Description

Metal Structure and Fire Resistant Element Barrier Formation Method {POST-FUSE BLOW CORROSION PREVENTION STRUCTURE FOR COPPER FUSES}

Fuses can be used in semiconductor chips to provide redundancy of functionality, electrical chip identification, and customization of functions. For designs with three (or more) layers of wiring, a fuse is typically one of the wiring layers, for example "last metal" (LM) or "final metal minus 1" ( LM-1) formed from the same segment as the wiring layer. Fusing, ie removal of the portion of the metal fuse line, is achieved by exposure of the short and high intensity pulses to the "light" of the metal fuse line portion from an infrared-red (IR) laser. The metal line absorbs energy, melts and expands, breaking the passivation layer overlying it. The molten metal then boils or evaporates from the oxide environment, disrupting line continuity resulting in high electrical resistance. The metal exposed by this laser ablation process can corrode and cause undesirable reconnection of fuse links.

A semiconductor integrated circuit is formed in a body of semiconductor material having an active region coupled to a desired circuit configuration by a plurality of wiring layers placed on the surface of the body.

In the fabrication of circuits, the wiring layers are deposited, defined, and interconnected by conductive vias through a series of well known photolithography and metal etching steps. These wiring levels can each be covered with a layer of a glassy protective material known as a passivation layer, which protects and insulates each wiring layer. The creation of such multilayered integrated circuits is well known in the semiconductor art.

In some circuits, for example CMOS logic circuits, fuses designed within the circuit are often formed in a regular array of top wiring layers, where no other wiring is located directly above the fuse. Within such arrays, the fuses are often arranged in parallel rows and located as close as possible. By opening a selected one of these fuses, the logic elements of the circuit can be arranged in different combinations to perform different logic functions.

These fuses are typically opened by applying a laser pulse of sufficient size, time and power to overheat and evaporate the metal forming the fuse. This overheating and evaporation of the fuse breaks away a portion of the overlying glassy protective layer, creating a crater-shaped pit in the protective layer. When the protective layer ruptures, cracks spread outwards, causing damage such as breakage and uncovering of adjacent devices. Such exposure of adjacent devices may subsequently lead to corrosion and premature failure of the circuit.

In next-generation integrated circuits, such as complementary metal oxide semiconductor (CMOS) back end of line (BEOL) and smaller than 0.25 µm, copper wiring meets BEOL resistive capacitor (RC) delay performance requirements. It is preferred to be used to meet. During stressing of a copper fuse, such as for example, a condition of 85% relative humidity with electrical bias stressing at a temperature of 85 ° C., the copper fuse may corrode. If tantalum nitride / tantalum (TaN / Ta) liners do not act as corrosion barriers, this corrosion may extend through multiple via levels. The byproduct of this corrosion can completely cover the blown fuse, which can create undesirable resistive leakage paths between the blown fuses. Known methods of reducing and eliminating these defects include using aluminum wiring and passivating the copper fuse after the fuse is blown. However, adding aluminum wiring levels reduces the electrical performance of the device, and adding a passivation layer after the fuse blows increases cost and complexity. There is a need for an improved method to reduce and eliminate corrosion of exposed copper wiring.

The reader may refer to a patent relating to a fuse as follows.

"Fusible Links with Improved Interconnection Structure," US Patent No. 5,760,674,

"Array Fuse Damage Protection Device and Fabrication Nethode," Richard A. US Patent No. 5,420,455 to Richard A. Gilmour et al.,

"Integrated Pad Fuse Structure For Planar Copper Metallurgy," William T. U.S. Patent No. 5,731,624 to William T. Motsiff et al.,

"Meyhod of making a multilayer thin film structure," US Pat. No. 5,266,446 to Kenneth Chang et al.

The reader may also refer to some papers and some known patent documents and patents.

Anonymous, "Fuse Structure for Wide Fuse Materials Choice," IBM Publication No. 32, 3A, pages 438-439, August 1989,

Anonymous, "Optimum Metal Line Structure For Memory Array and Support Circuits," IBM Publication No. 30, No. 12, pages 218-219, May 1988,

Anonymous, "Method to Incorporate Three Sets of Pattern Information in Two Photo-Masking Steps," IBM Publication No. 32, 8A, pages 170-171, January 1990,

"Structure and Method of Making Alpha-Ta in Thin Films", Lee. G. US Patent Application No. 5,281,485 to E.G.Colgan et al.,

Seed. European Publication No. EP 751566 A2, "A Thin-Film Metal Barrier for Electronic Connections" by C. Cabral et al.,

Seed. C.-K. Hu et al., “Diffusion Barrier Studies for Cu,” pages 181-187, Proc. V-MIC, 1986,

Seed. C.-K. Hu et al., “Copper-Polymide Wiring Technology for VLSI Circuits,” pages 369-373, Proc. Substance Research Council. 1990 and

D. D. Edelstein et al., “Full Copper Wiring in sub-0.25 μm CMOS ULSI Technology”, pp. 773-776. Dig. IEEE Int. Electr. Dev. Mtg. 1997. The contents of which are incorporated herein by reference.

Resistive elements are important for peripheral and internal circuits. The resistive element can be used in internal circuits, such as voltage regulators, reference bias circuits, and other applications. Resistive elements are used in peripheral circuits in receivers and drivers for impedance matching, noise / ring-back dampening, resistor ballasting, overvoltage dampening, and other applications. Can be used. In electrostatic discharge (ESD) networks, the resistor can be used in a resistor capacitor (RC) to which n-type field effect transistors (NFETs) are connected, for resistance stability and many other applications. Integrated into metal oxide semiconductor FETs (MOSFETs).

Many materials used as resistors are suitable in functional situations but not in ESD robust or precision linear applications. Diffusion resistors are commonly used in circuit applications but can have many disadvantages. Polysilicon thin film resistors and diffused implanted resistors can be considered in high voltage and high current situations. N-well, n-diffusion, buried resistor BR can be used for many circuit applications. Polysilicon resistance can also have reliability problems. Polysilicon resistance may exhibit a "spaghetti effect" at high voltage stresses. Under high voltage stress, polysilicon resistors can cause resistance value changes that cause malfunctions in circuits and ESD applications.

N-wells, n-diffusions, buried resistors (BR) can be used in many circuit applications. Diffusion resistors can add extra capacitance to the circuit. This separate capacitance does not benefit receiver performance and oscillator capacitance load. In analog, radio frequency CMOS, and high performance applications, capacitance can be considered. Diffusion resistors can also be considered for ring-back, undershoot and latchup phenomena. In solid state transistor logic (SSTL) circuit applications where "critical braking" is required, for example in input / output (I / O) circuits, the diffusion component is subject to the ringback phenomenon when this diffusion component is commonly used in negative undershoot. It can be harmful. N-wells, n-diffusions, and buried resistors can also form parasitic npn structures that can create unwanted ESD and functional parasitics. As a result, ground rules can be extended to handle these parasitic elements. The resistive element can be a large part of the I / O circuit area between the physical structure and the required ground rule space. Diffusion resistors may also be of interest to the charging device model (CDM). In CDM test mode, for example, diffusion resistors actively intervene to create unwanted parasitic elements.

If so, low capacitance, high resistance, high linearity with respect to voltage and temperature, and physically small resistance with high melting temperature are needed. There is also a need for improved resistance that does not interact with the silicon surface of the substrate. In applications where it is necessary to be insensitive to voltage stressing, electrical overstress (EOS) and electrostatic discharge (ESD) phenomena, it is desirable that resistive elements can be used.

Summary of the Invention

A first portion comprising a lower layer and an upper layer, the lower layer having a higher electrical resistance than the upper layer, the upper layer having a horizontal and vertical surface in contact with the lower layer in the first portion, the second portion being in contact with the first portion; And a metal structure formed over the semiconductor substrate, the second portion being formed by a lower layer in the second portion that is not in contact with the horizontal and vertical surfaces of the upper layer. Metal structures can be used as a corrosion resistant fuse. Metal structures can also be used as resistive elements.

The present invention relates to lithographic patterning, etching, deposition of a fire resistant liner (which can function as a resistor), final metal (LM) wiring levels and copper deposition and chemical mechanical polishing (CMP) steps to replace fuses, Lithographic patterning of one or more openings over the fuse, the method being exposed using an etchant that is selective to copper but does not attack the liner, such as aqueous ammonium phosphate and sulfuric acid, hydrogen peroxide and water Removing copper, depositing a resist and depositing a final passivation film, defining terminal metal contact holes in the final passivation film, and completing the processing as electrical testing and laser erasing of the fuse. Is composed of at least one of a segment of a liner and a segment of a copper LM line, wherein the copper LM Phosphorus segment is separated on at least one side by a "(only liner) only liner" structure.

The invention has the advantage that the laser erasing area is separated from the rest of the copper circuit by, for example, a link of fully passivated corrosion and fire resistant materials such as TaN / Ta. In one embodiment of the present invention, the fuse may be a TaN / Ta link portion, and in another embodiment, the fuse may be a TaN / Ta / Cu line portion of a suitable size adjacent to the TaN / Ta link. The structure of the present invention essentially eliminates the possibility of diffusion of erase fuse related corrosion to chip wiring or bridging of the erase region.

In the present invention, fully passivated corrosion resistant and fire resistant materials such as, for example, TaN / Ta links can be used as resistance. The resist structure has low capacitance, high resistance, and high linearity with respect to temperature and voltage, and is physically small and has a high melting temperature.

By having a high melt temperature Back End Of Line resistor (BEOL resistance) provided by a refractory metal, the present invention provides Electrostatic Discharge (ESD) protection.

The power to failure (P _f / A) of the interconnects is given by the square root of thermal conductivity (K), thermal capacity (C _p ) and mass density (ρ), as shown in Table 1 below. It is multiplied by the melting temperature (T _melting ) of the interconnect, which is in proportion to the value divided by the pulse width (τ ^1/2 ). Materials with higher melting temperatures (ie wiring) are more resistant to overvoltage and overcurrent protection and ESD events.

Table 1

By having the resistors in series with the sensing circuit, there is an advantage that the overvoltage of the peripheral circuit in the semiconductor chip can be prevented.

The present invention is a resistive structure disposed between pads and an ESD device. The device may also be physically a fuse.

Features of the present invention provide structures, methods, and circuit applications for applications that wish to be insensitive to voltage stress, Electrical OverStress (EOS) and Electrostatic Discharge (ESD) phenomena.

Another feature of the resistive element of the present invention is that it can be used for mixed voltage and analog / digital and mixed signal applications.

Another feature of the resistive element of the present invention when using a BEOL resistor is that the resistance has a low capacitance, and therefore, when it is a low capacitance material or silicon dioxide, it has a much lower capacitance than the silicon-based resist structure. .

Thus, another feature of the present invention is the use of interconnects and resistors.

Another characteristic of the resistance is that it increases ballasting at high currents as the interconnect temperature increases and the resistance increases (eg, R (T) = R0 (1 + αT)). Another advantage of Ta, in particular α-Ta, is that suitable sized resistors can be formed, for example 50 ohm resistors.

Typically resistors can be used for impedance matching and resistance ballasting. The concept of resistance ballasting is to have a multi-finger device, digitize it into a number of devices, and arrange the resistors in parallel. The present invention provides resistance ballasting in a multi-element cell that, when the resistors are placed in parallel, allows the placement of very high values of resistance to prevent electrical overload on one of the subcells.

A feature of the resistive element of the present invention is that it has a very low skin effect in relation to high frequency applications.

Another feature of the present invention is to provide a resistive element having a high critical current-density-to-failure (J _crit ) against failure.

The method of forming the resist structure may include a damascene process. The resistance corresponds to how the damascene structure is formed. For example, a damascene structure is formed in copper using a trough followed by refractory metal deposition. Embodiments of the present invention form a resistive element using a single damascene process. Another embodiment includes a single damascene process in which the resistor comprises a trough. Another embodiment includes a single damascene process in which the resistor includes a trough, a tungsten (W) contact, and a W membrane trough. Embodiments of the present invention form a resistive element using a dual damascene process. Another embodiment includes a dual damascene process in which the resistance includes troughs and vias. Another embodiment includes a dual damascene process in which the resistor comprises a trough, a via, and a second trough. Another embodiment includes a dual damascene process in which the resistance includes troughs, vias and second troughs, W contacts, and W membrane troughs.

Embodiments of the method of the present invention include forming a resistor by a damascene process, which includes defining a trough, depositing a high resistivity film, and depositing a second film. And polishing and etching away the second film to obtain a resist structure. In one embodiment of the invention, the first film may be tantalum, α-Ta, tantalum nitride or other liner / diffusion barrier material. In another embodiment of the present invention, the second film may be a conductive film such as, for example, copper.

Another embodiment of the method of the present invention includes forming a resistor by a dual damascene process, which includes defining troughs and vias, depositing a high resistivity film, and depositing a second film. And polishing and etching away the second film to obtain a resist structure. In one embodiment of the invention, the first film may be tantalum, tantalum nitride, or other liner / diffusion barrier material. In another embodiment of the present invention, the second film may be a conductive film such as, for example, copper.

Embodiments of the method of the present invention include forming a resistor by a damascene process, which includes defining a trough, depositing a high resistive film, depositing and polishing a dielectric film to resist resist structure Obtaining a step. In one embodiment of the invention, the high resistivity film may be tantalum, α-Ta, tantalum nitride, or other liner / diffusion barrier material.

Another embodiment of the method of the present invention forms a resistor by a dual damascene process, which defines a trough and via, and obtains a resist structure that deposits a high resistive film, deposits and polishes a dielectric film. It includes a step. In one embodiment of the invention, the first film may be tantalum, tantalum nitride, or other liner / diffusion barrier material.

In one embodiment of the invention, the resist structure may be a single trough. In other embodiments, the resist structure may comprise a single trough and via. In other embodiments, the resist structure may include a single trough, via, and W contact. In other embodiments, the resistor may include a single trough, via, trough, W via, and W film. In other embodiments, the resist structure may include a number of these exemplary resistive elements.

Other features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with reference to the accompanying drawings.

These and other features of the present invention will be described with reference to the accompanying drawings. In the drawings, like reference numerals generally refer to the same, functionally similar and / or structurally similar elements. In the drawings, the leftmost number of each reference number corresponds to the drawing in which the reference number was first used.

The present invention relates to a semiconductor integrated circuit (IC) chip that can be tailored to produce a fuse. The present invention also relates to a method of manufacturing an improved non-corrosive resistive structure.

1A-1G are cross-sectional views of an integrated circuit during fabrication of the metal structure of the present invention,

2 is a flow chart of exemplary process steps of the present invention;

3 is a plan view of a copper fuse in which copper is removed prior to cutting the fuse of the present invention;

4A and 4B are side cross-sectional views of structures of fire resistance, eg, TaN / Ta fuses of the present invention;

5 illustrates exemplary process steps of the present invention;

6 is a cross-sectional view of a diffused n-type conventional resist structure;

7A is a cross-sectional view of a damascene resistance structure including a trough of the present invention;

7B is a cross-sectional view of a dual damascene resistance structure comprising a trough, via hole, and a plurality of dual damascene membranes of the present invention;

FIG. 7C is another cross-sectional view of a dual damascene resistor structure including a trough, via hole, and insulator filled membrane of the present invention; FIG.

FIG. 7D is a cross sectional view of a dual damascene resistance structure including a trough, via hole, and a plurality of dual damascene membranes of the present invention; FIG.

8 is a cross-sectional view of a dual damascene resistance structure comprising a trough, via hole and a single trough of a single damascene of the present invention;

9 is a cross-sectional view of a double damascene resistance structure comprising a trough, via hole, a single trough of a single damascene, a tungsten (W) via, and a W membrane of the present invention;

10 is a flow chart illustrating an exemplary process of forming a resist structure of the present invention;

11 is a flow chart illustrating another embodiment of a process for forming a resist structure of the present invention;

12 illustrates an example circuit having a damascene resistor, an ESD network, and a peripheral circuit utilizing the present invention;

FIG. 13 shows an exemplary circuit having a damascene resistor (DR) as part of an RC triggered MOSFET network utilizing the present invention; FIG.

FIG. 14 shows an exemplary circuit having a damascene resistor as part of an RC triggered ESD power clamp, utilizing the present invention;

FIG. 15 illustrates an exemplary circuit illustrating W contacts in contact with a MOSFET in accordance with the present invention. FIG.

Preferred embodiments of the invention are described in detail below. Although specific embodiments have been described, it should be understood that such embodiments are for illustrative purposes only. Those skilled in the art will appreciate that other components and configurations may be possible without departing from the spirit and scope of the invention.

Overview of Present Invention

Laser erasing a metal fuse can corrode wiring conductors near the fuse. Part of the final metal (LM) line remains in the blown fuse, but is erased in the blown fuse to provide high resistance. A blown copper wiring fuse can cause corrosion by blocking or removing copper portions of adjacent wiring conductors. The fuse can be blown by irradiating an infrared (IR) laser to the metal line. The present invention eliminates the possibility of corrosion of the broken copper wiring fuse by blocking and / or removing the copper portion of the wiring conductor in the region between the fuse link and the remainder of the wiring. Copper (Cu) may be removed before the final passivation layer is deposited on the wafer and the final metal (LM) bond pads open. Prior to laser removal, the fuse link may remain electrically connected to the rest of the circuit by corrosion resistant tantalum nitride tantalum (TaN / Ta) deposited prior to copper deposition and damascene metal filling.

An exemplary manufacturing sequence for forming a fire resistant component barrier for fuse corrosion regrowth may include the following steps.

1. Using the lithographic patterning, etching, TaN / Ta liner deposition, copper deposition and chemical mechanical polishing (CMP) to substitute the final metal (LM) wiring level and fuse,

2. lithographic patterning one or more openings on the fuse;

3. removing the exposed copper using an etchant that is selective to copper and does not attack the liner, such as, for example, a water soluble hydroxide persulfate or a dilute mixture of sulfuric acid and hydrogen peroxide;

4. Complete the processing of removing the resist and depositing the final passivation film and defining terminal metal contact holes in the final passivation film; and

5. Electrically testing and laser removing the fuse, wherein the fuse comprises at least one of a segment of the liner and a segment of copper LM line separated on at least one side by a "liner only" structure. Said step.

1 shows a cross-sectional view of this structure described later.

Another exemplary manufacturing sequence for forming a fire resistant element is the following step, namely

1. lithographic patterning, etching, deposition of TaN / Ta liner, depositing copper and using chemical mechanical polishing (CMP) to machine the final metal (LM),

2. pretreatment with standard plasma followed by deposition of the barrier nitride layer;

3. patterning the wafer, opening the fuse window, etching the nitride and selectively etching copper to Ta;

4. Depositing the final passivation oxide / nitride, processing the wafer through a standard terminal via and blown with a laser.

3, 4A and 4B show several cross-sectional views of fabricating a structure using this method described below.

The present invention eliminates the possibility of a broken copper wiring fuse being corroded by removing copper from the fuse region before the final passivation layer is deposited on the wafer and the final metal (LM) bond pad is opened in the terminal via (TV) etch. This can be done by patterning the LM CMP, fuse window and adding an additional block mask level immediately after removing copper from the fuse. After copper removal, this final passivation can be deposited and a standard TV and fuse blow operation can be performed on the wafer.

An advantage of the present invention is that the laser erasure region is separated from the remainder of the copper circuit by a link of the fully passivated corrosion resistant TaN / Ta. In one embodiment of the present invention the fuse may be part of TaN / Ta, and in another embodiment the fuse may be part of a suitable size of TaN / Ta / Cu line adjacent to the TaN / Ta link. The structure of the present invention essentially eliminates the possibility that the removed fuse associated with corrosion will spread to the chip wiring or bridging in the removed area.

Another advantage of the present invention is that a fully passivated corrosion resistant TaN / Ta link can be used as the resistor. The resistive structure with low capacitance and high resistance is physically small and has a high melting point.

Examples of implementations of certain embodiments of the invention

1A-1G illustrate cross-sectional views of an integrated circuit during fuse manufacture of the present invention. FIG. 2 shows a flow chart 200 illustrating an example of a technique for manufacturing the structure shown in FIGS. 1A-1G.

Beginning at step 202 in FIG. 2 and proceeding straight to step 204. In step 204, a fuse line may be formed that includes a resist layer, an oxide layer, and a final metal minus 1 (LM-1) layer. Specifically, the fuse line is formed by disposing a resist layer over the previously deposited oxide layer. The oxide layer may include, for example, a material such as silicon dioxide, which is deposited over the previously deposited LM-1 layer using conventional methods such as, for example, plasma excited chemical vapor deposition (PECVD). An example of the structure formed in step 204 is shown in FIG. 1A.

FIG. 1A illustrates a semiconductor comprising resist segments 102a and 102b formed over an inner layer dielectric (ILD) oxide layer 106 that may in turn cover the final metal negative 1 (LM-1) layer segments 108a and 108b. The structure is shown.

From step 204, the flowchart 200 can proceed to step 206. In step 206, the oxide layer may be etched to create a “line-trench” and the resist layer may be stripped.

FIG. 1B shows the semiconductor structure of FIG. 1A etching the oxide layer 106 to produce an oxide layer 106a comprising a typical line trench and pedestal. Line trenches are formed in oxide layer 106a by stripping resist segments 102a and 102b. LM-1 segments 108a and 108b remain covered by oxide ILD layer 106a.

From step 206, the flowchart 200 can proceed to step 208. In step 208, a resist may be applied and a mask or reticle over the resist may be used to open the image so that the via holes do not cover the portion desired to be connected to the LM-1 layer wiring. The resulting structure of this material is shown in Figure 1c.

1C will apply resist segments 110a, 110b, 110c, and will protect the walls of the trench, as well as via holes through the ILD oxide 106a to the LM-1 segments 108a, 108b. The semiconductor structure of FIG. 1B is followed by opening an image mask over oxide 106a leaving the intended portion unprotected.

The photoresist can be dispensed with the wafer stopped or rotated. Uniform resist thickness is preferred.

After the resist coating is completed, the wafer can be transferred to a softbake station that can be baked by direct conduction at a specific temperature and time.

The resist film is sensitive to ultraviolet light (UV) of a specific wavelength. The wafer / resist combination may be inserted into a mask aligner, which may include optics, UV light sources, and circuit layer images contained on the mask or reticle, which circuit layer images may be incorporated into the resist film. Will be killed.

The development step may form a mask image by selectively removing exposed (or unexposed) areas of the positive (or negative) photoresist film. The wafer can be cassette loaded onto a developer / hardbake track and transferred to a developing station. The developing solution may be dispensed so that the wafer is immersed, the wafer may remain idle while the developing procedure is in progress, and then the spin / rinse cycle may complete the process. Another technique may use a temperature controlled bath in which the wafer is batch developed using agitation.

Flowchart 200 may continue from step 208 to step 210. In step 210, the oxide layer is selectively etched to make via holes to the LM-1 layer in the oxide layer, and then the resist layer can be removed. The resulting structure formed by step 210 is shown in FIG. 1D.

The patterned photoresist may expose the underlying material to be etched. Photoresists are implant beams when used as implant masks, as well as wet (acid) and dry (plasma or reactive ion etching (RIE)) etching environments with good adhesion and image continuity. It can be strong enough to stand the power of.

Resist stripping may include completely removing the photoresist after the masking process to prevent contamination in subsequent processes. Many photoresist solvent (premixed) strippers are available for removing positive and negative photoresist (+ PR and -PR) without adversely affecting the underlying material. Temperature controlled baths can be used for batch stripping of the photoresist and subsequent proper rinsing. Ozone plasma (O ₃ ) may also be effective to remove the photoresist.

1D forms oxide segments 106b, 106c and 106d that are etched oxide 106a and stripping resist segments 110a and 110b and separated by etched via holes to LM-1 wiring segments 108a and 108b. After that, the semiconductor structure of FIG. 1C is shown.

Flowchart 200 may continue from step 210 to step 212. In step 212, a liner is deposited, filling trenches and via holes with copper metal using a damascene metallization process, and the damascene fuses can be imaged. Metals are used in semiconductor processing to make low resistance paths. The metal may be deposited by a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) sputtering process. For example, using CVD, WF ₆ can be used to deposit W. Copper may be deposited by sputtering processes or electroplating. Physical vapor deposition can be accomplished by evaporation metallization processes and sputter deposition processes. Copper deposition can be performed using Ta or TaN as a liner or barrier layer between Cu and Si. The resulting structure following damaging the trenches and vias formed in step 212 with copper is shown in FIG. 1E.

FIG. 1E illustrates the semiconductor structure of FIG. 1D after depositing a liner in the trench and metal filling the vias for the LM-1 segments 108a, 108b formed by the trench and oxide segments 106a, 106b, 106d.

Flowchart 200 continues from step 212 to step 214. In step 214, a resist is applied and a fuse corrosion isolation trench can be imaged to allow etching of the metal layer. The resulting structure formed in step 214 is shown in FIG. 1F.

FIG. 1F illustrates the semiconductor structure of FIG. 1E after imaging of the resist leaving a portion of the damascene charge fuse 114 unprotected, wherein a portion of this damascene charge fuse 114 is etched to form a fuse corrosion blocking trench. something to do. Resist segments 112a, 112b, 112c protect lower fuse 114 and oxide portions 106a, 106d.

From step 214, the flowchart 200 can continue to step 216. In step 216, the damascene fuse 114 is etched by using an etchant that is selective to copper and does not attack the liner to form a corrosion barrier trench in the metal fuse, and the resist may be stripped. For example, various etching techniques can be used, including wet etching and dry etching. Wet etching may utilize various mixtures of hydrofluoric acid and water (eg, 10: 1, 6: 1, 100: 1) and may include buffers such as ammonium fluoride for slower and better controlled etch rates. Wet etching is relatively inexpensive, but can also result in severe undercutting because it is an isotropic process, ie, proceeding at about the same rate in all directions, which can be impractical. To avoid this erosion, the very anisotropic (i.e., directional) etching feature useful for high density circuits using dry or plasma etching techniques, for example, ionizing (i.e., reactive ion etching (RIE) physical sputtering) refractory gases using glow discharge. Can be set. If the dry etching process involves multiple layers, such as silicon nitride over silicon dioxide, it is important to know the relative etch rates of these two materials in the soluble etchant. This "selectivity" determines whether significant etching of underlying layers will occur. Plasma etching processes are inherently chemical in nature and thus exhibit good selectivity over RIE physical sputtering processes. The resulting structure formed by step 216 is shown in FIG. 1G. The flow chart from step 216 may end immediately to step 218.

In FIG. 1G, the copper metal fuse is etched using an etchant that is selective for copper and does not attack the liner, and then strips the resist portions 112a, 112b, 112c to rest the TaN / Ta liner segments 114b, 114d. Alternatively, the semiconductor structure of FIG. 1F is shown, leaving a thin corrosion blocking trench portion of the stub and copper segments 114a, 114c, 114e. TaN / Ta stubs 114b and 114d are left exposed to the environment and do not corrode. Thus, rather than merely creating a single resistive element (described in more detail with respect to FIGS. 7-15), FIGS. 1A-1G show fuses having non-corrosive liners 114b and 114d on each side of the fuse. Forming 114c). Liner stubs 114b and 114d remain after laser ablation of fuse line 114c (also remove liner under segment 114c). Since the stubs 114b and 114d are made of the liner material TaN / Ta, i.e. relatively high resistance and fire resistance, they do not corrode and thus no regrowth across the area where the fuse link 114c previously existed can occur. . Resistant noncorrosive materials can be used as resistors as described in more detail below with reference to FIGS. 7 to 15. The noncorrosive properties, ie fire resistance properties of liner materials such as Ta, α-Ta and TaN, make this material a good resistance. In particular, if the material is instead corrosive, the resistivity changes with corrosion of the material and thus is not useful as a resistance.

3 shows a top view 300 of a copper fuse with copper removed prior to cutting the fuse of the present invention. Top view 300 illustrates fuse bay 302 and fuse 306 and via hole 304.

4A and 4B show cross-sectional views of the structure shown in FIG. 3. 4A is a cross-sectional view that includes a TaN / Ta fuse 306, via holes 304a and 304b referred to as bomb shelter, TaN / Ta / Cu portions 402a and 402b and dielectric 2 404. 400). 4B is a cross-sectional view 410 including a TaN / Ta fuse 306, dielectric 1 408 and dielectric 2 404.

5 is a flow diagram 500 of the steps of an exemplary manufacturing sequence. The flow chart can begin with step 502 and begin immediately with step 504.

In step 504, flow chart 500 illustrates a final metal (LM) wiring level using lithography patterning, etching, deposition of TaN / Ta liners, deposition of copper, and chemical mechanical polishing (CMP). And replacing the fuse is illustrated. Flowchart 500 may continue from step 504 to step 506.

In step 506, the flowchart 500 illustrates depositing a barrier nitride layer that may follow a standard plasma pretreatment step. Flowchart 500 may continue from step 506 to step 508.

In step 508, the flowchart 500 illustrates the step of patterning the wafer, opening the fuse window, etching the nitride and selectively etching copper for Ta. From step 508 the flowchart 500 can continue to step 510.

In step 510, flowchart 500 illustrates depositing the final passivation oxide / nitride, processing the wafer through standard terminal vias and laser cutting the fuse. Flowchart 500 may continue from step 510 to step 512. In step 512, the flowchart 500 may end.

The present invention eliminates the possibility that the cut copper wiring fuses will corrode by removing copper from the fuse area before the final passivation layer is deposited on the wafer and the final metal (LM) bonding pads are opened with terminal via (TV) etching. This can be done by patterning the LM CMP fuse window and adding an additional block mask level immediately after removing copper from the fuse. After copper removal, the final passivation can be deposited and the wafer can be run through standard TV and fuse cutting operations.

6 shows a cross section of a diffused n-type resist structure 600 of the prior art. Resistor structure 600 includes an n-type diffusion resistor 602 separated from an n-type substrate by p-type isolation region 604. On the diffused n-type diffusion resistor 602, interconnects 606a, 606b separated by insulator segments 608a, 608b, 608c are deposited. Prior art resistors 602, which are typically used for resistance ballasting, suffer from the disadvantages of high capacitance, leakage, and temperature characteristics of silicon itself, and there may be breakdown in the substrate.

7A shows a cross-sectional view 700 of an exemplary anti-machine resistance structure including a trough of the present invention. Specifically, cross-sectional view 700 includes a trough 702 surrounded by insulator portions 704a, 704b, 706a, 706b. Cross-sectional view 700 includes a back end of line (BEOL) insulator, which may be a low K material, for example silicon dioxide. The trench can be formed, for example, by dry etching and standard back end processing. The liner material can then be placed after the adhesive film, for example tantalum nitride, and subsequent tantalum film. Copper may be deposited inside the cavity of the trench. In an embodiment of the invention, copper may be removed through the window. The trench of the trough 702 may be refilled with the insulator 708, for example, or may be left in the air. Copper is removed to provide high material resistance. Liners such as Ta, α-Ta, TaN act as effective resistive structures (see FIG. 7B). The tantalum film may be of a single damascene or double damascene structure as shown in FIG. Copper also has a lower melting point than tantalum films, so failures can be more likely to occur when the structure is further heated. Thermal properties vary depending on the filler. It will be apparent to those skilled in the art that the insulators 706a and 706b may comprise other materials, such as, for example, metal or dielectric layers. By filling the trench with a high dielectric material, ESD toughness is increased. The power to failure of the insulators increases the toughness against the air. The advantage of air is that it is non-corrosive and consumes heat by thermal transfer to the top layer or top region.

On the heat diffusion time side, when the volume of the trench 702 is refilled with the insulator 708, the power to failure is improved as compared to the case of air according to the fact that the insulator is present in the volume, which is formed by the insulator. Thermal sheaths are useful. Thermal properties can vary depending on whether the cavity is filled or left unfilled. Other low capacitance (K) materials or SiO ₂ may be used. When refilled with a high dielectric material, such as SiO ₂ , the thermal toughness of the resistance is enhanced and the ESD toughness is enhanced. In the case of air, this is physically low. When filled with a high K dielectric material, there is a high toughness power for failure, i.e. a high threshold current for failure. Instead of filling the trench with copper, the use of an insulator results in high resistance and a lower melting point. Trench 702 may be made of TaN / T film material, the same liner material used to form the non-corrosive fuse described with reference to FIGS. 3, 4A, 4B.

FIG. 7B shows a cross-sectional view 710 of an exemplary dual damascene resistance structure consisting of a trough, via hole, and a plurality of dual damascene membranes of the present invention. In particular, the cross-sectional view 700 is a double damascene resistance structure 702 including a trough 702 composed of a double damascene film 702 such as a tantalum film and a resistive film, and via holes 712 and 714, for example. ). Other materials may be included in the layer, such as insulators 706a and 706b.

7C shows a cross section of a double damascene resistance structure 702 consisting of a trough 702 filled with insulator 708 with a trough of a film, a via 714 filled with an insulator 716, and a via film. 720 is shown.

FIG. 7D shows a side cross-sectional view 722 of a plurality of membranes, ie, a plurality of single damascene membranes or a plurality of dual damascene membranes forming a plurality of resistors in parallel. In particular, in one embodiment, the side cross-sectional view 722 includes a double damascene resistance structure consisting of a trough 702a comprising a plurality of dual damascene films 726a, 726b and via holes 712a, 712b. . As shown, trough 702a may be filled with insulator 726a and copper segments 718, and vias 714a and 712a may be filled with insulator 716d and insulator 708c, respectively. Each insulator segment of the trough and via acts as a resistive element shown by resistors 724a, 724b, 724c.

8 shows a preferred cross-sectional view 800 of an exemplary resist structure consisting of a double dammer trough 802 of an upper layer and a single damsel single trough 810 of a bottom layer connected by a via hole 806. Here copper is removed to form a cavity, for example an oxide can be used to fill the cavity. The double machine trough 802 may be filled with an oxide material 804. The single machine trough 810 includes an insulator fill 812 and a copper portion 814 that connects the insulator 812 to the via 806, which in turn is an oxide fill 808. Can be filled with). Like the connection of two resistors 816a and 816b connected in series, a good conductor, copper 814, connects the insulator 812 and the oxide 808. Oxide 804 acts as resistor 816c as shown.

FIG. 9 illustrates an intermediate dammer 910 by a top trough 902 connected by a via hole 906, a single trough 910 of an intermediate layer, and a via 918 that may include a tungsten filler. A preferred cross-sectional view 900 of an exemplary dual damascene resistor structure, consisting of a tungsten (W) MO wiring layer 920, is shown. Since tungsten (W) has a high melting point, it can be used as a local interconnect as compared to silicon dioxide, ie in the so-called MO local interconnect layer on the silicon surface. Tungsten material can be used as a resistor in parallel with other resistive materials. Thus, a series of a plurality of refractory material surfaces can be used to form a resist structure on a plurality of levels. The double machine trough 902 may be filled with an oxide material 904. The single machine trough 910 may include an insulation fill 912 and a copper portion 914 that connects the insulator 912 to the oxide fill 908 of the via 906. Like the connection of the two resistors 916a and 916b connected in series, a good conductor copper 914 may connect the insulator 912 and the oxide 908. Oxide 904 may act as resistor 916c as shown.

10 is a flow diagram 1000 illustrating a preferred process for forming a resist structure in one embodiment of the present invention.

Flowchart 1000 may begin at step 1002 and continue directly to step 1004.

In step 1004, an oxide layer may be deposited. It may continue from step 1004 to step 1006 in flowchart 1000.

In step 1006, the trenches or trenches and vias may be etched into the predeposited oxide layer to form trench 702 from above. It may continue from step 1006 to step 1008 in flowchart 1000.

In step 1008, a liner may be deposited. It may continue from step 1008 to step 1010 in flowchart 1000.

In step 1010, a copper metal layer may be deposited. It may continue from step 1010 to step 1012 in flowchart 1000.

At step 1012, the window can be opened and the copper can be etched. In flowchart 1000, operation may continue from step 1012 to step 1014.

In step 1014, the final structure can be polished to planarize the final metal structure. In flowchart 1000, operation may continue from step 1014 to step 1016.

At step 1016, it may be determined whether another layer is to be deposited. If another layer is to be deposited, then the flow chart can continue to step 1004. If there are no other layers to be deposited, then flow continues from step 1016 to step 1018 in flowchart 1000.

11 is a flow chart 1100 illustrating another preferred process of forming the resist structure of another embodiment of the present invention.

Flowchart 1100 may begin with step 1102 and continue to step 1104 directly.

In step 1104 an oxide layer may be deposited. Flowchart 1100 may continue from step 1104 to step 1106.

In step 1106, troughs or trenches and vias may be etched into the predeposited oxide layer to form the trenches 702 described above. Flowchart 1100 may continue from step 1106 to step 1108.

In step 1108, a liner may be deposited. Flowchart 1100 may continue from step 1108 to step 1110.

In step 1110, the region may be filled with an oxide dielectric. Flowchart 1100 may continue from step 1110 to step 1112.

In step 1112, the final structure can be polished to planarize the final metal structure. Flowchart 1100 may continue from step 1112 to step 1114.

At step 1114, it may be determined whether another layer is to be deposited. If another layer is to be deposited, then the flow chart can continue to step 1104. If there are no other layers to be deposited, then flow diagram 1100 may continue from step 1114 to step 1116.

Thus, the cavity may be left open with air and remain as a fuse structure as described with reference to FIG. 1 above, or may be refilled with oxide for multiple layers of structures, causing another layer to be deposited thereon.

12 illustrates a pad connected to an ESD device 1204 (ie, a dual diode circuit including diodes 1206 and 1208), a damascene resistor structure 1210, and a peripheral I / O network circuit 1212 for use in the present invention. An example circuit 1200 is shown that includes 1202. The dam machine wiring resistor 1210 includes a single damascene or a double damascene refractory metal film resistor structure as described above.

In another embodiment of the present invention, the peripheral I / O network circuit 1212a connected to the ESD device 1204b, the damascene resistor structure 1210a, and the damascene resistor structure 1210a are connected to the ESD device 1204b. An example circuit 1220 is shown that includes an ESD device 1210a and a pad 1202a coupled with the ESD device 1210a.

In another embodiment of the present invention, the pad 1202b connected to the dual damascene resistor structure 1210a connected to the ESD device 1204c and the peripheral I / O network circuit 1212b connected to the ESD device 1204c are An example circuit 1230 is shown that includes. This embodiment has the advantages of ring back, noise reflection, and is useful for braking mechanisms.

Another embodiment of the present invention includes a pad 1202c connected to an ESD device 1204d connected to the damascene resistance structure 1210c, and a peripheral I / O circuit 1212c connected to the damascene resistor 1210c. Exemplary circuit 1240 is shown. Those skilled in the art will appreciate that the circuit 1200 is a specific example of the general circuit 1240.

Another embodiment shows an example circuit 1250 that includes a pad 1202d coupled with an ESD circuit 1204e.

13 shows an example circuit 1300 that includes a damascene resistor 1310 as part of an ESD circuit. Exemplary circuit 1300 represents a damascene resistor 1310 as part of an RC triggered MOSFET network. The circuit 1300 has a pad 1302 connected to a plate of a capacitor 1314 which is connected to both the one terminal of the grounded machine resistor 1310 (see ground 1318a) and the gate of the MOSFET 1316 on both sides. Where the source of MOSFET 1316 is connected to ground 1318b and the drain of MOSFET 1316 is connected to pad 1302. Another embodiment 1320 shows a charge resistance (DR) 1310a connected to both the pad 1302 and a plate of grounded capacitor (C) 1314a (connected to ground 1318c). Referring collectively to DR and C 1324, DR 1310a and C 1314a connected to another have a p-type MOSFET whose source is connected to pad 1302a and its drain is grounded to ground 1318d. Also connected to the gate of (PFET) 1322.

FIG. 14 shows an example circuit 1400 coupled to an ESD circuit 1404 and including a damascene resistor as part of an RC triggered ESD power clamp that includes DR and C 1424, where ESD Circuit 1404 is connected to V _dd 1402a and V _ss 1402b.

In general, the wiring resistance can be used as a circuit element for the ESD circuit as a circuit element in the core of the chip in the peripheral circuit and the ESD network.

FIG. 15 shows an example circuit 1500 that includes a damascene resistor 1508 on contact level in series with a MOSFET to provide local resistance ballasting for contact holes. Trench 1508 indicates etching from copper wire and liner 1512 and is filled with insulator 1510. The trench 1508 is connected to the MOSFET by a via of W 1506 and is also known as a plug. The MOSFET includes n-type regions 1502a and 1502b and a polysilicon portion 1504. 15 includes an example circuit having a multi-finger MOSFET structure. The MOSFET can be, for example, a MOSFET driver or a pull-down transistor in an ESD network. By adding a local resistive element on the contact level, the present invention can of course include a plurality of NFETs that provide parallel resistance to only a single finger MFET and also provide resistance ballasting in its dimensions if replicated. Exemplary circuit schematic block diagram 1520 includes pads 1514a connected to sources of MOSFETs 1518a and 1518b interconnected by DRs 1516a and 1516b, respectively. MOSFETs 1518a and 1518b are interconnected. In another embodiment, exemplary circuit schematic block diagram 1530 includes a pad 1514b coupled to source nodes of MOSFETs 1518c, 1516d, and 1518e. The drain nodes of MOSFETs 1518c, 1518d, and 1518e are interconnected with DRs 1516c, 1516d, and 1516e, respectively. Gates of the MOSFETs 1518c, 1518d, and 1518e are interconnected. Each MOSFET 1518c, 1518d, 1518e and the DR 1516c, 1516d, 1516e associated with it are optionally applied as a finger 1522. The present invention can be used in high current phenomenon.

Physical structure of the fuse and how to wire the fuse to protect against electrostatic discharge (ESD)

The use of the present invention for fuses is known as personalization or draws out a circuit. The application of the present invention to ESD is intended to avoid current overload of the network. As described above with reference to FIGS. 1 to 5, the present invention creates a trough in the oxide and produces refractory metals such as tantalum nitride / tantalum and copper oxide. The rough is filled and then a portion of the copper is etched away to form a short segment that is only TaN / Ta, for example the resistors of FIGS. 7-15, forming a resistive structure. It is useful to use fuses as this eliminates the possibility of corrosion of the removed copper wiring. When the laser erases a segment of a copper fuse line associated with the liner, the end of the cut may still have copper exposed to the atmosphere, for example. Copper is very reactive and can corrode too easily. Corrosion mechanisms for copper are typically dendritic growth, allowing unwanted reconnection of fuses. In order to avoid corrosion at this time, the present invention can make the exposed portion of the blown fuse non-reactive TaN / Ta.

While various embodiments of the invention have been described above, these are merely illustrative and are not restrictive. Thus, the breadth and scope of the present invention should not be limited by any of the above-described embodiments, but may be defined only in accordance with the following claims and the like.

Claims (37)

A metal structure formed in a trough on a semiconductor substrate, the trough having sides, bottoms, and ends; A first part of the structure consisting of a first layer and a second layer, wherein the first layer of the trough is formed at the side, bottom and end, the first layer having a higher electrical resistance than the second layer Wherein the second layer has horizontal and vertical surfaces in contact with the first layer in the first portion; (Ii) comprising a second portion of said first layer adjacent to said first portion and connected to said first portion, The first layer in the second portion does not contact the horizontal and vertical surfaces of the second layer in the second portion. Metal structures. The method of claim 1, And the first layer has a non-corrosive property that prevents regrowth of a blown fuse. The method of claim 1, And the first layer comprises a liner material. The method of claim 1, And the first layer comprises a refractory material. The method of claim 4, wherein The refractory material includes at least one of Ta, α-Ta, TaN, and TaN / Ta. The method of claim 1, And the first layer functions as a resistor. delete delete delete delete A metal structure formed in a trough on a semiconductor substrate, the trough having sides, bottoms, and ends; ① a refractory material deposited on at least the side and bottom of the trough, A non-refractory conductive material filling at least one end of the trough and in contact with only a portion of the refractory material in the trough; Metal structures. The method of claim 11, The metal structure further comprises interlevel vias in contact with the trough. delete The method of claim 11, The refractory material functions as a noncorrosive liner to prevent regrowth of a blown fuse. delete A method for forming a fire resistant element barrier to fuse corrosion regrowth, ① using the lithographic patterning, etching, liner deposition, copper deposition and chemical mechanical polishing (CMP) to substitute the final metal (LM) wiring level and fuse, (2) applying resist and lithographic patterning one or more openings on the fuse; (3) removing the exposed copper using an etchant selective to the exposed copper, wherein the etchant does not attack the liner; (4) removing the resist to deposit the final passivation film, and defining terminal metal contact holes in the final passivation film; ⑤ electrically testing and removing the fuse with a laser; The fuse comprises at least one of a liner segment and a copper LM line segment separated by a “liner only” structure on at least one side. A method of forming a fire resistant element barrier. delete delete The method of claim 16, Wherein said etchant is optional for said line and said etchant comprises at least one of a mixture of water soluble ammonium persulfate and dilute sulfuric acid with hydrogen peroxide. As a method for forming a fire resistant element, (1) using lithographic patterning, etching, fire resistant liner deposition including at least one of Ta, α-Ta, TaN, and TaN / Ta, deposition of copper, and chemical mechanical polishing (CMP), Replacing the fuse, (2) depositing a barrier nitride layer after performing pretreatment with a standard plasma; (3) patterning a wafer, opening a fuse window, etching the barrier nitride, and etching the copper, wherein the etchant is optional for the fire resistant liner; (4) depositing a final passivation oxide / nitride layer, processing the wafer through standard terminal vias, and cutting the fuse with a laser Method for forming fire resistant element. delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete