JP2005524906A - 少なくとも１つの組込型マイクロプロセッサコアを有するフィールドプログラマブルゲートアレイ制御要素を組込んだ適応プロセッサアーキテクチャ - Google Patents

少なくとも１つの組込型マイクロプロセッサコアを有するフィールドプログラマブルゲートアレイ制御要素を組込んだ適応プロセッサアーキテクチャ Download PDF

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JP2005524906A
JP2005524906A JP2004504121A JP2004504121A JP2005524906A JP 2005524906 A JP2005524906 A JP 2005524906A JP 2004504121 A JP2004504121 A JP 2004504121A JP 2004504121 A JP2004504121 A JP 2004504121A JP 2005524906 A JP2005524906 A JP 2005524906A
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computer system
processor element
processor
user
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JP2005524906A5 (https=
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ハッペンタール，ジョン・エム
ケラム，デニス・オー
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エス・アール・シィ・コンピューターズ・インコーポレイテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Logic Circuits (AREA)
JP2004504121A 2002-05-09 2002-12-03 少なくとも１つの組込型マイクロプロセッサコアを有するフィールドプログラマブルゲートアレイ制御要素を組込んだ適応プロセッサアーキテクチャ Withdrawn JP2005524906A (ja)

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US10/142,045 US20030212853A1 (en) 2002-05-09 2002-05-09 Adaptive processor architecture incorporating a field programmable gate array control element having at least one embedded microprocessor core
PCT/US2002/038844 WO2003096195A1 (en) 2002-05-09 2002-12-03 Adaptive processor architecture incorporating a field programmable gate array control element having at least one embedded microprocessor core

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JP2005524906A true JP2005524906A (ja) 2005-08-18
JP2005524906A5 JP2005524906A5 (https=) 2006-01-19

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JP2004504121A Withdrawn JP2005524906A (ja) 2002-05-09 2002-12-03 少なくとも１つの組込型マイクロプロセッサコアを有するフィールドプログラマブルゲートアレイ制御要素を組込んだ適応プロセッサアーキテクチャ

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US (2) US20030212853A1 (https=)
EP (1) EP1502190A1 (https=)
JP (1) JP2005524906A (https=)
AU (1) AU2002360486A1 (https=)
CA (1) CA2483541A1 (https=)
WO (1) WO2003096195A1 (https=)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4571454B2 (ja) * 2004-07-16 2010-10-27 株式会社アドバンテスト 半導体集積回路
DE602005009801D1 (de) * 2005-04-11 2008-10-30 St Microelectronics Srl Ein dynamisch rekonfigurierbares System auf einem Chip, welches eine Vielzahl rekonfigurierbarer Gate-Arrays beinhaltet.
WO2008061162A1 (en) * 2006-11-14 2008-05-22 Star Bridge Systems, Inc. Hybrid computing platform having fpga components with embedded processors
US8332610B2 (en) * 2007-04-17 2012-12-11 Marvell World Trade Ltd. System on chip with reconfigurable SRAM
CN102799559B (zh) * 2012-07-27 2015-12-02 浪潮(北京)电子信息产业有限公司 一种验证系统和拓扑结构的建立方法
CN103419201B (zh) * 2013-08-19 2015-07-08 电子科技大学 基于fpga的多指节机器人控制系统及其控制方法
JP6205654B2 (ja) 2015-04-07 2017-10-04 エスゼット ディージェイアイ テクノロジー カンパニー リミテッドＳｚ Ｄｊｉ Ｔｅｃｈｎｏｌｏｇｙ Ｃｏ．，Ｌｔｄ 画像処理方法及び画像処理装置
CN106648507B (zh) * 2016-12-05 2020-02-14 中国航空工业集团公司洛阳电光设备研究所 一种用于嵌入式处理器扩展dvi显示输出的电路及方法
TWI638442B (zh) * 2017-05-26 2018-10-11 瑞昱半導體股份有限公司 電子裝置及其電路基板
CN108776644B (zh) * 2018-05-04 2022-09-27 中国电子科技集团公司第三十六研究所 一种数据高速缓存系统、方法和航天用电子设备
CN110059049A (zh) * 2019-03-27 2019-07-26 中国计量大学上虞高等研究院有限公司 一种实时存储装置
CN112068467B (zh) * 2020-08-24 2022-01-14 国微集团(深圳)有限公司 数据传输系统、数据存储系统
CN113569525B (zh) * 2021-06-24 2024-07-23 合肥松豪电子科技有限公司 一种利用sram在fpga验证平台上的验证模型及方法
US12430270B1 (en) * 2024-11-26 2025-09-30 Texas Milkyway Inc. Multi-port SRAM system for a distributed memory pool

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE68920388T2 (de) * 1988-09-19 1995-05-11 Fujitsu Ltd Paralleles Rechnersystem mit Verwendung eines SIMD-Verfahrens.
US5802290A (en) * 1992-07-29 1998-09-01 Virtual Computer Corporation Computer network of distributed virtual computers which are EAC reconfigurable in response to instruction to be executed
US6052773A (en) * 1995-02-10 2000-04-18 Massachusetts Institute Of Technology DPGA-coupled microprocessors
US5570040A (en) * 1995-03-22 1996-10-29 Altera Corporation Programmable logic array integrated circuit incorporating a first-in first-out memory
US5903771A (en) * 1996-01-16 1999-05-11 Alacron, Inc. Scalable multi-processor architecture for SIMD and MIMD operations
US5737766A (en) * 1996-02-14 1998-04-07 Hewlett Packard Company Programmable gate array configuration memory which allows sharing with user memory
US5744980A (en) * 1996-02-16 1998-04-28 Actel Corporation Flexible, high-performance static RAM architecture for field-programmable gate arrays
US5892962A (en) * 1996-11-12 1999-04-06 Lucent Technologies Inc. FPGA-based processor
US6226776B1 (en) * 1997-09-16 2001-05-01 Synetry Corporation System for converting hardware designs in high-level programming language to hardware implementations
US6052327A (en) * 1997-10-14 2000-04-18 Altera Corporation Dual-port programmable logic device variable depth and width memory array
US6076152A (en) * 1997-12-17 2000-06-13 Src Computers, Inc. Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem
US6339819B1 (en) * 1997-12-17 2002-01-15 Src Computers, Inc. Multiprocessor with each processor element accessing operands in loaded input buffer and forwarding results to FIFO output buffer
US6414391B1 (en) * 1998-06-30 2002-07-02 Micron Technology, Inc. Module assembly for stacked BGA packages with a common bus bar in the assembly
US6192439B1 (en) * 1998-08-11 2001-02-20 Hewlett-Packard Company PCI-compliant interrupt steering architecture
JP2000183037A (ja) * 1998-12-11 2000-06-30 Tokyo Electron Ltd 真空処理装置
JP3616518B2 (ja) * 1999-02-10 2005-02-02 日本電気株式会社 プログラマブルデバイス
US6339818B1 (en) * 1999-06-24 2002-01-15 International Business Machines Corporation Method and system for dynamically locating frequently accessed memory regions or locations
US6496971B1 (en) * 2000-02-07 2002-12-17 Xilinx, Inc. Supporting multiple FPGA configuration modes using dedicated on-chip processor
US6877044B2 (en) * 2000-02-10 2005-04-05 Vicom Systems, Inc. Distributed storage management platform architecture
US6874043B2 (en) * 2000-10-17 2005-03-29 Bridgeworks Ltd. Data buffer
US6441483B1 (en) * 2001-03-30 2002-08-27 Micron Technology, Inc. Die stacking scheme

Also Published As

Publication number Publication date
WO2003096195A1 (en) 2003-11-20
US20050257029A1 (en) 2005-11-17
CA2483541A1 (en) 2003-11-20
AU2002360486A1 (en) 2003-11-11
EP1502190A1 (en) 2005-02-02
US20030212853A1 (en) 2003-11-13

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