Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F15/00—Digital computers in general; Data processing equipment in general
  • G06F15/76—Architectures of general purpose stored program computers
  • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
  • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

Definitions

• the present invention relates, in general, to the field of adaptive or reconfigurable processors. More particularly, the present invention relates to a multi-adaptive processor ("MAPTM", a trademark of SRC Computers, Inc., assignee of the present invention) element architecture incorporating a field programmable gate array (“FPGA”) control element having at least one embedded processor core.
• MAPTM multi-adaptive processor
• FPGA field programmable gate array
• Adaptive processors are processor elements that have the ability to alter their hardware functionality based on the program they are running. When compared to a standard microprocessor that can only sequentially execute pre-implemented logic, the adaptive processor has the ability to perform thousands of times more efficiently on a given program. When the next program is run, the logic is reconfigured via software, to again perform very efficiently.
• the integrated circuits used in these adaptive processors have historically fallen into two categories, namely the custom coprocessor application specific integrated circuits ("ASICs”), and the FPGAs.
• ASICs application specific integrated circuits
• a multi-adaptive processor element architecture incorporating an FPGA control element which may have at least one embedded processor core.
• the overall architecture has as its primary components three FPGAs, DRAM and dual-ported SRAM banks, with the heart of the design being the user FPGAs which are loaded with the logic required to perform the desired processing.
• Discrete FPGAs are used to allow the maximum amount of reconfigurable circuitry and, in a particular embodiment disclosed herein, the performance of the multi-adaptive processor element may be further enhanced by preferably using two such FPGAs to form a user array.
• the two user FPGAs of the user array can be set up as mirror-image functional pin configurations. This eliminates most of the chip-to-chip routing that would otherwise be required for their interconnection to the degree necessary to allow them to function as effectively one larger device. Further, in this manner the circuit board layer count and cost is also minimized. This mounting technique also permits the effective use of the largest pin count packages available which will maximize the I/O capability of the user array.
• the dual-ported SRAM banks are used to provide very fast bulk 5 memory to support the user array.
• discrete SRAM chips may be arranged in multiple, independently connected banks. This provides much more capacity than could be achieved if the SRAM were only integrated directly into the FPGAs.
• I/O input/output
• the high volume DRAM is "read” using its fast sequential burst modes and the lower capacity SRAM banks are then randomly loaded 5 allowing the user FPGAs to experience very high random access data rates from what appears to be a very large virtual SRAM. The reverse also happens when the user FPGAs are "writing" data to the SRAM banks.
• These overall control functions may be managed by an on-chip DMA engine that is implemented in the control FPGA.
• an adaptive processor element for a computer system comprising a first control FPGA; a system interface bus coupled to the control FPGA for coupling the processor element to the computer system; dynamic random access memory (DRAM) coupled to the control FPGA; dual-ported static random access memory (SRAM) having a first port thereof coupled to the control FPGA; and a user array comprising at least one second user FPGA coupled to a second port of the dual-ported 5 SRAM.
• DRAM dynamic random access memory
• SRAM static random access memory
• Various computer system implementations of the adaptive processor element of the present invention disclosed herein are also provided. In each of the possible system level implementations, it should be noted that, while a microprocessor may be used in conjunction with the adaptive processor element(s), it is also possible to construct computing systems using only 0 adaptive processor elements and no separate microprocessors.
• an adaptive processor using a discrete control FPGA having embedded processors, a system interface, a peripheral interface, a connection to discrete DRAM and a connection to one port of discrete dual ported SRAM, as well as discrete FPGAs forming a user array, 5 with connections between the FPGAs forming the user array and to a second port of the dual ported discrete SRAM as well as chain port connections to other adaptive processors.
• the adaptive processor may comprise multiple discrete FPGAs coaxially located on opposite sides of a circuit board to provide the largest possible user array and highest bandwidth, while o minimizing chip to chip interconnect complexity and board layer count. Dual- ported SRAM may be used and connected to the control chip and user array in conjunction with DRAM connected to the control chip, to form high speed circular transfer buffers.
• An adaptive processor as previously described may further comprise 5 an embedded processor in the control FPGA to create a high speed serial I/O channel to allow the adaptive processor to directly connect to peripheral devices such as disk drives for the purpose of reducing the bandwidth needed on the system interface. It may further comprise logic implemented in the control FPGA to create a high speed serial I/O channel to allow the adaptive o processor to directly connect to peripheral devices such as disk drives for the purpose of reducing the bandwidth needed on the system interface.
• a system interface allows interconnection of multiple adaptive processors without the need for a host microprocessor for each adaptive processor and an embedded microprocessor in the control chip can be used to decode commands arriving via the system interface.
• an adaptive processor as previously described comprises SRAM used as common memory and shared by all FPGAs in the user array and can use separate peripheral I/O and system interconnect ports for the purpose of improving system scalability and I/O bandwidth.
• DRAM may further be used to provide for large on board storage that is also accessible by all other processors in the system.
• Fig. 1 A is a functional block diagram of a particular, representative embodiment of a multi-adaptive processor element incorporating a field programmable gate array (“FPGAs”) control element having embedded processor cores in conjunction with a pair of user FPGAs and six banks of dual-ported static random access memory (“SRAM");
• FPGAs field programmable gate array
• SRAM static random access memory
• Fig. 1 B is a simplified flowchart illustrative of the general sequence of "read” and “write” operations as between the dynamic random access memory (“DRAM”) and SRAM portions of the representative embodiment of the preceding figure
• Fig. 2 is a system level block diagram of an exemplary implementation of a computer system utilizing one or more of the multi-adaptive processor elements of Fig. 1A in conjunction with one or more microprocessors and memory subsystem banks as functionally coupled by means of a memory interconnect fabric
• Fig. 3 is a further system level block diagram of another exemplary implementation of a computer system utilizing one or more of the multi- adaptive processor elements of Fig. 1 A in conjunction with one or more microprocessors functionally coupled to a shared memory resource by means of a switch network;
• Fig. 4 is an additional system level block diagram of yet another exemplary implementation of a computer system utilizing one or more of the multi-adaptive processor elements of Fig. 1 A in conjunction with one or more microprocessors and having shared peripheral storage though a storage area network ("SAN"); and
• SAN storage area network
• Fig. 5 is a partial cross-sectional view of a particular printed circuit board implementation of a technique for the mounting and interconnection of a pair of user FPGAs of possible use in the representative multi-adaptive processor element of Fig. 1A.
• the multi-adaptive processor element 100 comprises, in pertinent part, a discrete control FPGA 102 operating in conjunction with a pair of separate user FPGAs 104 0 and 104*-.
• the control FPGA 102 and user FPGAs 104 0 and 104 ⁇ are coupled through a number of SRAM banks 106, here illustrated in this particular implementation, as dual-ported SRAM banks
• An additional memory block comprising DRAM 108 is also associated with the control FPGA 102.
• the control FPGA 102 includes a number of embedded microprocessor cores including ⁇ P1 112 which is coupled to a peripheral interface bus 114 by means of an electro optic converter 116 to provide the capability for additional physical length for the bus 114 to drive any connected peripheral devices (not shown).
• a second microprocessor core ⁇ PO 118 is utilized to manage the multi-adaptive processor element 100 system interface bus 120, which although illustrated for sake of simplicity as a single bi- directional bus, may actually comprise a pair of parallel unidirectional busses.
• a chain port 122 may also be provided to enable additional multi-adaptive processor elements 100 to communicate directly with the multi- adaptive processor element 100 shown.
• the overall multi-adaptive processor element 100 architecture has as its primary components three FPGAs 102 and 104 0 , 104 ! , the DRAM 108 and dual-ported SRAM banks 106.
• the heart of the design is the user FPGAs 104 0 , 104- ⁇ which are loaded with the logic required to perform the desired processing.
• Discrete FPGAs 104 0 , 104 ⁇ are used to allow the maximum amount of reconfigurable circuitry.
• the performance of this multi-adaptive processor element 100 may be further enhanced by using a maximum of two such FPGAs 104 to form a user array. By using two chips, they can be placed on opposite sides of the circuit board from each other as will be more fully described hereinafter.
• the dual-ported SRAM banks 106 are used to provide very fast bulk memory to support the user array 104. To maximize its volume, discrete SRAM chips may be arranged in multiple, independently connected banks 106 0 through 106 5 as shown. This provides much more capacity than could be achieved if the SRAM were only integrated directly into the FPGAs 102 and/or 104. Again, the high input output ("I/O") counts achieved by the particular packaging employed and disclosed herein currently allows commodity FPGAs to be interconnected to six, 64 bit wide SRAM banks 106o through IO6 5 achieving a total memory bandwidth of 4.8 Gbytes/sec.
• I/O input output
• dual-ported SRAM may be used with each SRAM chip having two separate ports for address and data.
• One port from each chip is connected to the two user array FPGAs 104 0 and 104 ⁇ while the other is connected to a third FPGA that functions as a control FPGA 102.
• This control FPGA 102 also connects to a much larger high speed DRAM 108 memory dual in-line memory module ("DIMM").
• DIMM DRAM 108 memory dual in-line memory module
• This DRAM 108 DIMM can easily have 100 times the density of the SRAM banks 106 with similar bandwidth when used in certain burst modes. This allows the multi-adaptive processor element 100 to use the SRAM 106 as a circular buffer that is fed by the control FPGA 102 with data from the DRAM 108 as will be more fully described hereinafter.
• control FPGA 102 also performs several other functions.
• control FPGA 102 may be selected from the Virtex 5 Pro family available from Xilinx, Inc. San Jose, CA, which have embedded Power PC microprocessor cores.
• ⁇ PO 118 is used to decode control commands that are received via the system interface bus 120.
• This interface is a multi-gigabyte per second interface that allows multiple multi-adaptive processor elements 100 to be interconnected together. It also 0 allows for standard microprocessor boards to be interconnected to multi- adaptive processor elements 100 via the use of SRC SNAPTM cards.
• SNAP is a trademark of SRC Computers, Inc., assignee of the present invention; a representative implementation of such SNAP cards is disclosed in United States Patent Application Serial No. 09/932,330 filed August 17, 2001 for: 5 "Switch/Network Adapter Port for Clustered Computers Employing a Chain of Multi-Adaptive Processors in a Dual In-Line Memory Module Format" assigned to SRC Computers, Inc., the disclosure of which is herein specifically incorporated in its entirety by this reference.) Packets received over this interface perform a variety of functions including local and peripheral o direct memory access (“DMA") commands and user array 104 configuration instructions. These commands may be processed by one of the embedded microprocessor cores within the control FPGA 102 and/or by logic otherwise implemented in the FPGA 102.
• DMA direct memory access
• 5 several high speed serial peripheral I/O ports may also be implemented.
• Each of these can be controlled by either another microprocessor core (e.g. ⁇ P1 112) or by discrete logic implemented in the control FPGA 102. These will allow the multi-adaptive processor element 100 to connect directly to hard disks, a storage area network of disks or other computer mass storage o peripherals. In this fashion, only a small amount of the system interface bus
• any multi-adaptive processor element 100 can also be accessed by another multi-adaptive processor element 100 via the system interface bus 120 to allow for sharing of data such as in a database search that is partitioned across several multi- 5 adaptive processor elements 100.
• a simplified flowchart is shown illustrative of the general sequence of "read” and “write” operations as between the DRAM 108 and SRAM bank 106 portions of the representative embodiment of the preceding figure.
• reads are performed by the 0 DMA logic in the control FPGA 102 using sequential addresses to achieve the highest bandwidth possible from the DRAM 108.
• the DMA logic then performs "writes" to random address locations in any number of the SRAM banks 106.
• step 154 the use of dual-ported SRAM allows the 5 control FPGA 102 to continuously "write” into the SRAM banks 106 while the user FPGAs 104 continuously “reads” from them as well.
• step 156 the logic in the user FPGAs 104 simultaneously performs high speed "reads” from the random addresses in the multiple SRAM banks 106.
• step 158 the previously described process is reversed during "writes" from the o user FPGAs 104 comprising the user array.
• the high volume DRAM 108 is "read” using its fast sequential burst modes and the lower capacity SRAM banks 106 are then randomly loaded allowing the user FPGAs 104 to experience very high random access data rates from what appears to be a very large virtual SRAM.
• the reverse 5 also happens when the user FPGAs are "writing" data to the SRAM banks
• control FPGA 102 may be implemented in the control FPGA 102.
• FIG. 2 a system level block diagram of an exemplary implementation of a computer system 200 is shown.
• This o particular embodiment of a computer system 200 may utilize one or more of the multi-adaptive processor elements 100 0 through 100N of Fig. 1A in conjunction with one or more microprocessors 202o through 202M and memory subsystem banks 206 0 through 206 M as functionally coupled by means of a memory interconnect fabric 204.
• FIG. 3 a further system level block diagram of another exemplary implementation of a computer system 300 is shown.
• This particular embodiment of a computer system 300 may also utilize one or more of the multi-adaptive processor elements 100o through 100N of Fig. 1A in conjunction with one or more microprocessors 302 0 through 302M functionally coupled to a switch network 304 by means of a system interface bus 320 and, in turn, to a shared memory resource 306.
• each of the multi- adaptive processor elements 100o through 100N may directly access attached storage resources 308 as may one or more of the microprocessors 302o through 302M through a peripheral bus 312.
• a number of chain ports 322 may provide direct coupling between individual multi-adaptive processor elements 100 0 through 100 N .
• FIG. 4 an additional system level block diagram of yet another exemplary implementation of a computer system 400 is shown.
• This particular implementation of a computer system 400 may additionally utilize one or more of the multi-adaptive processor elements 10Oo through 10 ⁇ N ⁇ f Fig. 1A in conjunction with one or more microprocessors 402 0 through 402M coupled to the multi-adaptive processing elements 100 through respective system interface buses 420 and SNAP cards 416 as previously described.
• the multi-adaptive processor elements 100o through 100N may be directly coupled to each other by means of chain ports 422 as shown.
• the microprocessors 402o through 402M are coupled by means of a network 404 and the multi-adaptive processor elements 100 0 through 100N and microprocessors 402 0 through 402M may each have a directly coupled storage element 408 coupled to a peripheral interface 414 or 412 respectively.
• the multi-adaptive processor elements 100 0 through 100N and microprocessors 402 0 through 402M may each be coupled to a storage area network ("SAN") to access shared storage 410.
• SAN storage area network
• Fig. 5 a partial cross-sectional view of a particular printed circuit board 500 is shown. In accordance with the mounting configuration shown, the two user FPGAs 104o and 104 ! (Fig.
• a number of electrical interconnects 508 provide electrical connections to the vias 504 and contact pads 506 and, in turn, to o both of the user FPGAs 104 0 and 104 ! .
• Discrete FPGAs 104 are used for the user array to allow the maximum amount of reconfigurable circuitry.
• the performance of this multi-adaptive element 100 (Fig. 1A) is further enhanced by using a preferred two of such FPGAs 104 to form the user array.
• a preferred two of such FPGAs 104 By using two chips, they can be placed on 5 opposite sides of the printed circuit board 502 opposing each other with the contacts of their BGA packages sharing a common via 504 through the board. Since the I/O pins of these devices are programmable, the two user FPGAs 104o and 104 ⁇ can be set up as mirror-image functional pin configurations. This eliminates most of the chip-to-chip routing that would otherwise be o required for their interconnection to the degree necessary to allow them to function as effectively one larger device.
• circuit board 502 layer count and cost is also minimized.
• This mounting technique also permits the effective use of the largest pin count packages available which will maximize the I/O capability of the user array. Interconnecting the user 5 FPGAs 104 of the user array in this fashion makes the electrical loading of these two chips appear as a single electrical termination on the transmission lines that are formed by the traces that connect to the chips. At high data rates, such as that required by a high performance processor, this greatly simplifies termination of these lines leading to improved signal quality and 0 maximum data rates.

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• 2002
  • 2002-05-09 US US10/142,045 patent/US20030212853A1/en not_active Abandoned
  • 2002-12-03 AU AU2002360486A patent/AU2002360486A1/en not_active Abandoned
  • 2002-12-03 JP JP2004504121A patent/JP2005524906A/ja not_active Withdrawn
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  • 2002-12-03 WO PCT/US2002/038844 patent/WO2003096195A1/en not_active Ceased
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• 2005
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