JP2005514698A5 - - Google Patents

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Publication number
JP2005514698A5
JP2005514698A5 JP2003558678A JP2003558678A JP2005514698A5 JP 2005514698 A5 JP2005514698 A5 JP 2005514698A5 JP 2003558678 A JP2003558678 A JP 2003558678A JP 2003558678 A JP2003558678 A JP 2003558678A JP 2005514698 A5 JP2005514698 A5 JP 2005514698A5
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JP
Japan
Prior art keywords
thread
processor
selected time
resources
opcode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003558678A
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English (en)
Japanese (ja)
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JP2005514698A (ja
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Publication date
Priority claimed from US10/039,777 external-priority patent/US20030126416A1/en
Application filed filed Critical
Publication of JP2005514698A publication Critical patent/JP2005514698A/ja
Publication of JP2005514698A5 publication Critical patent/JP2005514698A5/ja
Pending legal-status Critical Current

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JP2003558678A 2001-12-31 2002-12-11 マルチスレッドプロセッサのスレッドの実行のサスペンド処理 Pending JP2005514698A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/039,777 US20030126416A1 (en) 2001-12-31 2001-12-31 Suspending execution of a thread in a multi-threaded processor
PCT/US2002/039790 WO2003058434A1 (en) 2001-12-31 2002-12-11 Suspending execution of a thread in a multi-threaded

Publications (2)

Publication Number Publication Date
JP2005514698A JP2005514698A (ja) 2005-05-19
JP2005514698A5 true JP2005514698A5 (https=) 2005-12-22

Family

ID=21907295

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003558678A Pending JP2005514698A (ja) 2001-12-31 2002-12-11 マルチスレッドプロセッサのスレッドの実行のサスペンド処理

Country Status (8)

Country Link
US (1) US20030126416A1 (https=)
JP (1) JP2005514698A (https=)
KR (1) KR100617417B1 (https=)
CN (1) CN1287272C (https=)
AU (1) AU2002364559A1 (https=)
DE (1) DE10297597T5 (https=)
TW (1) TW200403588A (https=)
WO (1) WO2003058434A1 (https=)

Families Citing this family (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7127561B2 (en) * 2001-12-31 2006-10-24 Intel Corporation Coherency techniques for suspending execution of a thread until a specified memory access occurs
US7363474B2 (en) * 2001-12-31 2008-04-22 Intel Corporation Method and apparatus for suspending execution of a thread until a specified memory access occurs
US7216346B2 (en) * 2002-12-31 2007-05-08 International Business Machines Corporation Method and apparatus for managing thread execution in a multithread application
US7496915B2 (en) 2003-04-24 2009-02-24 International Business Machines Corporation Dynamic switching of multithreaded processor between single threaded and simultaneous multithreaded modes
US7213093B2 (en) * 2003-06-27 2007-05-01 Intel Corporation Queued locks using monitor-memory wait
US9032404B2 (en) 2003-08-28 2015-05-12 Mips Technologies, Inc. Preemptive multitasking employing software emulation of directed exceptions in a multithreading processor
US7836450B2 (en) 2003-08-28 2010-11-16 Mips Technologies, Inc. Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts
US7711931B2 (en) * 2003-08-28 2010-05-04 Mips Technologies, Inc. Synchronized storage providing multiple synchronization semantics
US7418585B2 (en) * 2003-08-28 2008-08-26 Mips Technologies, Inc. Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts
US7870553B2 (en) * 2003-08-28 2011-01-11 Mips Technologies, Inc. Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts
JP4740851B2 (ja) * 2003-08-28 2011-08-03 ミップス テクノロジーズ インコーポレイテッド 仮想プロセッサリソースの動的構成のための機構体
US7376954B2 (en) 2003-08-28 2008-05-20 Mips Technologies, Inc. Mechanisms for assuring quality of service for programs executing on a multithreaded processor
US7849297B2 (en) 2003-08-28 2010-12-07 Mips Technologies, Inc. Software emulation of directed exceptions in a multithreading processor
US7594089B2 (en) 2003-08-28 2009-09-22 Mips Technologies, Inc. Smart memory based synchronization controller for a multi-threaded multiprocessor SoC
US8984517B2 (en) * 2004-02-04 2015-03-17 Intel Corporation Sharing idled processor execution resources
GB0407384D0 (en) * 2004-03-31 2004-05-05 Ignios Ltd Resource management in a multicore processor
US9189230B2 (en) 2004-03-31 2015-11-17 Intel Corporation Method and system to provide concurrent user-level, non-privileged shared resource thread creation and execution
US8533716B2 (en) 2004-03-31 2013-09-10 Synopsys, Inc. Resource management in a multicore architecture
WO2006120367A1 (en) * 2005-05-11 2006-11-16 Arm Limited A data processing apparatus and method employing multiple register sets
US8327115B2 (en) 2006-04-12 2012-12-04 Soft Machines, Inc. Plural matrices of execution units for processing matrices of row dependent instructions in single clock cycle in super or separate mode
US8032737B2 (en) * 2006-08-14 2011-10-04 Marvell World Trade Ltd. Methods and apparatus for handling switching among threads within a multithread processor
WO2008078329A2 (en) 2006-12-27 2008-07-03 More It Resources Ltd. Method and system for transaction resource control
US7975272B2 (en) * 2006-12-30 2011-07-05 Intel Corporation Thread queuing method and apparatus
US20080162858A1 (en) * 2007-01-03 2008-07-03 Freescale Semiconductor, Inc. Hardware-based memory initialization with software support
US8725975B2 (en) * 2007-01-03 2014-05-13 Freescale Semiconductor, Inc. Progressive memory initialization with waitpoints
US20080244242A1 (en) * 2007-04-02 2008-10-02 Abernathy Christopher M Using a Register File as Either a Rename Buffer or an Architected Register File
US7707390B2 (en) * 2007-04-25 2010-04-27 Arm Limited Instruction issue control within a multi-threaded in-order superscalar processor
WO2008155794A1 (ja) 2007-06-19 2008-12-24 Fujitsu Limited 情報処理装置
CN101681260B (zh) * 2007-06-20 2013-04-17 富士通株式会社 运算装置
US20090100249A1 (en) * 2007-10-10 2009-04-16 Eichenberger Alexandre E Method and apparatus for allocating architectural register resources among threads in a multi-threaded microprocessor core
US8131983B2 (en) * 2008-04-28 2012-03-06 International Business Machines Corporation Method, apparatus and article of manufacture for timeout waits on locks
US20120166777A1 (en) * 2010-12-22 2012-06-28 Advanced Micro Devices, Inc. Method and apparatus for switching threads
KR101966712B1 (ko) 2011-03-25 2019-04-09 인텔 코포레이션 분할가능한 엔진에 의해 인스턴스화된 가상 코어를 이용한 코드 블록의 실행을 지원하는 메모리 프래그먼트
US8578394B2 (en) * 2011-09-09 2013-11-05 Microsoft Corporation Exempting applications from suspension
CN103389911B (zh) * 2012-05-07 2016-08-03 启碁科技股份有限公司 节省系统资源的方法及运用其方法的操作系统
US9361116B2 (en) 2012-12-28 2016-06-07 Intel Corporation Apparatus and method for low-latency invocation of accelerators
US9417873B2 (en) 2012-12-28 2016-08-16 Intel Corporation Apparatus and method for a hybrid latency-throughput processor
US10140129B2 (en) 2012-12-28 2018-11-27 Intel Corporation Processing core having shared front end unit
US10346195B2 (en) * 2012-12-29 2019-07-09 Intel Corporation Apparatus and method for invocation of a multi threaded accelerator
EP2972836B1 (en) 2013-03-15 2022-11-09 Intel Corporation A method for emulating a guest centralized flag architecture by using a native distributed flag architecture
US10140138B2 (en) 2013-03-15 2018-11-27 Intel Corporation Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
CN103345422B (zh) * 2013-07-02 2019-01-29 厦门雅迅网络股份有限公司 一种基于Linux的多线程硬实时控制方法
US10140212B2 (en) 2013-09-30 2018-11-27 Vmware, Inc. Consistent and efficient mirroring of nonvolatile memory state in virtualized environments by remote mirroring memory addresses of nonvolatile memory to which cached lines of the nonvolatile memory have been flushed
US10223026B2 (en) * 2013-09-30 2019-03-05 Vmware, Inc. Consistent and efficient mirroring of nonvolatile memory state in virtualized environments where dirty bit of page table entries in non-volatile memory are not cleared until pages in non-volatile memory are remotely mirrored
US9515901B2 (en) 2013-10-18 2016-12-06 AppDynamics, Inc. Automatic asynchronous handoff identification
US20160170767A1 (en) * 2014-12-12 2016-06-16 Intel Corporation Temporary transfer of a multithreaded ip core to single or reduced thread configuration during thread offload to co-processor
CN105843592A (zh) * 2015-01-12 2016-08-10 芋头科技（杭州）有限公司 一种在预设嵌入式系统中实现脚本操作的系统
CN107430527B (zh) * 2015-05-14 2021-01-29 株式会社日立制作所 具有服务器存储系统的计算机系统
US11023233B2 (en) 2016-02-09 2021-06-01 Intel Corporation Methods, apparatus, and instructions for user level thread suspension
US10353817B2 (en) * 2017-03-07 2019-07-16 International Business Machines Corporation Cache miss thread balancing
WO2018165952A1 (zh) * 2017-03-16 2018-09-20 深圳大趋智能科技有限公司 iOS线程恢复的方法及装置
TWI647619B (zh) * 2017-08-29 2019-01-11 智微科技股份有限公司 用來於一電子裝置中進行硬體資源管理之方法以及對應的電子裝置
CN109471673B (zh) * 2017-09-07 2022-02-01 智微科技股份有限公司 用来于电子装置中进行硬件资源管理的方法及电子装置
US10481915B2 (en) * 2017-09-20 2019-11-19 International Business Machines Corporation Split store data queue design for an out-of-order processor
GB2569098B (en) * 2017-10-20 2020-01-08 Graphcore Ltd Combining states of multiple threads in a multi-threaded processor
GB201717303D0 (en) * 2017-10-20 2017-12-06 Graphcore Ltd Scheduling tasks in a multi-threaded processor

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5357617A (en) * 1991-11-22 1994-10-18 International Business Machines Corporation Method and apparatus for substantially concurrent multiple instruction thread processing by a single pipeline processor
JP3678759B2 (ja) * 1992-07-21 2005-08-03 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 割込を発生するための装置および割込を発生するための方法
US5584031A (en) * 1993-11-09 1996-12-10 Motorola Inc. System and method for executing a low power delay instruction
JPH08320797A (ja) * 1995-05-24 1996-12-03 Fuji Xerox Co Ltd プログラム制御システム
US5933627A (en) * 1996-07-01 1999-08-03 Sun Microsystems Thread switch on blocked load or store using instruction thread field
DE69717369T2 (de) * 1996-08-27 2003-09-11 Matsushita Electric Ind Co Ltd Vielfadenprozessor zur Verarbeitung von mehreren Befehlsströmen unabhängig von einander durch eine flexible Durchsatzsteuerung in jedem Befehlsstrom
US5961639A (en) * 1996-12-16 1999-10-05 International Business Machines Corporation Processor and method for dynamically inserting auxiliary instructions within an instruction stream during execution
US6463527B1 (en) * 1997-03-21 2002-10-08 Uzi Y. Vishkin Spawn-join instruction set architecture for providing explicit multithreading
US6401155B1 (en) * 1998-12-22 2002-06-04 Philips Electronics North America Corporation Interrupt/software-controlled thread processing
SG65097A1 (en) * 1998-12-28 2001-08-21 Compaq Computer Corp Break event generation during transitions between modes of operation in a computer system
US6535905B1 (en) * 1999-04-29 2003-03-18 Intel Corporation Method and apparatus for thread switching within a multithreaded processor
US6341347B1 (en) * 1999-05-11 2002-01-22 Sun Microsystems, Inc. Thread switch logic in a multiple-thread processor
US6493741B1 (en) * 1999-10-01 2002-12-10 Compaq Information Technologies Group, L.P. Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit
US6357016B1 (en) * 1999-12-09 2002-03-12 Intel Corporation Method and apparatus for disabling a clock signal within a multithreaded processor
US6496925B1 (en) * 1999-12-09 2002-12-17 Intel Corporation Method and apparatus for processing an event occurrence within a multithreaded processor
US6931639B1 (en) * 2000-08-24 2005-08-16 International Business Machines Corporation Method for implementing a variable-partitioned queue for simultaneous multithreaded processors
US7168076B2 (en) * 2001-07-13 2007-01-23 Sun Microsystems, Inc. Facilitating efficient join operations between a head thread and a speculative thread

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