Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/30003—Arrangements for executing specific machine instructions
  • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
  • G06F9/3009—Thread control instructions
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/30098—Register arrangements
  • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
  • G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
  • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating

Definitions

• the present disclosure pertains to the field of processors. More particularly, the
• present disclosure pertains to multi-threaded processors and techniques for temporarily suspending the processing of one thread in a multi-threaded processor.
• a multi-threaded processor is capable of processing multiple different instruction
• a primary motivating factor driving execution of multiple instruction streams within a single processor is the resulting improvement in processor utilization.
• Highly parallel architectures have developed over the years, but it is often difficult to extract sufficient parallelism from a single stream of instructions to utilize the multiple execution units.
• Simultaneous multi-threading processors allow multiple 25 instruction streams to execute concurrently in the different execution resources in an attempt to better utilize those resources. Multi-threading can be particularly advantageous for programs that encounter high latency delays or which often wait for events to occur. When one thread is waiting for a high latency task to complete or for a particular event, a different thread may be processed.
• Figure 1 illustrates one embodiment of a multi-threaded processor having logic to suspend a thread in response to an instruction and to relinquish resources associated with that thread.
• Figure 2 is a flow diagram illustrating operation of the multi-threaded processor of
• Figure 1 illustrates various options for specifying an amount of time a multithreading processor may be suspended.
• Figure 3b illustrates a flow diagram in which the suspended state may be exited by either the elapse of a selected amount of time or the occurrence of an event.
• Figure 4 illustrates resource patititioning, sharing, and duplication according to one embodiment.
• Figure 5 illustrates various design representations or formats for simulation, emulation, and fabrication of a design using the disclosed techniques.
• the disclosed techniques may allow a programmer to implement a suspend mechanism in one thread while letting other threads harness processing resources. Thus, partitions previously dedicated to the suspended thread may be relinquished while the
• Figure 1 illustrates one embodiment of a multi-threaded processor 100 having suspend logic 110 to allow a thread to be suspended in response to an instruction.
• a "processor” may be formed as a single integrated circuit in some embodiments. In other 15 embodiments, multiple integrated circuits may together form a processor, and in yet other embodiments, hardware and software routines (e.g., binary translation routines) may together form the processor.
• the suspend logic may be microcode, various forms of control logic, or other implementation of the described functionality, possibly including translation, software, etc.
• the processor 100 is coupled to a memory 195 to allow the processor to retrieve instructions from the memory 195 and to execute these instructions.
• the memory and the processor may be coupled in a point-to-point fashion, via bus bridges, via a memory controller or via other known or otherwise available techniques.
• the memory 195 stores various program threads, including a first thread 196 and a second thread 198.
• the first 25 thread 196 includes a SUSPEND instruction.
• a bus/memory controller 120 provides instructions for execution to a front end 130.
• the front end 130 directs the retrieval of instructions from various threads according to instruction pointers 170. Instruction pointer logic is replicated to support multiple threads.
• the front end 130 feeds instructions into thread 5 partitionable resources 140 for further processing.
• the thread partitionable resources 140 include logically separated partitions dedicated to particular threads when multiple threads are active within the processor 100. In one embodiment, each separate partition only contains instructions from the thread to which that portion is dedicated.
• the thread partitionable resources 140 may include, for example, instruction queues. When in a 10 single thread mode, the partitions of the thread partitionable resources 140 may be combined to form a single large partition dedicated to the one thread.
• the processor 100 also includes replicated state 180.
• the replicated state 180 includes state variables sufficient to maintain context for a logical processor. With replicated state 180, multiple threads can execute without competition for state variable 15 storage. Additionally, register allocation logic may be replicated for each thread. The replicated state-related logic operates with the appropriate resource partitions to prepare incoming instructions for execution.
• the thread partitionable resources 140 pass instructions along to shared resources
• the shared resources 150 operate on instructions without regard to their origin.
• scheduler and execution units may be thread-unaware shared resources.
• the partitionable resources 140 may feed instructions from multiple threads to the shared resources 150 by alternating between the threads in a fair manner that provides continued progress on each active thread.
• the shared resources may execute the provided instructions on the appropriate state without concern for the thread mix.
• the shared resources 150 may be followed by another set of thread partitionable resources 160.
• the thread partitionable resources 160 may include retirement resources such as a re-order buffer and the like. Accordingly, the thread partitionable resources 160 may ensure that execution of instructions from each thread concludes properly and that the appropriate state for that thread is appropriately updated.
• the processor 100 of Figure 1 includes the suspend logic 110.
• the suspend logic 110 may be programmable to provide a particular duration for which the thread is to be suspended or to provide a fixed delay.
• the suspend 10 logic 110 includes pipeline flush logic 112 and partition/anneal logic 114.
• the instruction set of the processor 100 includes a SUSPEND opcode (instruction) to cause thread suspension.
• the SUSPEND opcode is received as a part of the sequence of instructions of a 15 first thread (Tl).
• Thread Tl execution is suspended as indicated in block 210.
• the thread suspend logic 110 includes pipeline flush logic 112, which drains the processor pipeline in order to clear all instructions as indicated in block 220.
• partition/anneal logic 114 causes any partitioned resources associated exclusively with thread Tl to be relinquished for use by other threads as 20 indicated in block 230. These relinquished resources are annealed to form a set of larger resources for the remaining active threads to utilize.
• processor resources may continue to be utilized, substantially without interference from
• the processor may relinquish some or all of the partitions of partitionable resources 140 and 160 that were dedicated to Tl.
• different permutations of the SUSPEND opcode or settings associated therewith may indicate which resources to relinquish, if any. For example, when a programmer
• the thread may be suspended, but maintain most resource partitions. Throughput is still enhanced because the shared resources may be used exclusively by other threads during the thread suspension period. When a longer wait is anticipated, relinquishing all partitions associated with the suspended thread allows other threads to have additional resources, potentially increasing the throughput of the other
• a test is performed to determine if the suspend state should be exited.
• the thread may
• a processor 300 may include a delay time (Dl) specified by a routine of microcode 310.
• a timer or counter 312 may implement the delay and signal the microcode when the specified amount of time has elapsed.
• one or more fuses 330 may be used to specify a delay (D2), or a register 340
• a delay (D3) may store a delay (D3).
• a delay (D4) may be specified by a register or storage location such as a configuration register in a bridge or memory controller 302 which is coupled to the processor.
• a delay (D5) may also be specified by the basic input/output system (BIOS) 322.
• the delay (D6) could be stored in a memory 304 which is coupled to the memory controller 302.
• the processor 300 may retrieve the delay value as 5 an implicit or explicit operand to the SUSPEND opcode as it is executed by an execution unit 320. Other known or otherwise available or convenient techniques of specifying a value may be used to specify the delay as well. [0026] Referring back to Figure 2, if the delay time has not elapsed, then the timer, counter, or other delay-measuring mechanism used continues to track the delay, and the
• thread Tl 10 thread remains suspended, as indicated by the return to block 240. If the delay time has elapsed, then thread Tl resumption begins in block 250. As indicated in block 250, the pipeline is flushed, to free resources for thread Tl. In block 260, resources are re- partitioned such that thread Tl has portions of the thread-partitionable resources with which to perform operations. Finally, thread Tl re-starts execution, as indicated in block
• Figures 1 and 2 provide techniques to allow a thread to be suspended by a program for a particular duration.
• other events also cause Tl to be resumed.
• an interrupt may cause Tl to resume.
• 3b illustrates a flow diagram for one embodiment that allows other events to cause the
• 25 state-breaking events are detected in blocks 370 and 375.
• block 370 tests whether any (and in some embodiments which) events are enabled to break the suspend state. If no events are enabled to break the suspend state, then the process returns to block
• thread Tl is resumed, as indicated in block 380. Otherwise, the processor remains with thread Tl in the suspended state, and the process returns to block 365.
• Figure 4 illustrates the partitioning, duplication, and sharing of resources according to one embodiment. Partitioned resources may be partitioned and annealed (fused back
• duplicated resources include instruction pointer logic in the instruction fetch portion of the pipeline, register renaming logic in the rename portion of the pipeline, state variables (not shown, but referenced in various stages in the pipeline), and an interrupt controller (not shown, generally asynchronous to pipeline).
• Shared resources in the embodiment of Figure 4 include schedulers in the schedule stage of the pipeline, a pool of registers in the register read and write portions of the pipeline, execution resources in the execute portion of the pipeline. Additionally, a trace cache and an LI data cache may be shared resources populated according to memory accesses without regard to thread context. In other embodiments, consideration of thread context
• Partitioned resources in the embodiment of Figure 4 include two queues in queuing stages of the pipeline, a re-order buffer in a retirement stage of the pipeline, and a store buffer. Thread selection multiplexing logic alternates between the various duplicated and partitioned resources to provide reasonable access to both threads.
• the partitionable resources may not be strictly partitioned, but rather may allow some instructions to cross partitions or may allow partitions to vary in size depending on the thread being executed in that partition or the total number of threads being executed. Additionally, different mixes of resources may be designated as shared, duplicated, and partitioned resources.
• Figure 5 illustrates various design representations or formats for simulation, emulation, and fabrication of a design using the disclosed techniques.
• Data representing a design may represent the design in a number of manners.
• the hardware may be represented using a hardware description language or another functional description language which essentially provides a computerized model of how the designed hardware is expected to perform.
• the hardware model 1110 may be stored in a storage medium 1100 such as a computer memory so that the model may be simulated using simulation software 1120 that applies a particular test suite 1130 to the hardware model 1110 to determine if it indeed functions as intended.
• the simulation software is not recorded, captured, or contained in the medium.
• a circuit level model with logic and/or transistor gates may be produced at some stages of the design process.
• This model may be similarly simulated, sometimes by dedicated hardware simulators that form the model using programmable logic. This type of simulation, taken a degree further, may be an emulation technique.
• re-configurable hardware is another embodiment that may involve a machine readable medium storing a model employing the disclosed techniques.
• the data representing the hardware model may be the data specifying the presence or absence of various features on different mask layers for masks used to produce the integrated circuit.
• this data representing the integrated circuit embodies the techniques disclosed in that the circuitry or logic in the data can be simulated or fabricated to perform these techniques.
• the data may be stored in any form of a computer readable medium.
• An optical or electrical wave 1160 modulated or otherwise generated to transmit such information, a memory 1150, or a magnetic or optical storage 1140 such as a disc may be the medium.
• the set of bits describing the design or the particular part of the design are an article that may be sold in and of itself or used by others for further design or fabrication. Thus, techniques for suspending execution of a thread in a multi-threaded processor are disclosed.

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• Physics & Mathematics (AREA)
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• General Physics & Mathematics (AREA)
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• Executing Machine-Instructions (AREA)

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• 2001
  • 2001-12-31 US US10/039,777 patent/US20030126416A1/en not_active Abandoned
• 2002
  • 2002-12-11 KR KR1020047010393A patent/KR100617417B1/ko not_active Expired - Fee Related
  • 2002-12-11 WO PCT/US2002/039790 patent/WO2003058434A1/en not_active Ceased
  • 2002-12-11 CN CNB028261585A patent/CN1287272C/zh not_active Expired - Fee Related
  • 2002-12-11 DE DE10297597T patent/DE10297597T5/de not_active Ceased
  • 2002-12-11 AU AU2002364559A patent/AU2002364559A1/en not_active Abandoned
  • 2002-12-11 JP JP2003558678A patent/JP2005514698A/ja active Pending
  • 2002-12-25 TW TW091137297A patent/TW200403588A/zh unknown

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