JP2005507128A - 物理的および非物理的なシステムのポジノミナルモデル化、サイジング、最適化および制御 - Google Patents

物理的および非物理的なシステムのポジノミナルモデル化、サイジング、最適化および制御 Download PDF

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JP2005507128A
JP2005507128A JP2003540877A JP2003540877A JP2005507128A JP 2005507128 A JP2005507128 A JP 2005507128A JP 2003540877 A JP2003540877 A JP 2003540877A JP 2003540877 A JP2003540877 A JP 2003540877A JP 2005507128 A JP2005507128 A JP 2005507128A
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positive
model
numerical data
computer
fitting
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JP2005507128A5 (enExample
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デームス，ワルター
ギーレン，ゲオルゲス
サンセン，ウィリー
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キモーション・テクノロジーズ・インコーポレイテッド
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B17/00—Systems involving the use of models or simulators of said systems
    • G05B17/02—Systems involving the use of models or simulators of said systems electric
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
JP2003540877A 2001-10-31 2002-10-31 物理的および非物理的なシステムのポジノミナルモデル化、サイジング、最適化および制御 Pending JP2005507128A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB0126104.9A GB0126104D0 (en) 2001-10-31 2001-10-31 Electronic circuit modeling sizing and optimisation
PCT/BE2002/000164 WO2003038686A2 (en) 2001-10-31 2002-10-31 Posynomial modeling, sizing, optimization and control of physical and non-physical systems

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JP2005507128A true JP2005507128A (ja) 2005-03-10
JP2005507128A5 JP2005507128A5 (enExample) 2006-01-05

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JP2003540877A Pending JP2005507128A (ja) 2001-10-31 2002-10-31 物理的および非物理的なシステムのポジノミナルモデル化、サイジング、最適化および制御

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Country Link
US (1) US7162402B2 (enExample)
EP (1) EP1440396A2 (enExample)
JP (1) JP2005507128A (enExample)
CA (1) CA2464935A1 (enExample)
GB (1) GB0126104D0 (enExample)
IL (1) IL161675A0 (enExample)
WO (1) WO2003038686A2 (enExample)

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US20030191611A1 (en) * 2002-04-05 2003-10-09 Hershenson Maria Del Mar Behavioral circuit modeling for geometric programming
US20040054515A1 (en) * 2002-09-18 2004-03-18 Todi Rajat Kumar Methods and systems for modeling the performance of a processor
US20090077508A1 (en) * 2004-01-28 2009-03-19 Rubin Daniel I Accelerated life testing of semiconductor chips
US7458052B1 (en) 2004-08-30 2008-11-25 Gradient Design Automation, Inc. Method and apparatus for normalizing thermal gradients over semiconductor chip designs
US7353471B1 (en) * 2004-08-05 2008-04-01 Gradient Design Automation Inc. Method and apparatus for using full-chip thermal analysis of semiconductor chip designs to compute thermal conductance
US7194711B2 (en) * 2004-01-28 2007-03-20 Gradient Design Automation Inc. Method and apparatus for full-chip thermal analysis of semiconductor chip designs
US20090048801A1 (en) * 2004-01-28 2009-02-19 Rajit Chandra Method and apparatus for generating thermal test vectors
US7203920B2 (en) * 2004-01-28 2007-04-10 Gradient Design Automation Inc. Method and apparatus for retrofitting semiconductor chip performance analysis tools with full-chip thermal analysis capabilities
US7401304B2 (en) * 2004-01-28 2008-07-15 Gradient Design Automation Inc. Method and apparatus for thermal modeling and analysis of semiconductor chip designs
US7383520B2 (en) * 2004-08-05 2008-06-03 Gradient Design Automation Inc. Method and apparatus for optimizing thermal management system performance using full-chip thermal analysis of semiconductor chip designs
US20090224356A1 (en) * 2004-01-28 2009-09-10 Rajit Chandra Method and apparatus for thermally aware design improvement
WO2007070879A1 (en) * 2005-12-17 2007-06-21 Gradient Design Automation, Inc. Simulation of ic temperature distributions using an adaptive 3d grid
US7472363B1 (en) * 2004-01-28 2008-12-30 Gradient Design Automation Inc. Semiconductor chip design having thermal awareness across multiple sub-system domains
US8286111B2 (en) * 2004-03-11 2012-10-09 Gradient Design Automation Inc. Thermal simulation using adaptive 3D and hierarchical grid mechanisms
US8019580B1 (en) 2007-04-12 2011-09-13 Gradient Design Automation Inc. Transient thermal analysis
US7350164B2 (en) * 2004-06-04 2008-03-25 Carnegie Mellon University Optimization and design method for configurable analog circuits and devices
US8818784B1 (en) * 2004-06-23 2014-08-26 Cypress Semiconductor Corporation Hardware description language (HDL) incorporating statistically derived data and related methods
US7458041B2 (en) * 2004-09-30 2008-11-25 Magma Design Automation, Inc. Circuit optimization with posynomial function F having an exponent of a first design parameter
US7669150B2 (en) * 2004-10-29 2010-02-23 Xigmix, Inc. Statistical optimization and design method for analog and digital circuits
WO2007079238A2 (en) * 2005-12-30 2007-07-12 Saudi Arabian Oil Company Computational method for sizing three-phase separators
US7844926B1 (en) * 2006-01-31 2010-11-30 Oracle America, Inc. Specification window violation identification with application in semiconductor device design
US8332188B2 (en) * 2006-03-03 2012-12-11 Solido Design Automation Inc. Modeling of systems using canonical form functions and symbolic regression
US7353473B2 (en) * 2006-05-04 2008-04-01 International Business Machines Corporation Modeling small mosfets using ensemble devices
US7844927B2 (en) * 2007-01-19 2010-11-30 Globalfoundries Inc. Method for quality assured semiconductor device modeling
US20080312885A1 (en) * 2007-06-12 2008-12-18 Justsystems Evans Research, Inc. Hybrid method for simulation optimization
US8001515B2 (en) * 2007-12-21 2011-08-16 National Semiconductor Corporation Simultaneous optimization of analog design parameters using a cost function of responses
US8443329B2 (en) * 2008-05-16 2013-05-14 Solido Design Automation Inc. Trustworthy structural synthesis and expert knowledge extraction with application to analog circuit design
EP2194756B1 (en) * 2008-12-02 2016-07-27 Whirlpool Corporation A method for controlling the induction heating system of a cooking appliance
KR101794069B1 (ko) * 2010-05-26 2017-12-04 삼성전자주식회사 반도체 제조설비 및 그의 시즈닝 공정 최적화 방법
PL2753991T3 (pl) * 2011-09-10 2017-08-31 Abb Schweiz Ag Układ i sposób dla identyfikacji systemu instalacji przemysłowej lub procesu
US9323870B2 (en) 2012-05-01 2016-04-26 Advanced Micro Devices, Inc. Method and apparatus for improved integrated circuit temperature evaluation and IC design
CN102968064B (zh) * 2012-12-10 2015-10-28 上海市电力公司 一种发电机励磁系统模型的动态自动更新方法
US10169507B2 (en) * 2016-11-29 2019-01-01 Taiwan Semiconductor Manufacturing Co., Ltd. Variation-aware circuit simulation
CN109670138B (zh) * 2019-01-28 2023-02-03 三峡大学 基于分数Zener模型的植物油纸绝缘状态评估方法
CN116151172B (zh) * 2023-04-18 2023-07-04 中国电子科技集团公司信息科学研究院 Mems器件模型构建方法、装置及设计方法

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US5392221A (en) * 1991-06-12 1995-02-21 International Business Machines Corporation Procedure to minimize total power of a logic network subject to timing constraints
US6269277B1 (en) * 1998-07-27 2001-07-31 The Leland Stanford Junior University Board Of Trustees System and method for designing integrated circuits
US6295635B1 (en) * 1998-11-17 2001-09-25 Agilent Technologies, Inc. Adaptive Multidimensional model for general electrical interconnection structures by optimizing orthogonal expansion parameters
CN1160776C (zh) * 1999-03-01 2004-08-04 松下电器产业株式会社 晶体管最优化方法、集成电路布局设计方法及其相应装置
US6311145B1 (en) * 1999-06-17 2001-10-30 The Board Of Trustees Of The Leland Stanford Junior University Optimal design of an inductor and inductor circuit
US7065727B2 (en) * 2001-04-25 2006-06-20 Barcelona Design, Inc. Optimal simultaneous design and floorplanning of integrated circuit

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Publication number Publication date
CA2464935A1 (en) 2003-05-08
EP1440396A2 (en) 2004-07-28
US7162402B2 (en) 2007-01-09
IL161675A0 (en) 2004-09-27
WO2003038686A3 (en) 2004-03-18
GB0126104D0 (en) 2002-01-02
WO2003038686A2 (en) 2003-05-08
US20050251373A1 (en) 2005-11-10

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