JP2005351885A - Cv converter - Google Patents

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JP2005351885A
JP2005351885A JP2005038180A JP2005038180A JP2005351885A JP 2005351885 A JP2005351885 A JP 2005351885A JP 2005038180 A JP2005038180 A JP 2005038180A JP 2005038180 A JP2005038180 A JP 2005038180A JP 2005351885 A JP2005351885 A JP 2005351885A
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capacitor
end connected
voltage source
signal voltage
input terminal
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JP4811987B2 (en
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Minoru Sudo
稔 須藤
Mitsuo Shoda
光男 鎗田
Kenji Kato
健二 加藤
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Seiko Instruments Inc
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Seiko Instruments Inc
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G01R27/2605—Measuring capacitance
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
    • G01D5/00—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable
    • G01D5/12—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means
    • G01D5/14—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage
    • G01D5/24—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying capacitance
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16528—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values using digital techniques or performing arithmetic operations
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
    • G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
    • G01R23/06—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage by converting frequency into an amplitude of current or voltage

Abstract

<P>PROBLEM TO BE SOLVED: To provide a CV converter which can use a simple circuit for measuring a plurality of capacity values. <P>SOLUTION: This CV converter enables measurement of two or more capacity values, with few circuit components by impressing time-sharing signal to the capacity. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

この発明は、複数の静電容量の値を電圧に変換するＣＶ変換回路に関する。   The present invention relates to a CV conversion circuit that converts a plurality of capacitance values into voltages.

従来のＣＶ変換回路としては、図7に示されるような回路が知られていた（例えば、特許文献１参照。）。   As a conventional CV conversion circuit, a circuit as shown in FIG. 7 is known (for example, refer to Patent Document 1).

即ち、非反転入力端子が接地された演算増幅器１と、前記演算増幅器１の出力端子と、反転入力端子の間に接続された抵抗３と、一端が前記演算増幅器１の反転入力端子に接続され、他端が信号電圧源４に接続された、検出すべき容量２があり、前記信号電圧源４には、ある電圧振幅Ｖとある角周波数ωの信号が与えられている。すなわち、信号電圧源４の信号電圧をＶｓとすれば、（１）式で表される。   That is, the operational amplifier 1 whose non-inverting input terminal is grounded, the output terminal of the operational amplifier 1, the resistor 3 connected between the inverting input terminals, and one end thereof are connected to the inverting input terminal of the operational amplifier 1. The other end is connected to the signal voltage source 4 and has a capacitor 2 to be detected. The signal voltage source 4 is given a signal having a certain voltage amplitude V and a certain angular frequency ω. That is, if the signal voltage of the signal voltage source 4 is Vs, it is expressed by the equation (1).

Ｖｓ＝Ｖ・ｓｉｎ（ωｔ） …（１）
図７において、反転入力端子は仮想接地されているため、非反転入力端子の接地電位に等しくなっている。仮に、この接地電位を０Ｖとすれば、容量２に流れる電流Ｉは、容量２の値をＣとすれば、（２）式で与えられる。 Vs = V · sin (ωt) (1)
In FIG. 7, since the inverting input terminal is virtually grounded, it is equal to the ground potential of the non-inverting input terminal. If the ground potential is 0 V, the current I flowing through the capacitor 2 is given by the equation (2) if the value of the capacitor 2 is C.

Ｉ＝ｊωＣ・Ｖ・ｓｉｎ（ωｔ） …（２）
従って、演算増幅器１の出力端子５には、抵抗３の抵抗値をＲとすれば、（３）式で与えられる電圧Ｖｏが発生する。 I = jωC · V · sin (ωt) (2)
Therefore, if the resistance value of the resistor 3 is R, the voltage Vo given by the equation (3) is generated at the output terminal 5 of the operational amplifier 1.

Ｖｏ＝−ｊωＣＲ・Ｖ・ｓｉｎ（ωｔ） …（３）
（３）式より、演算増幅器１の出力電圧の振幅Ｖｏは、容量２の値に比例するため、前記振幅Ｖｏを測定する事で、容量２の値を測定する事ができる。 Vo = −jωCR · V · sin (ωt) (3)
From the equation (3), the amplitude Vo of the output voltage of the operational amplifier 1 is proportional to the value of the capacitor 2, so that the value of the capacitor 2 can be measured by measuring the amplitude Vo.

図８に、図７のＣＶ変換回路の各部の時間に対する電圧・電流波形を示す。図８（Ａ）は、信号電圧源４の信号電圧を示している。ここでは、正弦波を与えている。図８（Ｂ）は、容量２及び抵抗３に流れる電流波形であり、図８（Ｃ）は、演算増幅器１の出力端子５に現れる電圧波形である。   FIG. 8 shows voltage / current waveforms with respect to time of the respective parts of the CV conversion circuit of FIG. FIG. 8A shows the signal voltage of the signal voltage source 4. Here, a sine wave is given. FIG. 8B shows a current waveform flowing through the capacitor 2 and the resistor 3, and FIG. 8C shows a voltage waveform appearing at the output terminal 5 of the operational amplifier 1.

複数の容量の値を測定する場合、図８の回路を、測定する容量の数だけ用意する事で、複数の容量値を測定する事ができる。
特開2001-124807号公報（第2図） When measuring a plurality of capacitance values, a plurality of capacitance values can be measured by preparing the circuit of FIG. 8 by the number of capacitances to be measured.
Japanese Patent Laid-Open No. 2001-124807 (Fig. 2)

従来のＣＶ変換回路では、測定する容量の数だけ、ＣＶ変換回路が必要となり、複数の容量を測定すると回路の規模が大きくなるという課題があった。   The conventional CV conversion circuit requires CV conversion circuits as many as the number of capacitances to be measured, and there is a problem in that the circuit scale increases when a plurality of capacitances are measured.

そこで、この発明の目的は従来のこのような課題を解決するために、少ない回路規模で複数の容量を測定することを目的としている。   Accordingly, an object of the present invention is to measure a plurality of capacitors with a small circuit scale in order to solve the conventional problems.

本願発明にかかるＣＶ変換回路は、反転入力端子が出力端子に接続された演算増幅器と、
一端が前記演算増幅器の非反転入力端子に接続され、他端が接地された抵抗と、
一端が前記演算増幅器の非反転入力端子に接続され、他端が第一の信号電圧源に接続された第一の容量と、
一端が前記演算増幅器の非反転入力端子に接続され、他端が第一の信号電圧源の反転出力に接続された第二の容量と、
一端が前記演算増幅器の反転入力端子に接続され、他端が第二の信号電圧源に接続された第三の容量と、
一端が前記演算増幅器の非反転入力端子に接続され、他端が第二の信号電圧源の反転出力に接続された第四の容量とを有するＣＶ変換回路において、
前記第一の信号電圧源と、前記第二の信号電圧源が、時分割的に信号パルスを発生し、前記信号パルスに同期して検波するＣＶ変換回路とした。
また、反転入力端子が出力端子に接続された演算増幅器と、
一端が前記演算増幅器の非反転入力端子に接続され、他端が接地された抵抗と、
一端が前記演算増幅器の非反転入力端子に接続され、他端が第一の信号電圧源に接続された第一の容量と、
一端が前記演算増幅器の非反転入力端子に接続され、他端が第一の信号電圧源の反転出力に接続された第二の容量と、
一端が前記演算増幅器の反転入力端子に接続され、他端が第二の信号電圧源に接続された第三の容量と、
を有するＣＶ変換回路において、
前記第一の信号電圧源と、前記第二の信号電圧源が、時分割的に信号パルスを発生し、前記信号パルスに同期して検波するＣＶ変換回路とした。
また、反転入力端子が出力端子に接続された演算増幅器と、
一端が前記演算増幅器の非反転入力端子に接続され、他端が接地された抵抗と、
一端が前記演算増幅器の非反転入力端子に接続され、他端が第一の信号電圧源に接続された第一の容量と、
一端が前記演算増幅器の反転入力端子に接続され、他端が第二の信号電圧源に接続された第二の容量と、
一端が前記演算増幅器の非反転入力端子に接続され、他端が第二の信号電圧源の反転出力に接続された第三の容量と、
を有するＣＶ変換回路において、
前記第一の信号電圧源と、前記第二の信号電圧源が、時分割的に信号パルスを発生し、前記信号パルスに同期して検波するＣＶ変換回路とした。
また、反転入力端子が出力端子に接続された演算増幅器と、
一端が前記演算増幅器の非反転入力端子に接続され、他端が接地された抵抗と、
一端が前記演算増幅器の非反転入力端子に接続され、他端が第一の信号電圧源に接続された第一の容量と、
一端が前記演算増幅器の反転入力端子に接続され、他端が第二の信号電圧源に接続された第二の容量と、
を有するＣＶ変換回路において、
前記第一の信号電圧源と、前記第二の信号電圧源が、時分割的に信号パルスを発生し、前記信号パルスに同期して検波するＣＶ変換回路とした。
さらに、上記ＣＶ変換回路において、前記信号電圧源が、３つ以上で、かつ、前記信号源に接続する容量が３つ以上であるCV変換回路とした。
さらに、前記反転入力端子に接続される全容量値の和Cと、前記抵抗の値RによるCRの時定数の値が、前記第一及び前期第二の信号電圧源の信号パルス時間よりも、小さいＣＶ変換回路とした。
さらに、前記抵抗の値を前記信号電圧源に同期して変更するＣＶ変換回路とした。
さらに、前記信号電圧源の振幅電圧値が異なるＣＶ変換回路とした。 The CV conversion circuit according to the present invention includes an operational amplifier having an inverting input terminal connected to an output terminal,
A resistor having one end connected to the non-inverting input terminal of the operational amplifier and the other end grounded;
A first capacitor having one end connected to the non-inverting input terminal of the operational amplifier and the other end connected to a first signal voltage source;
A second capacitor having one end connected to the non-inverting input terminal of the operational amplifier and the other end connected to the inverting output of the first signal voltage source;
A third capacitor having one end connected to the inverting input terminal of the operational amplifier and the other end connected to a second signal voltage source;
In a CV conversion circuit having a fourth capacitor having one end connected to the non-inverting input terminal of the operational amplifier and the other end connected to the inverting output of the second signal voltage source,
The first signal voltage source and the second signal voltage source generate a signal pulse in a time-sharing manner, and a CV conversion circuit that detects in synchronization with the signal pulse is used.
An operational amplifier having an inverting input terminal connected to the output terminal;
A resistor having one end connected to the non-inverting input terminal of the operational amplifier and the other end grounded;
A first capacitor having one end connected to the non-inverting input terminal of the operational amplifier and the other end connected to a first signal voltage source;
A second capacitor having one end connected to the non-inverting input terminal of the operational amplifier and the other end connected to the inverting output of the first signal voltage source;
A third capacitor having one end connected to the inverting input terminal of the operational amplifier and the other end connected to a second signal voltage source;
In the CV conversion circuit having
The first signal voltage source and the second signal voltage source generate a signal pulse in a time-sharing manner, and a CV conversion circuit that detects in synchronization with the signal pulse is used.
An operational amplifier having an inverting input terminal connected to the output terminal;
A resistor having one end connected to the non-inverting input terminal of the operational amplifier and the other end grounded;
A first capacitor having one end connected to the non-inverting input terminal of the operational amplifier and the other end connected to a first signal voltage source;
A second capacitor having one end connected to the inverting input terminal of the operational amplifier and the other end connected to a second signal voltage source;
A third capacitor having one end connected to the non-inverting input terminal of the operational amplifier and the other end connected to the inverting output of the second signal voltage source;
In the CV conversion circuit having
The first signal voltage source and the second signal voltage source generate a signal pulse in a time-sharing manner, and a CV conversion circuit that detects in synchronization with the signal pulse is used.
An operational amplifier having an inverting input terminal connected to the output terminal;
A resistor having one end connected to the non-inverting input terminal of the operational amplifier and the other end grounded;
A first capacitor having one end connected to the non-inverting input terminal of the operational amplifier and the other end connected to a first signal voltage source;
A second capacitor having one end connected to the inverting input terminal of the operational amplifier and the other end connected to a second signal voltage source;
In the CV conversion circuit having
The first signal voltage source and the second signal voltage source generate a signal pulse in a time-sharing manner, and a CV conversion circuit that detects in synchronization with the signal pulse is used.
Furthermore, in the CV conversion circuit, the CV conversion circuit has three or more signal voltage sources and three or more capacitors connected to the signal source.
Furthermore, the sum C of all capacitance values connected to the inverting input terminal, and the value of the CR time constant due to the value R of the resistor, than the signal pulse time of the first and second signal voltage sources, A small CV conversion circuit was used.
Furthermore, a CV conversion circuit that changes the value of the resistor in synchronization with the signal voltage source is provided.
Further, the CV conversion circuit has different amplitude voltage values of the signal voltage source.

本願発明にかかるＣＶ変換回路は、複数の容量の値を少ない回路で測定できるという効果がある。   The CV conversion circuit according to the present invention has an effect that a plurality of capacitance values can be measured with a small number of circuits.

上記課題を解決するために、この発明ではＣＶ変換回路において、複数の測定する容量に対して時分割で信号パルスを容量に印加するようにした。さらに、駆動電圧に同期して、抵抗の値を変えるようにした。   In order to solve the above problems, in the present invention, in the CV conversion circuit, signal pulses are applied to the capacitors in a time-division manner for a plurality of capacitors to be measured. Furthermore, the resistance value is changed in synchronization with the drive voltage.

以下に、本発明の実施例を図面に基づいて説明する。図１は、本発明の第一の実施例を示すＣＶ変換回路である。 第一の容量２Aと第二の容量２Bとがあり、２Aと２Bは、どちらか一方が基準容量で、他方の容量が、測定すべき容量である。同様に、第三の容量３Aと第四の容量３Bとがあり、どちらか一方が基準容量で、他方の容量が、測定すべき容量である。   Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a CV conversion circuit showing a first embodiment of the present invention. There are a first capacity 2A and a second capacity 2B, and either 2A or 2B is a reference capacity, and the other capacity is a capacity to be measured. Similarly, there are a third capacitor 3A and a fourth capacitor 3B, one of which is a reference capacitor and the other is a capacitor to be measured.

前記４つの容量全ての一端が、共通になっており、それが演算増幅器１の非反転入力端子に接続されている。演算増幅器１は、出力端子１０と反転入力端子を接続した、ボルテージ・フォロアとなっている。演算増幅器１の非反転入力端子には、抵抗９が接続され、抵抗９の他端は、接地されている。   One end of all the four capacitors is common, and it is connected to the non-inverting input terminal of the operational amplifier 1. The operational amplifier 1 is a voltage follower in which an output terminal 10 and an inverting input terminal are connected. A resistor 9 is connected to the non-inverting input terminal of the operational amplifier 1, and the other end of the resistor 9 is grounded.

第一の容量２Aの他端は、第一の信号電圧源４に接続されている。インバータ６の入力は第一の信号電圧源４に接続されており、そのインバータ６の出力は、第二の容量２Bの他端に接続されている。すなわち、第一の容量２Aと第二の容量２Bは、逆相で駆動している。   The other end of the first capacitor 2 </ b> A is connected to the first signal voltage source 4. The input of the inverter 6 is connected to the first signal voltage source 4, and the output of the inverter 6 is connected to the other end of the second capacitor 2B. That is, the first capacitor 2A and the second capacitor 2B are driven in opposite phases.

第三の容量３Aの他端は、第二の信号電圧源５に接続されている。インバータ７の入力は第二の信号電圧源５に接続されており、そのインバータ７の出力は、第四の容量３Bの他端に接続されている。すなわち、第三の容量３Aと第四の容量３Bは、逆相で駆動している。   The other end of the third capacitor 3 </ b> A is connected to the second signal voltage source 5. The input of the inverter 7 is connected to the second signal voltage source 5, and the output of the inverter 7 is connected to the other end of the fourth capacitor 3B. That is, the third capacitor 3A and the fourth capacitor 3B are driven in opposite phases.

図２に、横軸を時間とした、図1のCV変換回路の各部の電圧波形を示す。
図２（Ａ）は、信号電圧源４及び５の基本となるクロックの波形を示している。図２（Ｂ）は、図２（Ａ）のクロックを分周した波形を示している。図２（Ｃ）は、図１の第一の信号電圧源４の出力波形である。この波形は、図２（Ａ）と（Ｂ）のＡＮＤによって、簡単に生成することができる。図２（Ｄ）は、図２（Ｃ）の電圧波形にて、容量２Ａ及び２Ｂを駆動したときに、演算増幅器１の出力端子１０に現れる電圧波形である。 FIG. 2 shows voltage waveforms at various parts of the CV conversion circuit of FIG. 1, with the horizontal axis representing time.
FIG. 2A shows the waveform of the clock that is the basis of the signal voltage sources 4 and 5. FIG. 2B shows a waveform obtained by dividing the clock of FIG. FIG. 2C shows an output waveform of the first signal voltage source 4 of FIG. This waveform can be easily generated by AND of FIGS. 2 (A) and 2 (B). 2D is a voltage waveform that appears at the output terminal 10 of the operational amplifier 1 when the capacitors 2A and 2B are driven with the voltage waveform of FIG.

今、第一の容量２Ａの値をC2A、第二の容量２Bの値をC2Bとすると、その容量値の引き算を、Cxとする。すなわち、Cx=C2A−C2Bとする。 If the value of the first capacitor 2A is C 2A and the value of the second capacitor 2B is C 2B , the subtraction of the capacitance value is Cx. That is, Cx = C 2A −C 2B .

図２（Ｄ）の電圧波形は、Cxの値に依存し、Cxが正の場合は、図２（Ｄ）のように図２（Ｃ）の波形の立ち上がりで、上にスパイクが発生する。逆に、Ｃｘが負の場合は、図２（Ｄ）とは逆に、図２（Ｃ）の波形の立ち上がりで、下にスパイクが発生する。   The voltage waveform in FIG. 2D depends on the value of Cx. When Cx is positive, a spike is generated at the rising edge of the waveform in FIG. 2C as shown in FIG. Conversely, when Cx is negative, a spike is generated at the bottom of the waveform of FIG. 2C, contrary to FIG. 2D.

図２（Ｄ）のスパイクの高さは、第一の信号電圧源４の信号パルス振幅及び、インバータ６の電源、すなわち、信号パルス振幅が一定であれば、Cxの値に依存し、Cxが大きければ、スパイクの高さは高くなり、Cxが小さければ、スパイクの高さは低くなる。   The height of the spike in FIG. 2D depends on the value of Cx if the signal pulse amplitude of the first signal voltage source 4 and the power source of the inverter 6, that is, the signal pulse amplitude is constant. If it is large, the spike height is high, and if Cx is small, the spike height is low.

すなわち、このスパイクを計測することで、CV変換が可能となる。   That is, CV conversion is possible by measuring this spike.

また、図２（Ｄ）のスパイクの放電波形は、非反転入力端子の全容量をＣＴとし、抵抗９の抵抗値をＲとすれば、ＣＴ・Ｒの時定数で、放電されることになる。
ここで、その時定数が、図２（Ｃ）の“Ｈ”となっている時間（駆動パルス時間）を超える場合、図２（Ｃ）の波形が“Ｈ”→“Ｌ”に下がる時点で、演算増幅器１の出力１０が接地電圧にならず、測定誤差が発生する。したがって、ＣＴ・Ｒの値は、信号電圧源が、容量を駆動するときのパルス時間よりも、小さいことが必要である。 Moreover, the spike discharge waveform of FIG. 2 (D) the total volume of the non-inverting input terminal and C T, if the resistance value of the resistor 9 is R, a time constant of C T · R, it is discharged become.
Here, when the time constant exceeds the time (drive pulse time) of “H” in FIG. 2 (C), the waveform in FIG. 2 (C) falls from “H” to “L”. The output 10 of the operational amplifier 1 does not become the ground voltage, and a measurement error occurs. Therefore, the value of CT / R needs to be smaller than the pulse time when the signal voltage source drives the capacitor.

図２（Ｅ）は、図１の第二の信号電圧源５の出力波形である。この波形は、図２（Ａ）と（Ｂ）の反転波形のＡＮＤによって、簡単に生成することができる。図２（Ｆ）は、図２（Ｅ）の電圧波形にて、容量３Ａ及び３Ｂを駆動したときに、演算増幅器１の出力端子１０に現れる電圧波形である。   FIG. 2E shows an output waveform of the second signal voltage source 5 of FIG. This waveform can be easily generated by ANDing the inverted waveforms of FIGS. 2 (A) and 2 (B). FIG. 2F is a voltage waveform that appears at the output terminal 10 of the operational amplifier 1 when the capacitors 3A and 3B are driven with the voltage waveform of FIG.

今、第三の容量３Ａの値をC3A、第四の容量３Bの値をC3Bとすると、その容量値の引き算を、Cyとする。すなわち、Cy=C3A−C3Bとする。図２（Ｆ）の波形は、図２（Ｃ）と同様に、Cyの値に依存する。
図２（Ｇ）は、信号電圧源４と５によって、容量２Ａ、２Ｂ、３Ａ、３Ｂが駆動された結果、演算増幅器１の出力端子１０に現れる電圧波形で、図２（Ｄ）及び（Ｆ）の和である。 Now, assuming that the value of the third capacitor 3A is C 3A and the value of the fourth capacitor 3B is C 3B , the subtraction of the capacitance value is Cy. That is, Cy = C 3A −C 3B . The waveform in FIG. 2 (F) depends on the value of Cy as in FIG. 2 (C).
FIG. 2G shows voltage waveforms appearing at the output terminal 10 of the operational amplifier 1 as a result of driving the capacitors 2A, 2B, 3A, and 3B by the signal voltage sources 4 and 5, and FIG. ).

図２（Ｈ）〜（Ｋ）は、演算増幅器１の出力端子１０の電圧波形を検波するときの信号を示している。図２（Ｈ）は（Ｃ）と同じで、（Ａ）と（Ｂ）のＡＮＤによって、簡単に生成することができる。図２（Ｉ）は、（Ａ）の反転と、（Ｂ）のＡＮＤによって、簡単に生成することができる。図２（Ｊ）は、（Ｅ）と同じで、（Ａ）と（Ｂ）の反転のＡＮＤによって、簡単に生成することができる。図２（Ｋ）は、（Ａ）の反転と、（Ｂ）の反転のＡＮＤによって、簡単に生成することができる。   FIGS. 2H to 2K show signals when detecting the voltage waveform at the output terminal 10 of the operational amplifier 1. FIG. 2 (H) is the same as (C), and can be easily generated by ANDing (A) and (B). FIG. 2I can be easily generated by inversion of (A) and AND of (B). FIG. 2J is the same as FIG. 2E, and can be easily generated by AND of (A) and (B) inversion. FIG. 2K can be easily generated by AND of (A) inversion and (B) inversion.

図３に、同期検波回路の例を示す。スイッチS1〜S4があり、S1とS3及び、S2とS4は相補的にON/OFFする。すなわち、S1がONの時には、S3がOFF、S2がOFFの時には、S4がONとなるように動作する。   FIG. 3 shows an example of the synchronous detection circuit. There are switches S1 to S4, and S1 and S3 and S2 and S4 are complementarily turned ON / OFF. That is, when S1 is ON, S3 is OFF, and when S2 is OFF, S4 is ON.

図１の演算増幅器１の出力端子１０が、図３の同期検波回路の入力端子ＩＮに接続される。   The output terminal 10 of the operational amplifier 1 in FIG. 1 is connected to the input terminal IN of the synchronous detection circuit in FIG.

図３の同期検波回路は、測定しようとする容量の数だけ必要になる。   The number of the synchronous detection circuits in FIG. 3 is required by the number of capacitors to be measured.

今、第一の容量２Ａと第二の容量２Ｂによる容量差Ｃｘを測定する場合、図２（Ｈ）の信号が“Ｈ”の時、Ｓ２とＳ３をＯＮ（Ｓ１とＳ４をＯＦＦ）し、図２（Ｉ）の信号が“Ｈ”の時、Ｓ１とＳ４をＯＮ（Ｓ２とＳ３をＯＦＦ）する。   When measuring the capacitance difference Cx between the first capacitor 2A and the second capacitor 2B, when the signal in FIG. 2 (H) is “H”, S2 and S3 are turned on (S1 and S4 are turned off), When the signal in FIG. 2I is “H”, S1 and S4 are turned on (S2 and S3 are turned off).

これによって、第一の容量２Ａと第二の容量２Ｂによる容量差Ｃｘによって発生する演算増幅器１の出力を検出することが可能となる。   As a result, it is possible to detect the output of the operational amplifier 1 generated by the capacitance difference Cx between the first capacitor 2A and the second capacitor 2B.

別の同期検波回路によって、第三の容量３Ａと第四の容量３Ｂによる容量差Ｃyを測定する場合、図２（Ｊ）の信号が“Ｈ”の時、Ｓ２とＳ３をＯＮ（Ｓ１とＳ４をＯＦＦ）し、図２（Ｋ）の信号が“Ｈ”の時、Ｓ１とＳ４をＯＮ（Ｓ２とＳ３をＯＦＦ）する。   When the capacitance difference Cy between the third capacitor 3A and the fourth capacitor 3B is measured by another synchronous detection circuit, when the signal in FIG. 2J is “H”, S2 and S3 are turned on (S1 and S4). 2), and when the signal in FIG. 2K is “H”, S1 and S4 are turned on (S2 and S3 are turned off).

これによって、第三の容量３Ａと第四の容量３Ｂによる容量差Ｃｙによって発生する演算増幅器１の出力を検出することが可能となる。   As a result, it is possible to detect the output of the operational amplifier 1 generated by the capacitance difference Cy between the third capacitor 3A and the fourth capacitor 3B.

同期検波後は、図３のOUT端子の出力を必要に応じてロー・パス・フィルタにかけ、必要に応じて増幅することで、CV変換が可能となる。   After synchronous detection, CV conversion becomes possible by applying the output of the OUT terminal in FIG. 3 to a low-pass filter as necessary and amplifying as necessary.

すなわち、一つの演算増幅器と一つの抵抗で、２つの容量値の測定が可能となる。   That is, two capacitance values can be measured with one operational amplifier and one resistor.

尚、前述の説明では、簡単化のため、第一の容量２Aと第二の容量２Bの、どちらか一方が基準容量で、他方の容量が、測定すべき容量とし、同様に、第三の容量３Aと第四の容量３Bのどちらか一方が基準容量で、他方の容量が、測定すべき容量と述べたが、本回路は、あくまでも、第一の容量２Ａと第二の容量２Bの容量差、または、第三の容量３Aと第四の容量３Bの容量差を検出する回路であり、必ずしも、どちらか一方を基準容量とする必要は無いことは、明白である。   In the above description, for simplification, one of the first capacitor 2A and the second capacitor 2B is a reference capacitor, and the other capacitor is a capacitor to be measured. Although one of the capacity 3A and the fourth capacity 3B is a reference capacity and the other capacity is a capacity to be measured, this circuit is only a capacity of the first capacity 2A and the second capacity 2B. It is a circuit that detects the difference or the capacitance difference between the third capacitor 3A and the fourth capacitor 3B, and it is obvious that one of them is not necessarily used as the reference capacitor.

また、前述の説明では、一組の容量の差を検出すると記載しているが、片側の容量がなくとも、すなわち片側の容量値がゼロであっても容量の差として検出可能なことは明白である。   Further, in the above description, it is described that a difference between a set of capacitances is detected. It is.

図４は、本発明の第二の実施例を示すＣＶ変換回路である。図１との違いは、第五の容量１２Ａと第六の容量１２Ｂの一端が演算増幅器１の非反転入力端子に接続されており、第五の容量１２Ａの他端は第三の信号電圧源１４に接続されている。また、インバータ１６の入力は第三の信号電圧源１４に接続されており、そのインバータ１６の出力は、第六の容量１２Bの他端に接続されている。すなわち、第五の容量１２Aと第六の容量１２Bは、逆相で駆動している。また、第一の信号電圧源４と、第二の信号電圧源５と第三の信号電圧源１４は、時分割的に信号パルスを発生している。それ以外は、図１と同様である。   FIG. 4 is a CV conversion circuit showing a second embodiment of the present invention. The difference from FIG. 1 is that one end of the fifth capacitor 12A and the sixth capacitor 12B is connected to the non-inverting input terminal of the operational amplifier 1, and the other end of the fifth capacitor 12A is the third signal voltage source. 14. The input of the inverter 16 is connected to the third signal voltage source 14, and the output of the inverter 16 is connected to the other end of the sixth capacitor 12B. That is, the fifth capacitor 12A and the sixth capacitor 12B are driven in opposite phases. The first signal voltage source 4, the second signal voltage source 5, and the third signal voltage source 14 generate signal pulses in a time division manner. The rest is the same as FIG.

図５に図４のＣＶ変換回路の横軸時間に対する各部の電圧波形を示す。
図５（Ａ）は、基本となるクロックの波形を示している。図５（Ｂ）は、図４の第一の信号電圧源４の出力波形である。図５（Ｃ）は、図５（Ｂ）の電圧波形にて、容量２Ａ及び２Ｂを駆動したときに、演算増幅器１の出力端子１０に現れる電圧波形である。
図５（Ｄ）は、図４の第二の信号電圧源５の出力波形である。図５（Ｅ）は、図５（Ｄ）の電圧波形にて、容量３Ａ及び３Ｂを駆動したときに、演算増幅器１の出力端子１０に現れる電圧波形である。
図５（Ｆ）は、図４の第三の信号電圧源１４の出力波形である。図５（Ｇ）は、図５（Ｆ）の電圧波形にて、容量１２Ａ及び１２Ｂを駆動したときに、演算増幅器１の出力端子１０に現れる電圧波形である。 FIG. 5 shows voltage waveforms of respective parts with respect to the horizontal axis time of the CV conversion circuit of FIG.
FIG. 5A shows a basic clock waveform. FIG. 5B shows an output waveform of the first signal voltage source 4 of FIG. 5C is a voltage waveform that appears at the output terminal 10 of the operational amplifier 1 when the capacitors 2A and 2B are driven with the voltage waveform of FIG. 5B.
FIG. 5D shows an output waveform of the second signal voltage source 5 of FIG. FIG. 5E is a voltage waveform that appears at the output terminal 10 of the operational amplifier 1 when the capacitors 3A and 3B are driven with the voltage waveform of FIG.
FIG. 5F shows an output waveform of the third signal voltage source 14 of FIG. 5G is a voltage waveform that appears at the output terminal 10 of the operational amplifier 1 when the capacitors 12A and 12B are driven with the voltage waveform of FIG.

図５（Ｈ）は、信号電圧源４と５と１４によって、容量２Ａ、２Ｂ、３Ａ、３Ｂ、１２Ａ、１２Ｂが駆動された結果、演算増幅器１の出力端子１０に現れる電圧波形で、図５（Ｃ）及び（Ｅ）及び（Ｇ）の和である。   FIG. 5H shows voltage waveforms that appear at the output terminal 10 of the operational amplifier 1 as a result of driving the capacitors 2A, 2B, 3A, 3B, 12A, and 12B by the signal voltage sources 4, 5, and 14. It is the sum of (C) and (E) and (G).

図５（Ｊ）〜（Ｐ）は、演算増幅器１の出力端子１０の電圧波形を検波するときの信号を示している。図５（Ｊ）〜（Ｍ）は、実施例１と同様である。
同期検波回路によって、第五の容量１２Ａと第六の容量１２Ｂによる容量差Ｃzを測定する場合、図５（O）の信号が“Ｈ”の時、図３のＳ２とＳ３をＯＮ（Ｓ１とＳ４をＯＦＦ）し、図５（P）の信号が“Ｈ”の時、図３のＳ１とＳ４をＯＮ（Ｓ２とＳ３をＯＦＦ）する。 FIGS. 5J to 5P show signals when detecting the voltage waveform at the output terminal 10 of the operational amplifier 1. 5J to 5M are the same as those in the first embodiment.
When the capacitance difference Cz between the fifth capacitor 12A and the sixth capacitor 12B is measured by the synchronous detection circuit, when the signal in FIG. 5 (O) is “H”, S2 and S3 in FIG. S4 is turned OFF, and when the signal in FIG. 5P is “H”, S1 and S4 in FIG. 3 are turned ON (S2 and S3 are turned OFF).

これによって、第五の容量１２Ａと第六の容量１２Bによる容量差Ｃzによって発生する演算増幅器１の出力を検出することが可能となる。   As a result, it is possible to detect the output of the operational amplifier 1 generated by the capacitance difference Cz between the fifth capacitor 12A and the sixth capacitor 12B.

すなわち、一つの演算増幅器と一つの抵抗で、３つの容量値の測定が可能となる。   That is, three capacitance values can be measured with one operational amplifier and one resistor.

以上、説明から判るように、測定する容量の数だけ、時分割でその容量を駆動することで、３つ以上の容量値を一つの演算増幅器と一つの抵抗で、測定することが可能となることは、明白である。   As described above, it is possible to measure three or more capacitance values with one operational amplifier and one resistor by driving the capacitors in a time-division manner by the number of capacitors to be measured. That is obvious.

図６は、本発明の第三の実施例を示すＣＶ変換回路である。図１との違いは、抵抗９が、９Aと９Bの２つの抵抗となっており、９Bに並列に、スイッチ２１が付加されており、前記スイッチ２１は、第一の信号電圧源４の信号と、第二の信号電圧源５の信号を入力とするロジック回路２０の出力によって、制御されている。（ロジック回路２０の入力は、第一の信号電圧源４の信号と、第二の信号電圧源５の信号そのものである必要はなく、第一の信号電圧源４の信号または、第二の信号電圧源５の信号と同期した信号が得られれば良い。）
非反転入力端子の全容量をＣＴとし、抵抗９Aの抵抗値をR9A、抵抗９Bの抵抗値をR9Bとすれば、スイッチ２１がONしているときは、容量検出時のスパイク電圧がＣＴ・R9Aの時定数で放電され、スイッチ２１がOFFしているときは、容量検出時のスパイク電圧がＣＴ・（R9A+R9B）の時定数で放電さることになる。 FIG. 6 is a CV conversion circuit showing a third embodiment of the present invention. The difference from FIG. 1 is that the resistor 9 is two resistors 9A and 9B, and a switch 21 is added in parallel with 9B. The switch 21 is a signal of the first signal voltage source 4. And the output of the logic circuit 20 that receives the signal of the second signal voltage source 5 as an input. (The input of the logic circuit 20 does not have to be the signal of the first signal voltage source 4 and the signal of the second signal voltage source 5 itself, but the signal of the first signal voltage source 4 or the second signal. It is sufficient that a signal synchronized with the signal of the voltage source 5 is obtained.)
The total volume of the non-inverting input terminal and C T, the resistance of the resistor 9A R 9A, the resistance value of the resistor 9B if R 9B, when the switch 21 is ON, the spike voltage for the capacitive detection When discharge is performed with a time constant of C T · R 9A and the switch 21 is OFF, the spike voltage at the time of capacitance detection is discharged with a time constant of C T · (R 9A + R 9B ).

仮に、第一の容量２Aと第二の容量２Bの容量差Cxの値が大きいときは、第一の電圧信号源４及び、インバータ６で、容量を駆動したときに、図２（Ｄ）のピーク電圧が大きくなる。一方、第三の容量３Aと第四の容量３Bの容量差Cyの値が小さいときは、第二の電圧信号源５及び、インバータ７で、容量を駆動したときに、図２（Ｆ）のピーク電圧が小さくなる。その場合、非反転入力端子と接地電位間に接続されている抵抗の値を大きくすれば、図２（Ｄ）の波形が歪むことになり、抵抗の値を小さくすれば、図２（Ｆ）の波形が、ほとんど得られない（ノイズにうもれる）という問題が発生する。   If the value of the capacitance difference Cx between the first capacitor 2A and the second capacitor 2B is large, when the capacitor is driven by the first voltage signal source 4 and the inverter 6, as shown in FIG. The peak voltage increases. On the other hand, when the value of the capacitance difference Cy between the third capacitor 3A and the fourth capacitor 3B is small, when the capacitor is driven by the second voltage signal source 5 and the inverter 7, as shown in FIG. The peak voltage is reduced. In that case, if the value of the resistor connected between the non-inverting input terminal and the ground potential is increased, the waveform of FIG. 2D is distorted, and if the value of the resistor is decreased, FIG. This causes a problem that the waveform of (1) is almost unobtainable (depressed by noise).

しかし、図２（Ｂ）が“Ｈ”の時に、図６のスイッチ２１を、ONするようにすることで容量差が大きいときには、非反転入力端子と接地電位間の抵抗値を小さくし（R9A）、容量差が小さいときには、非反転入力端子と接地電位間の抵抗値を大きく（R9A+R9B）することで、良好なCV変換を行うことが可能となる。 However, when the capacitance difference is large by turning ON the switch 21 of FIG. 6 when FIG. 2B is “H”, the resistance value between the non-inverting input terminal and the ground potential is reduced (R 9A ) When the capacitance difference is small, it is possible to perform good CV conversion by increasing the resistance value between the non-inverting input terminal and the ground potential (R 9A + R 9B ).

抵抗値を変えることは、CV変換の感度を変えることになるため、同期検波後の出力は、フィルタにかけた後、抵抗値に応じて、必要があれば増幅率を変えてCV変換の出力をとりだす。   Changing the resistance value changes the sensitivity of the CV conversion, so the output after synchronous detection is filtered and the output of the CV conversion is changed by changing the amplification factor if necessary according to the resistance value. Take it out.

また、第一の容量２Aと第二の容量２Bの容量差Cxの値が大きいときは、第一の電圧信号源４及び、インバータ６の電源振幅を小さくし、第三の容量３Aと第四の容量３Bの容量差Cyの値が小さいときは、第二の電圧信号源５及び、インバータ７の電源振幅を大きくすることで、図２（Ｄ）及び図２（Ｆ）のピーク電圧をある程度の範囲内に設定することが可能となる。すなわち、容量差に応じて、容量を駆動する電圧の振幅を変えることで、良好なCV変換を行うことが可能となる。   When the value of the capacitance difference Cx between the first capacitor 2A and the second capacitor 2B is large, the power supply amplitudes of the first voltage signal source 4 and the inverter 6 are reduced, and the third capacitor 3A and the fourth capacitor 4 When the value of the capacitance difference Cy of the capacitor 3B is small, the peak voltage of FIGS. 2D and 2F is increased to some extent by increasing the power supply amplitude of the second voltage signal source 5 and the inverter 7. It is possible to set within the range. That is, it is possible to perform good CV conversion by changing the amplitude of the voltage for driving the capacitor according to the capacitance difference.

容量を駆動する電圧の振幅を変えることは、CV変換の感度を変えることになるため、同期検波後の出力は、フィルタにかけた後、容量を駆動する電圧の振幅に応じて、必要があれば増幅率を変えてCV変換の出力をとりだす。   Changing the amplitude of the voltage that drives the capacitor changes the sensitivity of the CV conversion, so the output after synchronous detection is filtered, and if necessary, depending on the amplitude of the voltage that drives the capacitor. The output of CV conversion is taken out by changing the amplification factor.

以上、実施例１〜３では、演算増幅器１の非反転入力端子は全て、０Ｖに接地しているが、０Ｖである必要はなく、ある任意の電圧であれば、その任意の電圧を基準に、演算増幅器１の出力電圧が発生する。   As described above, in the first to third embodiments, all the non-inverting input terminals of the operational amplifier 1 are grounded to 0V, but need not be 0V, and any arbitrary voltage can be used as a reference. The output voltage of the operational amplifier 1 is generated.

また、第一の容量２Aと第二の容量２B、第三の容量３Aと第四の容量３B、第五の容量１２Aと第６の容量１２Bのどちらか片方が必ずしも、基準容量である必要はなく、本発明のCV変換回路は、２つの容量差を検出することができる。   In addition, one of the first capacitor 2A and the second capacitor 2B, the third capacitor 3A and the fourth capacitor 3B, or the fifth capacitor 12A and the sixth capacitor 12B is not necessarily the reference capacitor. Instead, the CV conversion circuit of the present invention can detect two capacitance differences.

以上説明したように、本発明によればＣＶ変換回路おいて、少ない回路で複数の容量を測定することが可能となる。   As described above, according to the present invention, a plurality of capacitors can be measured with a small number of circuits in a CV conversion circuit.

本発明の第一の実施例のＣＶ変換回路である。1 is a CV conversion circuit according to a first embodiment of the present invention. 本発明の第一の実施例のＣＶ変換回路の電圧波形である。It is a voltage waveform of the CV conversion circuit of the first embodiment of the present invention. 同期検波回路の例である。It is an example of a synchronous detection circuit. 本発明の第二の実施例のＣＶ変換回路である。It is a CV conversion circuit of the second embodiment of the present invention. 本発明の第二の実施例のＣＶ変換回路の電圧波形である。It is a voltage waveform of the CV conversion circuit of the 2nd Example of this invention. 本発明の第三の実施例のＣＶ変換回路である。It is a CV conversion circuit of the third embodiment of the present invention. 従来のＣＶ変換回路である。This is a conventional CV conversion circuit. 従来のＣＶ変換回路の電圧電流波形である。It is a voltage-current waveform of the conventional CV conversion circuit.

符号の説明Explanation of symbols

１ 演算増幅器
２Ａ、２Ｂ、３A、３B、１２A、１２B 容量
９、９A、９B 抵抗
４、５、１４ 信号電圧源
６、７、１６ インバータ 1 operational amplifier 2A, 2B, 3A, 3B, 12A, 12B capacity 9, 9A, 9B resistor 4, 5, 14 signal voltage source 6, 7, 16 inverter

Claims (8)

反転入力端子が出力端子に接続された演算増幅器と、
一端が前記演算増幅器の非反転入力端子に接続され、他端が接地された抵抗と、
一端が前記非反転入力端子に接続され、他端が第一の信号電圧源に接続された第一の容量と、
一端が前記非反転入力端子に接続され、他端が第一の信号電圧源の反転出力に接続された第二の容量と、
一端が前記反転入力端子に接続され、他端が第二の信号電圧源に接続された第三の容量と、
一端が前記非反転入力端子に接続され、他端が第二の信号電圧源の反転出力に接続された第四の容量と、
を有するＣＶ変換回路において、
前記第一の信号電圧源と、前記第二の信号電圧源が、時分割的に信号パルスを発生するとともに、前記信号パルスに同期して検波することを特徴とするＣＶ変換回路。 An operational amplifier with an inverting input terminal connected to the output terminal;
A resistor having one end connected to the non-inverting input terminal of the operational amplifier and the other end grounded;
A first capacitor having one end connected to the non-inverting input terminal and the other end connected to a first signal voltage source;
A second capacitor having one end connected to the non-inverting input terminal and the other end connected to the inverting output of the first signal voltage source;
A third capacitor having one end connected to the inverting input terminal and the other end connected to a second signal voltage source;
A fourth capacitor having one end connected to the non-inverting input terminal and the other end connected to the inverting output of the second signal voltage source;
In the CV conversion circuit having
The CV conversion circuit, wherein the first signal voltage source and the second signal voltage source generate a signal pulse in a time-division manner and detect in synchronization with the signal pulse. 反転入力端子が出力端子に接続された演算増幅器と、
一端が前記演算増幅器の非反転入力端子に接続され、他端が接地された抵抗と、
一端が前記非反転入力端子に接続され、他端が第一の信号電圧源に接続された第一の容量と、
一端が前記非反転入力端子に接続され、他端が第一の信号電圧源の反転出力に接続された第二の容量と、
一端が前記反転入力端子に接続され、他端が第二の信号電圧源に接続された第三の容量と、
を有するＣＶ変換回路において、
前記第一の信号電圧源と、前記第二の信号電圧源が、時分割的に信号パルスを発生するとともに、前記信号パルスに同期して検波することを特徴とするＣＶ変換回路。 An operational amplifier with an inverting input terminal connected to the output terminal;
A resistor having one end connected to the non-inverting input terminal of the operational amplifier and the other end grounded;
A first capacitor having one end connected to the non-inverting input terminal and the other end connected to a first signal voltage source;
A second capacitor having one end connected to the non-inverting input terminal and the other end connected to the inverting output of the first signal voltage source;
A third capacitor having one end connected to the inverting input terminal and the other end connected to a second signal voltage source;
In the CV conversion circuit having
The CV conversion circuit, wherein the first signal voltage source and the second signal voltage source generate a signal pulse in a time-division manner and detect in synchronization with the signal pulse. 反転入力端子が出力端子に接続された演算増幅器と、
一端が前記演算増幅器の非反転入力端子に接続され、他端が接地された抵抗と、
一端が前記非反転入力端子に接続され、他端が第一の信号電圧源に接続された第一の容量と、
一端が前記反転入力端子に接続され、他端が第二の信号電圧源に接続された第二の容量と、
一端が前記非反転入力端子に接続され、他端が第二の信号電圧源の反転出力に接続された第三の容量と、
を有するＣＶ変換回路において、
前記第一の信号電圧源と、前記第二の信号電圧源が、時分割的に信号パルスを発生するとともに、前記信号パルスに同期して検波することを特徴とするＣＶ変換回路。 An operational amplifier with an inverting input terminal connected to the output terminal;
A resistor having one end connected to the non-inverting input terminal of the operational amplifier and the other end grounded;
A first capacitor having one end connected to the non-inverting input terminal and the other end connected to a first signal voltage source;
A second capacitor having one end connected to the inverting input terminal and the other end connected to a second signal voltage source;
A third capacitor having one end connected to the non-inverting input terminal and the other end connected to the inverting output of the second signal voltage source;
In the CV conversion circuit having
The CV conversion circuit, wherein the first signal voltage source and the second signal voltage source generate a signal pulse in a time-division manner and detect in synchronization with the signal pulse. 反転入力端子が出力端子に接続された演算増幅器と、
一端が前記演算増幅器の非反転入力端子に接続され、他端が接地された抵抗と、
一端が前記非反転入力端子に接続され、他端が第一の信号電圧源に接続された第一の容量と、
一端が前記反転入力端子に接続され、他端が第二の信号電圧源に接続された第二の容量と、
を有するＣＶ変換回路において、
前記第一の信号電圧源と、前記第二の信号電圧源が、時分割的に信号パルスを発生するとともに、前記信号パルスに同期して検波することを特徴とするＣＶ変換回路。 An operational amplifier with an inverting input terminal connected to the output terminal;
A resistor having one end connected to the non-inverting input terminal of the operational amplifier and the other end grounded;
A first capacitor having one end connected to the non-inverting input terminal and the other end connected to a first signal voltage source;
A second capacitor having one end connected to the inverting input terminal and the other end connected to a second signal voltage source;
In the CV conversion circuit having
The CV conversion circuit, wherein the first signal voltage source and the second signal voltage source generate a signal pulse in a time-division manner and detect in synchronization with the signal pulse. 前記信号電圧源が、３つ以上で、かつ、前記信号源に接続する容量が
３つ以上であることを特徴とする請求項１乃至４記載のCV変換回路。 5. The CV conversion circuit according to claim 1, wherein there are three or more signal voltage sources and three or more capacitors connected to the signal sources. 前記反転入力端子に接続される全容量値の和Cと、前記抵抗の値RによるCRの時定数の値が、前記第一及び前期第二の信号電圧源の信号パルス時間よりも、小さいことを特徴とする請求項１乃至５記載のＣＶ変換回路。 The sum C of all capacitance values connected to the inverting input terminal and the value of the CR time constant based on the resistance value R are smaller than the signal pulse time of the first and second signal voltage sources. 6. The CV conversion circuit according to claim 1, wherein: 前記抵抗の値を前記信号電圧源に同期して変更することを特徴とする請求項１乃至６記載のＣＶ変換回路。 7. The CV conversion circuit according to claim 1, wherein a value of the resistor is changed in synchronization with the signal voltage source. 前記信号電圧源の振幅電圧値が異なることを特徴とする請求項１乃至７記載のＣＶ変換回路。 8. The CV conversion circuit according to claim 1, wherein amplitude voltage values of the signal voltage sources are different.
JP2005038180A 2004-05-12 2005-02-15 CV conversion circuit Expired - Fee Related JP4811987B2 (en)

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US11/127,017 US7224193B2 (en) 2004-05-12 2005-05-11 Current-voltage conversion circuit
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