1363875 (1) 九、發明說明 【發明所屬之技術領域】 本發明係關於一電流電壓轉換電路（current-voltage, CV )，以將多個電容値轉換爲相對之電壓。 【先前技術】 圖7顯示一傳統C V轉換電路（範例請參見Jp 2 0 0 1 -1 24807 A，圖 2 )。 在此架構中’ 一傳統CV轉換電路包括具有非反向輸 入端接地之運算放大器1、連接該運算放大器1輸出端與 反向輸入端之電阻器3、與電容値待測之電容器2。該電 容器2之一端接至運算放大器1之反向輸入端，另一端接 至訊號電壓源4»訊號電壓源4之訊號有特定電壓振幅V 與特定角頻率ω。訊號電壓源4之訊號電壓乂5可以方程 式（1 )表示：1363875 (1) Description of the Invention [Technical Field] The present invention relates to a current-voltage (CV) circuit for converting a plurality of capacitors 相对 into opposite voltages. [Prior Art] Fig. 7 shows a conventional C V conversion circuit (for an example, see Jp 2 0 0 1 - 1 24807 A, Fig. 2). In this architecture, a conventional CV conversion circuit includes an operational amplifier having a non-inverting input ground, a resistor 3 connected to the output of the operational amplifier 1 and an inverting input terminal, and a capacitor 2 to be tested. One of the capacitors 2 is terminated to the inverting input of the operational amplifier 1, and the other end is connected to the signal voltage source 4»the signal voltage source 4 has a specific voltage amplitude V and a specific angular frequency ω. The signal voltage 乂5 of the signal voltage source 4 can be expressed by equation (1):
Vs = V · sin ( ωί ) ... ( 1 ) 因爲由於圖7中運算放大器1之反向輸入端實質接地 ，在反向輸入端上之電位等於非反向輸入端之地電位。使 地電位爲〇 V，並將電容器2之電容値以C表示，則流過 電容器2之電流I表示爲方程式（2): I=j gjC · V · sin ( cot ) ... ( 2) 因此在運算放大器1之輸出端5產生一振幅爲V。之 電壓： V 0 = - j ω CR · V · s i η ( ω t ) ... ( 3) -5- (2) 1363875 從方程式（3)中明顯可見’運算放大器1之輸出電 . 壓振幅V。正比於電容器2之電容値c。因此，電容器2 之電容値C可由測量輸出電壓之振幅v。而測出。 圖8A、8B以及8C爲CV轉換電路各相對部分之電壓 與電流’在時間上的波形。圖8A顯示訊號電壓源4之訊 - 號電壓波形。此例中所給的是正弦波。圖8B顯示流過電 • 容器2與電阻器3的電流波形。圖8C顯示出現於運算放 g 大器1輸出端5的電壓波形。 當要量測多個電容器的電容時，就需要與欲量測電容 器一樣數目的如圖7之電路，方得以對多個電容器進行量 測。 傳統之CV轉換電路，有需要與欲量測電容器數目〜 樣數目的CV轉換電路的問題，並且當要量測多個電容器 時電路之規模也因此增大。 φ 【發明內容】 有鑑於上述，本發明旨在解決先前提到的問題，而本 發明之一目的在以一小型電路測量多個電容器。 本發明提供一種CV轉換電路，其中包含：一反向輸 入端與輸出端相接之運算放大器；一電阻器，一端接於該 運算放大器之非反向輸入端.，另一端接地；第一電容器， 一端接於該運算放大器之非反向輸入端，另一端接於第一 訊號電壓源；第二電容器，一端接於該運算放大器之非反 向輸入端，另一端接於該第一訊號電壓源之反向輸出；第 -6- (4) 1363875 . 步之偵測。 . 此外’—種CV轉換電路，其中包含：—反向輸入端 與輸出端相接之運算放大器；一電阻器，一端接於該運算 放大器之非反向輸入端’另一端接地；第一電容器，一端 接於該運算放大器之非反向輸入端，另一端接於第一訊號 - 電壓源，·以及第二電容器，一端接於該運算放大器之反向 • 輸入端’另一端接於第二訊號電壓源，其中該第一訊號電 φ 壓源與該第二訊號電壓源以分時方式產生訊號，並進行與 該等訊號脈衝同步之偵測。 此外，於上述之CV轉換電路中，訊號電壓源之數目 等於或大於三，且分別連接到該等訊號電壓源之電容器之 數目亦等於或大於三。 此外，於該CV轉換電路中，當連接到該運算放大器 反向輸入端之該等電容器之總電容的和爲C，而該電阻器 之電阻値爲R，則時間常數CR之値小於來自該第一與第 φ 二訊號電壓源之各該等訊號脈衝之脈衝長度。 此外，於該CV轉換電路中，該電阻器之電阻隨來自 該等訊號電壓源之驅動電壓同步改變。 此外，於該CV轉換電路中，該等訊號電壓源之振幅 電壓値各不相同。 依本發明之CV轉換電路，提供了可以少數電路量測 多個電容器之電容的效果。 【實施方式】 -8 - (5) 1363875 • 在本發明中，爲解決上述CV轉換電路中的問題，施 加一分時訊號脈衝於多個個別電容値待量測的電容器上。 此外，電阻器之電阻値隨驅動電壓同步改變。 本發明之較佳實施例將參照附圖於以下敘述。 第一實施例. . 圖1爲依照本發明第一實施例之C V轉換電路的電路 φ 圖。該CV轉換電路有第一電容器2A與第二電容器2B。 第一電容器2A與第二電容器2B其中之一爲參考電容器， 另一者爲待測電容器。該CV轉換電路亦有第三電容器3A 與第四電容器3B。相似地，第三電容器3A與第四電容器 3B其中之一爲參考電容器，另一者爲待測電容器。 上述四電容器2A、2B、3A、3B之一端連接於一共同 節點，其接於運算放大器1之非反向輸入端。該運算放大 器1爲一電壓跟隨器，其中輸出端10與反向輸入端相接 φ 。電阻器9之一端接於該運算放大器1之非反向輸入端， 該電阻器9另一端接地。 第一電容器2A另一端接至第一訊號電壓源4。反向 器6之輸入接至該第一訊號電壓源4，該反向器6之輸出 則接至第二電容器2B另一端。亦即，第一電容器2A與第 二電容器2B以相反相位驅動。 第三電容器3A另一端接至第二訊號電壓源5。反向 器7之輸入接至該第一訊號電壓源5，該反向器7之輸出 則接至第四電容器3 B另一端。亦即，第三電容器3 A與第 -9 - (6) 1363875 . 四電容器3 B以相反相位驅動。 . 圖2A至2K爲圖1之CV轉換電路各相對部分之電壓 波形，其中橫軸代表時間。 圖2A顯示作爲第一訊號電壓源4與第二訊號電壓源 5基礎的時脈訊號波形。圖2B顯示對圖2A中時脈訊號除 - 頻所得波形。圖2C顯示來自第一訊號電壓源4之輸出電 . 壓波形。此波形只需將圖2A與2B所示訊號作AND運算 φ 即可產生。圖2D顯示當第一電容器2A與第二電容器2B ，以圖2C所示波形之輸出電壓驅動時，出現在運算放大 器1之輸出端〗〇的波形。 當第一電容器2A之電容爲C2A，而第二電容器2B之 電容爲C2B，由電容C2A減去電容C2B所得之差爲Cx，也 就是差値Cx定義爲CX = C2A-C2B » 圖2D所顯示輸出電壓之波型，決定於差値Cx。因此 ，當差値Cx如圖2D顯示爲正時，圖2C中顯示輸出電壓 φ 的上升緣會產生一向上突波。另一方面，當差値Cx爲負 時，圖2C中顯示輸出電壓的上升緣會產生一與圖2D相反 的向下突波。 若第一訊號電壓源4的訊號振幅與反向器6之電源電 壓的振幅，也就是輸入第二電容器的訊號振幅固定時，圖 2D所顯示突波的高度決定於差値Cx。當差値Cx大時，突 波的高度就大’當差値C x小時，突波的高度就小。 亦即，電流電壓轉換可靠量測突波而完成。 此外’當連接到運算放大器1非反向輸入端之總電容 -10- (7) (7)1363875 爲CT，而電阻器9之電阻爲R，圖2D中突波波形遵照一 時間常數爲CT · R的放電曲線。 此處’當時間常數較圖2C所示輸出電壓之位準保持 在"Η ”的時間週期（驅動脈衝長度）爲長時，運算放大器1 輸出端1 〇的電壓在圖2 C所示輸出電壓之位準從” Η "(高 )降到"L"(低）的時間內，並未達到地電壓，量測因此 產生誤差。職是之故，時間常數CT · R之値須小於當第一 電容器2A與第二電容器2B被第一訊號電壓源4驅動時之 脈衝長度。 圖2E顯示來自圖1中第二訊號電壓源5輸出電壓之 波形。來自第二訊號電壓源5輸出電壓之波形只需將圖 2A所示訊號與圖2B所示訊號局部反向所得訊號作AND 運算即可產生。圖2F顯示當第三電容器3A與第四電容器 3B，以圖2E所示波形之電壓驅動時，出現在運算放大器 1之輸出端〗〇的輸出電壓波形。 當第三電容器3A之電容爲C3A，而第四電容器3B之 電容爲C3B，由電容C3A減去電容C3B所得之差爲Cy，也 就是差値Cy定義爲Cy = C3A-C3B。圖2F所顯示輸出電壓之 波型，決定於差値Cy，類似於圖2C的情形。 圖2G顯示當第一電容器2A與第二電容器2B，以及 第三電容器3A與第四電容器3B分別被第一訊號電壓源4 與第二訊號電壓源5驅動時，出現在運算放大器1輸出 端10的輸出電壓波形。圖2G之波形爲圖2D與2F波形 的和。 -11 - (8) 1363875 • 圖2H至2K顯示用以偵測運算放大器1輸出端丨〇電 . 壓波形的訊號。圖2Η所示訊號與圖2C所示相同，因此只 需將圖2Α與2Β所不訊號作AND運算即可產生。圖21所 示訊號只需將圖2A訊號邏輯反向所得訊號，再與圖2B訊 號作AND運算即可產生。圖2J所示訊號與圖2£相同，Vs = V · sin ( ωί ) (1) Since the inverting input of the operational amplifier 1 in Fig. 7 is substantially grounded, the potential at the inverting input is equal to the ground potential of the non-inverting input. Let the ground potential be 〇V and the capacitance 値 of the capacitor 2 be denoted by C, then the current I flowing through the capacitor 2 is expressed as equation (2): I=j gjC · V · sin ( cot ) ... ( 2) Therefore, an amplitude of V is generated at the output terminal 5 of the operational amplifier 1. Voltage: V 0 = - j ω CR · V · si η ( ω t ) ( 3) -5- (2) 1363875 It is obvious from equation (3) that the output voltage of the operational amplifier 1 is V. It is proportional to the capacitance 値c of the capacitor 2. Therefore, the capacitance 値C of the capacitor 2 can be measured by the amplitude v of the output voltage. And measured. 8A, 8B and 8C are waveforms of voltage and current '''''''''' Figure 8A shows the signal voltage waveform of the signal voltage source 4. In this case, a sine wave is given. Fig. 8B shows the current waveform flowing through the electric container 2 and the resistor 3. Figure 8C shows the voltage waveform appearing at the output 5 of the operational amplifier 1. When measuring the capacitance of multiple capacitors, it is necessary to measure the number of capacitors as shown in Figure 7 to measure multiple capacitors. Conventional CV conversion circuits have problems with the number of CV conversion circuits that are required to measure the number of capacitors, and the scale of the circuit is increased when a plurality of capacitors are to be measured. φ [ SUMMARY OF THE INVENTION In view of the above, the present invention is directed to solving the aforementioned problems, and an object of the present invention is to measure a plurality of capacitors in a small circuit. The present invention provides a CV conversion circuit comprising: an operational amplifier with an inverting input connected to the output; a resistor having one end connected to the non-inverting input of the operational amplifier. The other end is grounded; the first capacitor One end is connected to the non-inverting input end of the operational amplifier, and the other end is connected to the first signal voltage source; the second capacitor is connected at one end to the non-inverting input end of the operational amplifier, and the other end is connected to the first signal voltage. Reverse output of the source; -6- (4) 1363875. Detection of the step. In addition, a CV conversion circuit includes: an operational amplifier connected to the output terminal of the inverting input terminal; a resistor connected to the non-inverting input terminal of the operational amplifier at one end and grounded at the other end; the first capacitor One end is connected to the non-inverting input terminal of the operational amplifier, the other end is connected to the first signal-voltage source, and the second capacitor is connected to the opposite end of the operational amplifier. The other end is connected to the second end. a signal voltage source, wherein the first signal electric φ voltage source and the second signal voltage source generate signals in a time sharing manner, and perform detection in synchronization with the signal pulses. Further, in the above CV conversion circuit, the number of signal voltage sources is equal to or greater than three, and the number of capacitors respectively connected to the signal voltage sources is equal to or greater than three. In addition, in the CV conversion circuit, when the sum of the total capacitances of the capacitors connected to the inverting input terminal of the operational amplifier is C, and the resistance 値 of the resistor is R, the time constant CR is less than The pulse length of each of the first and second φ two-signal voltage sources. Further, in the CV conversion circuit, the resistance of the resistor changes in synchronization with the driving voltage from the signal voltage sources. In addition, in the CV conversion circuit, the amplitude voltages of the signal voltage sources are different. According to the CV conversion circuit of the present invention, the effect of measuring the capacitance of a plurality of capacitors with a small number of circuits is provided. [Embodiment] -8 - (5) 1363875 • In the present invention, in order to solve the above problem in the CV conversion circuit, a minute-time signal pulse is applied to a plurality of capacitors to be measured by a plurality of individual capacitors. In addition, the resistance 値 of the resistor changes synchronously with the driving voltage. Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. First Embodiment Fig. 1 is a circuit diagram of a C V conversion circuit in accordance with a first embodiment of the present invention. The CV conversion circuit has a first capacitor 2A and a second capacitor 2B. One of the first capacitor 2A and the second capacitor 2B is a reference capacitor, and the other is a capacitor to be tested. The CV conversion circuit also has a third capacitor 3A and a fourth capacitor 3B. Similarly, one of the third capacitor 3A and the fourth capacitor 3B is a reference capacitor, and the other is a capacitor to be tested. One of the above-mentioned four capacitors 2A, 2B, 3A, 3B is connected to a common node which is connected to the non-inverting input terminal of the operational amplifier 1. The operational amplifier 1 is a voltage follower in which the output terminal 10 is connected to the inverting input terminal φ . One of the resistors 9 is terminated to the non-inverting input of the operational amplifier 1, and the other end of the resistor 9 is grounded. The other end of the first capacitor 2A is connected to the first signal voltage source 4. The input of the inverter 6 is connected to the first signal voltage source 4, and the output of the inverter 6 is connected to the other end of the second capacitor 2B. That is, the first capacitor 2A and the second capacitor 2B are driven in opposite phases. The other end of the third capacitor 3A is connected to the second signal voltage source 5. The input of the inverter 7 is connected to the first signal voltage source 5, and the output of the inverter 7 is connected to the other end of the fourth capacitor 3B. That is, the third capacitor 3 A is driven in the opposite phase to the -9 - (6) 1363875 . 2A to 2K are voltage waveforms of respective opposite portions of the CV conversion circuit of Fig. 1, in which the horizontal axis represents time. Fig. 2A shows the clock signal waveform which is the basis of the first signal voltage source 4 and the second signal voltage source 5. Fig. 2B shows the waveform obtained by dividing the frequency of the clock signal in Fig. 2A. Figure 2C shows the output voltage from the first signal voltage source 4. This waveform can be generated by simply ANDing φ the signals shown in Figures 2A and 2B. Fig. 2D shows a waveform appearing at the output terminal of the operational amplifier 1 when the first capacitor 2A and the second capacitor 2B are driven by the output voltage of the waveform shown in Fig. 2C. When the capacitance of the first capacitor 2A is C2A and the capacitance of the second capacitor 2B is C2B, the difference obtained by subtracting the capacitance C2B from the capacitor C2A is Cx, that is, the difference Cx is defined as CX = C2A-C2B » as shown in FIG. 2D The waveform of the output voltage is determined by the difference Cx. Therefore, when the difference Cx is shown as positive in Fig. 2D, the rising edge of the output voltage φ is shown in Fig. 2C to generate an upward glitch. On the other hand, when the difference Cx is negative, the rising edge of the output voltage shown in Fig. 2C produces a downward glitch opposite to that of Fig. 2D. If the amplitude of the signal of the first signal voltage source 4 and the amplitude of the power supply voltage of the inverter 6, that is, the amplitude of the signal input to the second capacitor, are fixed, the height of the glitch shown in Fig. 2D is determined by the difference Cx. When the difference Cx is large, the height of the glitch is large. When the difference C x is small, the height of the glitch is small. That is, the current-voltage conversion is reliably performed by measuring the glitch. In addition, when the total capacitance of the non-inverting input terminal of the operational amplifier 1 is -10- (7) (7) 1363875 is CT, and the resistance of the resistor 9 is R, the glitch waveform in Fig. 2D follows a time constant of CT. · The discharge curve of R. Here, when the time constant is longer than the level of the output voltage shown in Figure 2C at the time of "Η" (the drive pulse length) is long, the voltage at the output of the operational amplifier 1 is 1 在 at the output shown in Figure 2C. The voltage level has not reached the ground voltage from " Η " (high) to "L" (low), and the measurement has produced errors. For the sake of the job, the time constant CT · R must be less than the pulse length when the first capacitor 2A and the second capacitor 2B are driven by the first signal voltage source 4. Figure 2E shows the waveform from the output voltage of the second signal voltage source 5 of Figure 1. The waveform of the output voltage from the second signal voltage source 5 can be generated by performing an AND operation on the signal obtained by partially inverting the signal shown in FIG. 2A and the signal shown in FIG. 2B. Fig. 2F shows an output voltage waveform appearing at the output terminal of the operational amplifier 1 when the third capacitor 3A and the fourth capacitor 3B are driven by the voltage of the waveform shown in Fig. 2E. When the capacitance of the third capacitor 3A is C3A and the capacitance of the fourth capacitor 3B is C3B, the difference obtained by subtracting the capacitance C3B from the capacitor C3A is Cy, that is, the difference Cy is defined as Cy = C3A - C3B. The waveform of the output voltage shown in Fig. 2F is determined by the difference Cy, similar to the case of Fig. 2C. 2G shows that when the first capacitor 2A and the second capacitor 2B, and the third capacitor 3A and the fourth capacitor 3B are respectively driven by the first signal voltage source 4 and the second signal voltage source 5, they appear at the output terminal 10 of the operational amplifier 1. Output voltage waveform. The waveform of Fig. 2G is the sum of the waveforms of Figs. 2D and 2F. -11 - (8) 1363875 • Figures 2H to 2K show the signals used to detect the output voltage of the op amp 1 output. The signal shown in Fig. 2A is the same as that shown in Fig. 2C, so that it is only necessary to perform an AND operation on the signals of Fig. 2 and Fig. 2 to generate an AND operation. The signal shown in Fig. 21 only needs to logically invert the signal obtained by the signal of Fig. 2A, and then generate an AND operation with the signal of Fig. 2B. The signal shown in Figure 2J is the same as Figure 2,
- 只需將圖2A訊號與圖2B訊號邏輯反向所得訊號作AND- Just reverse the signal obtained by logically inverting the signal of Figure 2A and Figure 2B.
- 運算即可產生。圖2K所示訊號，只需將圖2A訊號邏輯 φ 反向所得訊號’與圖2B訊號邏輯反向所得訊號，作AND 運算即可產生。 圖3顯示同步偵測電路之一例。同步偵測電路包含開 關S1至S4。開關對S1及S3，與開關對S2及S4，以互 補方式關上（ON )或打開（OFF )。也就是，當開關S1 開到ON，開關S3就開到OFF。而當開關S2開到OFF， 開關S4就開到ON。 運算放大器1輸出端1 〇接到圖3所示同步偵測電路 籲之輸入端IN。 圖3所示同步偵測電路的數目，必須與待偵測的電容 器數目相同。 .爲測量第一電容器2A電容與第二電容器2B電容之間 的電容差Cx，當圖2H所示訊號位準是在”H”時，開關S2 與S3開到ON (開關S1與S4開到OFF )，而當圖21所 示訊號是在"Ηπ時’開關S1與S4開到ON (開關S2與S3 開到0 F F )。 結果，即可偵測由第一電容器2A與第二電容器2B之 -12- (9) 1363875 . 間電容差Cx所產生的運算放大器1的輸出訊號β _ 爲利用另一同步偵測電路測量第三電容器3 Α電容與 第四電容器3B電容之間的電容差Cy，當圖所示訊號 之位準是在"H"時，開關S2與S3開到on (開關S1與 S 4開到〇 F F )。而當圖2 K所示訊號位準是在》η ’’時，開 - 關S1與S4開到ON (開關S2與S3開到OFF)。 . 以這種方式，即可偵測由第三電容器3 A與第四電容 φ 器3B之間電容差Cy所產生的運算放大器1的輸出訊號。 在同步偵測之後，圖3所示之〇 U T端之輸出訊號若 有需要可經過一低通濾波器，亦可在有需要時經過放大， 藉以使電流電壓轉換成爲可能。 結果，兩個電容可以用一個運算放大器與一個電阻器 量得。 注意在以上的敘述中，爲簡單起見，描述爲第一電容 器2A的電容或第二電容器2B的電容其中之一爲參考電容 φ ，另一者爲待測電容，且相似地，第三電容器3 A的電容 與第四電容器3B的電容其中之一爲參考電容，另一者爲 待測電容。然而，很明顯地，此電路原理上是一偵測第一 . 電容器2A電容與第二電容器2B電容之間的電容差，或第 三電容器3A電容與第四電容器3B電容之間的電容差的電 路’因此電容其中之一不一定是參考。 此外，雖然在以上解釋中，顯示了可以偵測一對電容 器之間的電容差値。很明顯地，即使兩電容器其中之一不 存在’亦即，兩電容其中之一爲零，剩下的電容仍可以以 -13- 1363875 do) . 電容差的形式測出。 第二實施例 圖4爲依照本發明第二實施例之CV轉換電路的電路 圖。與圖1所示CV轉換電路架構差異的一個重點是第五 電容器12A與第六電容器12B之一端接至第一訊號電壓源 . 4。反向器6之輸入接至運算放大器1非反向輸入端，第 φ 五電容器12的另一端則接至第三訊號電壓源14。此外， 反向器16之輸入接至該第三訊號電壓源14，該反向器16 的輸出則接至第六電容器12B另一端。亦即，第五電容器 12A與第六電容器12B是以相反相位驅動。除此以外，第 —訊號電壓源4、第二訊號電壓源5、與第三訊號電壓源 14是以分時方式產生訊號脈衝。其他重點與圖1所示之 CV轉換電路相同。 圖5A至5P爲圖4所示CV轉換電路各相對部分之電 φ 壓，於時間橫軸上的波形。 圖5A顯示作爲第一訊號電壓源4、第二訊號電壓源5 、與第三訊號電壓源14基礎的時脈訊號波形。圖5B顯示 來自圖4所示，第一訊號電壓源4之輸出電壓脈衝訊號的 波形。圖5C顯示當第一電容器2A與第二電容器2B，以 圖5B所示波形之輸出電壓驅動時，出現在運算放大器1 輸出端10的電壓波形。 圖5D顯示來自圖4所示，第二訊號電壓源5之輸出 電壓脈衝訊號的波形。圖5 E顯示當第三電容器3 A與第四 14- (11) (11)1363875 電容器3B，以圖5D所示之輸出電壓脈衝驅動時，出現在 運算放大器1輸出端】〇的電壓波形。 圖5F顯示來自圖4所示，第三訊號電壓源14之輸出 電壓脈衝訊號的波形。圖5 G顯示當第五電容器1 2 A與第 六電容器〗2B，以圖5F所示之輸出電壓信號脈衝驅動時 ，出現在運算放大器1.輸出端1 〇的電壓波形。 圖5H顯示當第一電容器2A與第二電容器2B’第三 電容器3A與第四電容器3B，以及第五電容器12A與第六 電容器12B，分別被第一訊號電壓源4，第二訊號電壓源 5，與第三訊號電壓源14驅動時，出現在運算放大器1輸 出端10的電壓波形。出現在運算放大器1輸出端10的電 壓爲圖5C，5E與5G所示電壓的和。 圖5J至5P顯示用以偵測運算放大器1輸出端10電 壓波形的訊號波形。如此，圖5 J至5 Μ與第一實施例相似 〇 在利用同步偵測電路測量第五電容器1 2 Α電容與第六 電容器12B電容之間的電容差（：2的情形中，當圖50所示 訊號的位準是在"H"時，圖3的開關S2與S3開到ON ( 開關S1與S4開到OFF)。而當圖5P所示訊號的位準是 在"H”時，開關S1與S4開到ON (開關S2與S3開到 OFF )。 以此方式，即可偵測由第五電容器12A與第六電容器 12B之間電容差Cz所產生的運算放大器1的輸出。 結果，三個電容可以用一個運算放大器與一個電阻器 -15- (12) 1363875 , 量得。 從以上解釋可見，很明顯地，三個或更多電容可以靠- The operation can be generated. The signal shown in Fig. 2K can be generated by performing an AND operation only by reversing the signal obtained by inverting the signal φ of the signal φ of Fig. 2A and the signal of Fig. 2B. Figure 3 shows an example of a synchronous detection circuit. The sync detection circuit includes switches S1 to S4. The switch pairs S1 and S3, and the switch pairs S2 and S4 are turned ON (ON) or OFF (OFF) in a complementary manner. That is, when the switch S1 is turned ON, the switch S3 is turned OFF. When switch S2 is turned OFF, switch S4 is turned ON. The output terminal 1 of the operational amplifier 1 is connected to the input terminal IN of the synchronous detection circuit shown in FIG. The number of synchronization detection circuits shown in Figure 3 must be the same as the number of capacitors to be detected. In order to measure the capacitance difference Cx between the capacitance of the first capacitor 2A and the capacitance of the second capacitor 2B, when the signal level shown in FIG. 2H is at "H", the switches S2 and S3 are turned ON (the switches S1 and S4 are opened to OFF), and when the signal shown in Fig. 21 is at "Ηπ, the switches S1 and S4 are turned ON (switches S2 and S3 are turned to 0 FF). As a result, the output signal β _ of the operational amplifier 1 generated by the first capacitor 2A and the second capacitor 2B -12-(9) 1363875. The capacitance difference Cx is detected by using another synchronization detecting circuit. The capacitance difference Cy between the three capacitor 3 tantalum capacitor and the fourth capacitor 3B capacitor. When the level of the signal shown in the figure is at "H", the switches S2 and S3 are turned on (switches S1 and S4 are turned on) FF). When the signal level shown in Fig. 2K is at "η", the on-off S1 and S4 are turned ON (switches S2 and S3 are turned OFF). In this way, the output signal of the operational amplifier 1 generated by the capacitance difference Cy between the third capacitor 3 A and the fourth capacitor φ 3B can be detected. After the synchronous detection, the output signal of the UT terminal shown in FIG. 3 can pass through a low-pass filter if necessary, and can be amplified when necessary, thereby making current-voltage conversion possible. As a result, the two capacitors can be measured with one operational amplifier and one resistor. Note that in the above description, for the sake of simplicity, one of the capacitances described as the capacitance of the first capacitor 2A or the second capacitor 2B is the reference capacitance φ, the other is the capacitance to be tested, and similarly, the third capacitor One of the capacitance of 3 A and the capacitance of the fourth capacitor 3B is a reference capacitance, and the other is a capacitance to be measured. However, it is obvious that the circuit is in principle a first difference between the capacitance of the capacitor 2A and the capacitance of the second capacitor 2B, or the difference between the capacitance of the third capacitor 3A and the capacitance of the fourth capacitor 3B. The circuit 'so one of the capacitors is not necessarily a reference. Further, although in the above explanation, it is shown that the capacitance difference 一对 between a pair of capacitors can be detected. Obviously, even if one of the two capacitors does not exist 'that is, one of the two capacitors is zero, the remaining capacitance can still be measured in the form of a capacitance difference of -13 - 1363875 do). SECOND EMBODIMENT Fig. 4 is a circuit diagram of a CV conversion circuit in accordance with a second embodiment of the present invention. One important difference from the CV conversion circuit architecture shown in Fig. 1 is that one of the fifth capacitor 12A and the sixth capacitor 12B is terminated to the first signal voltage source. The input of the inverter 6 is connected to the non-inverting input terminal of the operational amplifier 1, and the other end of the fifth φ capacitor 12 is connected to the third signal voltage source 14. In addition, the input of the inverter 16 is connected to the third signal voltage source 14, and the output of the inverter 16 is connected to the other end of the sixth capacitor 12B. That is, the fifth capacitor 12A and the sixth capacitor 12B are driven in opposite phases. In addition, the first signal voltage source 4, the second signal voltage source 5, and the third signal voltage source 14 generate signal pulses in a time sharing manner. The other points are the same as the CV conversion circuit shown in Figure 1. Figs. 5A to 5P are waveforms of electric φ pressures of respective opposite portions of the CV conversion circuit shown in Fig. 4 on the horizontal axis of time. FIG. 5A shows a clock signal waveform which is the basis of the first signal voltage source 4, the second signal voltage source 5, and the third signal voltage source 14. Fig. 5B shows the waveform of the output voltage pulse signal from the first signal voltage source 4 shown in Fig. 4. Fig. 5C shows the voltage waveform appearing at the output terminal 10 of the operational amplifier 1 when the first capacitor 2A and the second capacitor 2B are driven by the output voltage of the waveform shown in Fig. 5B. Figure 5D shows the waveform of the output voltage pulse signal from the second signal voltage source 5 shown in Figure 4. Fig. 5E shows the voltage waveform appearing at the output terminal of the operational amplifier 1 when the third capacitor 3 A and the fourth 14-(11) (11) 1363875 capacitor 3B are driven by the output voltage pulse shown in Fig. 5D. Figure 5F shows the waveform of the output voltage pulse signal from the third signal voltage source 14 shown in Figure 4. Fig. 5G shows the voltage waveform appearing at the output terminal 1 of the operational amplifier 1. When the fifth capacitor 1 2 A and the sixth capacitor 〖2B are driven by the output voltage signal pulse shown in Fig. 5F. 5H shows the first capacitor 2A and the second capacitor 3B', the third capacitor 3A and the fourth capacitor 3B, and the fifth capacitor 12A and the sixth capacitor 12B, respectively, being the first signal voltage source 4 and the second signal voltage source 5, respectively. When the third signal voltage source 14 is driven, the voltage waveform appears at the output terminal 10 of the operational amplifier 1. The voltage appearing at the output terminal 10 of the operational amplifier 1 is the sum of the voltages shown in Figures 5C, 5E and 5G. Figures 5J through 5P show signal waveforms for detecting the voltage waveform at the output 10 of the operational amplifier 1. Thus, FIG. 5 to FIG. 5 are similar to the first embodiment, and in the case of measuring the capacitance difference between the fifth capacitor 1 2 tantalum capacitor and the sixth capacitor 12B capacitance by using the synchronization detecting circuit (in the case of 2, FIG. 50) The level of the signal shown is at "H", the switches S2 and S3 of Figure 3 are turned ON (switches S1 and S4 are turned OFF), and the level of the signal shown in Figure 5P is at "H" When the switches S1 and S4 are turned ON (the switches S2 and S3 are turned OFF). In this way, the output of the operational amplifier 1 generated by the capacitance difference Cz between the fifth capacitor 12A and the sixth capacitor 12B can be detected. As a result, the three capacitors can be measured with an operational amplifier and a resistor -15-(12) 1363875. As can be seen from the above explanation, it is obvious that three or more capacitors can be used.
V 著將分別電容待測的電容器，以分時方式驅動，而利用一 個運算放大器與一個電阻器量得。 - 第三實施例 . 圖6爲依照本發明第三實施例之CV轉換電路的電路 g 圖。與圖1所示CV轉換電路架構差異的一個重點是電阻 器9換爲兩個電阻器9A與9B，開關21與電阻器9B並聯 ，及開關21是依照邏輯電路2 0的輸出訊號控制，以接收 第一訊號電壓源4與第二訊號電壓源5的輸出電壓訊號作 爲輸入電壓訊號。（邏輯電路20的輸入不一定要是來自 第一訊號電壓源4的輸出電壓訊號與來自第二訊號電壓源 5的輸出電壓訊號本身，只須與來自第一訊號電壓源4的 輸出電壓訊號或來自第二訊號電壓源5的輸出電壓訊號同 φ 步即可。） 使CT爲在非反向輸入端之總電容，R9A爲電阻器9A 之電阻値，而R9B爲電阻器9B之電阻値，則當開關21是 ON時，在偵測電容期間的突波以時間常數CT · R9A的速 率放電；而當開關2 1是OFF時，在偵測電容期間的突波 以時間常數Cf* (R9A + R9B)的速率放電。 假設第一電容器2A與第二電容器2B的電容差（^大 ，則當第一電容器2A與第二電容器2B被第一訊號電壓源 4與反向器6驅動時，圖2D所示突波的峰壓也變大。另 -16- (13) 1363875 , —方面，若第三電容器3A與第四電容器3B的電容差cy ， 小’則當第三電容器3 A與第四電容器3 b被第二訊號電壓 源5與反向器7驅動時，圖2 D所示突波的峰壓也變小^ 在這種情形’有一個問題產生：當連接於非反向輸入端與 地電位之間的電阻器電阻較大時，圖2 D所示輸出電壓波 - 形失真；而當電阻器的電阻値較小時，圖2F所示電壓波 . 形幾乎無法得到（被雜訊遮蔽）。 P 然而，靠著當圖2B所顯示的訊號位準爲”H"時，將開 關2 1開到ON ’此時電容差値大，讓連接於非反向輸入端 與地電位之間的電阻器電阻値小於r9A，而當電容差値小 時，讓連接於非反向輸入端與地電位之間的電阻器電阻値 大於R9A + R9B，仍可得到令人滿意的電流電壓轉換。 改變電容器驅動的電壓大小會導致CV轉換敏感度的 改變。在同步偵測後對輸出電壓濾波，輸出訊號的放大量 則依照電容器驅動所需電壓大小而改變，即可得到C V轉 Φ 換之後的輸出訊號。 如上所述，在第一至第三實施例中，運算放大器1非 反向輸入端接地至0V。然而，運算放大器1非反向輸入 端並不一定要接地至0V。因此，若設定運算放大器1非 反向輸入端爲一任意電壓，運算放大器1的輸出電壓即相 對該任意電壓產生。 除此之外，第一電容器2A與第二電容器2B其中之一 電容，第三電容器3A與第四電容器3B其中之一電容，以 及第五電容器12A與第六電容器12B其中之一電容，不必 -17- (15) (15)1363875 2 A :第一電容器 2B :第二電容器 3A :第三電容器 3B :第四電容器 4 :第一訊號電壓源 5 :第二訊號電壓源 6 :反向器 7 :反向器 9 :電阻器 9A :電阻器 9B :電阻器 10 :輸出端 12A :第五電容器 1 2B :第六電容器 14:第三訊號電壓源 20 :邏輯電路 2 1 :開關 S 1 :開關 S2 :開關 S 3 :開關 S 4 :開關V is the capacitor to be tested separately, driven in a time-sharing manner, and is measured by an operational amplifier and a resistor. - Third Embodiment Fig. 6 is a circuit diagram of a CV conversion circuit in accordance with a third embodiment of the present invention. One key difference from the CV conversion circuit architecture shown in FIG. 1 is that the resistor 9 is replaced by two resistors 9A and 9B, the switch 21 is connected in parallel with the resistor 9B, and the switch 21 is controlled according to the output signal of the logic circuit 20, The output voltage signals of the first signal voltage source 4 and the second signal voltage source 5 are received as input voltage signals. (The input of the logic circuit 20 does not have to be the output voltage signal from the first signal voltage source 4 and the output voltage signal itself from the second signal voltage source 5, only with the output voltage signal from the first signal voltage source 4 or from The output voltage signal of the second signal voltage source 5 can be the same as the φ step.) Let CT be the total capacitance at the non-inverting input terminal, R9A is the resistance 电阻 of the resistor 9A, and R9B is the resistance 电阻 of the resistor 9B. When the switch 21 is ON, the glitch during the detection of the capacitance is discharged at the rate of the time constant CT · R9A; and when the switch 2 1 is OFF, the glitch during the detection of the capacitance is time constant Cf* (R9A + The rate of R9B) is discharged. Assuming that the capacitance difference between the first capacitor 2A and the second capacitor 2B is large, when the first capacitor 2A and the second capacitor 2B are driven by the first signal voltage source 4 and the inverter 6, the glitch shown in FIG. 2D The peak pressure also becomes larger. Another -16-(13) 1363875, in the case, if the capacitance difference cy of the third capacitor 3A and the fourth capacitor 3B is small, then the third capacitor 3 A and the fourth capacitor 3 b are When the two-signal voltage source 5 and the inverter 7 are driven, the peak voltage of the glitch shown in Fig. 2D also becomes smaller. ^ In this case, there is a problem: when connected between the non-inverting input terminal and the ground potential When the resistance of the resistor is large, the output voltage wave-shaped distortion shown in Fig. 2D; and when the resistance 値 of the resistor is small, the voltage wave shape shown in Fig. 2F is almost impossible (obscured by noise). However, when the signal level shown in Figure 2B is "H", turn the switch 2 1 to ON ' at this time, the capacitance difference is large, and the resistor connected between the non-inverting input terminal and the ground potential is connected. The resistance 値 is less than r9A, and when the capacitance difference is small, let the resistor resistance connected between the non-inverting input and the ground potential値More than R9A + R9B, satisfactory current-to-voltage conversion can still be obtained. Changing the voltage of the capacitor drive will result in a change in CV conversion sensitivity. After the synchronous detection, the output voltage is filtered, and the amplification of the output signal is driven by the capacitor. The output voltage after the change of the required voltage is obtained, and the output signal after the CV conversion is obtained. As described above, in the first to third embodiments, the non-inverting input terminal of the operational amplifier 1 is grounded to 0 V. However, the operational amplifier 1 The non-inverting input does not have to be grounded to 0 V. Therefore, if the non-inverting input of the operational amplifier 1 is set to an arbitrary voltage, the output voltage of the operational amplifier 1 is generated with respect to the arbitrary voltage. One of the capacitor 2A and the second capacitor 2B, one of the third capacitor 3A and the fourth capacitor 3B, and one of the fifth capacitor 12A and the sixth capacitor 12B, not necessarily -17-(15) (15 1363875 2 A : First capacitor 2B : Second capacitor 3A : Third capacitor 3B : Fourth capacitor 4 : First signal voltage source 5 : Second signal voltage source 6 : Inverter 7 : Transmitter 9: Resistor 9A: Resistor 9B: Resistor 10: Output terminal 12A: Fifth capacitor 1 2B: Sixth capacitor 14: Third signal voltage source 20: Logic circuit 2 1 : Switch S 1 : Switch S2: Switch S 3 : Switch S 4 : Switch