JP2005340245A - Semiconductor device and mounting substrate - Google Patents

Semiconductor device and mounting substrate Download PDF

Info

Publication number
JP2005340245A
JP2005340245A JP2004153041A JP2004153041A JP2005340245A JP 2005340245 A JP2005340245 A JP 2005340245A JP 2004153041 A JP2004153041 A JP 2004153041A JP 2004153041 A JP2004153041 A JP 2004153041A JP 2005340245 A JP2005340245 A JP 2005340245A
Authority
JP
Japan
Prior art keywords
semiconductor device
lead
substrate
exposed
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004153041A
Other languages
Japanese (ja)
Inventor
Hideki Ishii
秀基 石井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2004153041A priority Critical patent/JP2005340245A/en
Publication of JP2005340245A publication Critical patent/JP2005340245A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13021—Disposition the bump connector being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10157—Shape being other than a cuboid at the active surface

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can provide higher capacity and realizes reduction in size and thickness and also provide a mounting substrate thereof. <P>SOLUTION: In a resin-sealing type semiconductor device using leads for external connection, a single surface of lead is covered with resin, a part of the opposite surface of the lead is exposed, and the exposed lead is recessed in comparison with the other part of the opposite surface of the semiconductor device. This semiconductor device is provided on a substrate with the part where the lead is exposed is placed in the upper side and the part where the lead is exposed is electrically connected with the substrate with a wire. Or, the semiconductor device is provided on the substrate with the part where the lead is exposed is placed in the lower side and the part where the lead is exposed is electrically connected with the substrate using solder. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、外部接続用のリードを用いた樹脂封止型の半導体装置及び実装基板に関するものである。   The present invention relates to a resin-encapsulated semiconductor device using a lead for external connection and a mounting substrate.

電子機器の高機能化に伴い、それに使用される半導体装置も小型化、高機能化が必要となってきている。   As electronic devices become more sophisticated, semiconductor devices used for them are also required to be smaller and more functional.

この高機能化の手段として、複数のチップを１つのパッケージに収納し、リードで基板に接続するシステムインパッケージがある。この従来の半導体装置の断面図を図８（ａ）に、上面図を図８（ｂ）に示す。   As a means for increasing the functionality, there is a system-in-package in which a plurality of chips are housed in one package and connected to a substrate with leads. A sectional view of this conventional semiconductor device is shown in FIG. 8A, and a top view thereof is shown in FIG. 8B.

図８に示すように、ダイパッド８１の表面にチップ８２が接着され、裏面にチップ８３が接着されている。そして、チップ８２，８３とリード８４がそれぞれワイヤ８５、８６により電気的に接続されている。これら全体が樹脂８７で封止されている。そして、リード８４と基板８８が実装ランド８９を介して接続されている。   As shown in FIG. 8, the chip 82 is bonded to the front surface of the die pad 81, and the chip 83 is bonded to the back surface. The chips 82 and 83 and the leads 84 are electrically connected by wires 85 and 86, respectively. All of these are sealed with a resin 87. The lead 84 and the substrate 88 are connected via the mounting land 89.

また、基板上に複数のチップを積載し基板下面に半田ボールを取り付けたシステムインパッケージがある（例えば、特許文献１参照）。この従来の半導体装置の断面図を図９に示す。   In addition, there is a system-in-package in which a plurality of chips are stacked on a substrate and solder balls are attached to the lower surface of the substrate (for example, see Patent Document 1). A cross-sectional view of this conventional semiconductor device is shown in FIG.

図９に示すように、ダイパッド９１上にチップ９２と９３が順番に積載されている。そして、チップ９２，９３とダイパッド９１がそれぞれワイヤ９４，９５により電気的に接続されている。これら全体が樹脂９６で封止されている。そして、ダイパッド９１の下面と基板９８が半田ボール９９を介して接続されている。   As shown in FIG. 9, chips 92 and 93 are sequentially stacked on the die pad 91. The chips 92 and 93 and the die pad 91 are electrically connected by wires 94 and 95, respectively. All of these are sealed with a resin 96. The lower surface of the die pad 91 and the substrate 98 are connected via solder balls 99.

特開２００２−２３１８８０号公報JP 2002-231880 A

図８に示す従来の半導体装置では、大容量化するための多ピン化に伴いリードピッチが狭くなると実装が困難であった。逆に、実装を容易にするためリードピッチを広くすると、パッケージサイズが大きくなり小型化できないという問題があった。   The conventional semiconductor device shown in FIG. 8 is difficult to mount when the lead pitch becomes narrow as the number of pins increases to increase the capacity. On the other hand, if the lead pitch is increased to facilitate mounting, there is a problem that the package size becomes large and cannot be reduced.

図９に示す従来の半導体装置では、基板下面に取り付けた半田ボールによって基板との接続を行うためパッケージ高さが高くなるという問題があった。そして、基板との接続に基板下面に取り付けた半田ボールを使用するため、パッケージを積層実装できないため複数個のパッケージが必要な場合、実装面積が大きくなるという問題があった。   The conventional semiconductor device shown in FIG. 9 has a problem that the package height is increased because the solder ball attached to the lower surface of the substrate is connected to the substrate. In addition, since solder balls attached to the lower surface of the substrate are used for connection to the substrate, the packages cannot be stacked and mounted, so that when a plurality of packages are required, there is a problem that the mounting area increases.

本発明は、上述のような課題を解決するためになされたもので、その目的は、大容量化、小型化及び薄型化を図ることができる半導体装置及び実装基板を得るものである。   The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a semiconductor device and a mounting substrate that can be increased in capacity, size, and thickness.

本発明に係る半導体装置は、外部接続用のリードを用いた樹脂封止型の半導体装置であって、リードの片面は樹脂により覆われ、リードの逆面の一部は露出し、リードの露出した部分は、半導体装置の逆面の他の部分と比べて窪んでいる。本発明のその他の特徴は以下に明らかにする。   The semiconductor device according to the present invention is a resin-encapsulated semiconductor device using a lead for external connection, wherein one side of the lead is covered with resin, and a part of the opposite side of the lead is exposed, and the lead is exposed. Such a portion is recessed as compared with other portions on the opposite surface of the semiconductor device. Other features of the present invention will become apparent below.

本発明により、大容量化、小型化及び薄型化を図ることができる。   According to the present invention, the capacity, the size, and the thickness can be reduced.

実施の形態１．
図１は、本発明の実施の形態１に係る半導体装置の断面図（ａ）及び上面図（ｂ）である。 Embodiment 1 FIG.
FIG. 1 is a cross-sectional view (a) and a top view (b) of a semiconductor device according to the first embodiment of the present invention.

図１（ａ）に示すように、ダイパッド１１の片面に、メモリＩＣ等のチップ１２が取り付けられている。そして、チップ１２とリード１３がワイヤ１４により電気的に接続されている。さらに、これら全体が樹脂１５で封止されている。また、図１（ｂ）に示すように、リード１３は、半導体装置の対向する２辺に沿って複数個並べて設けられている。このように、図１に示す半導体装置は、外部接続用のリードを用いた樹脂封止型の半導体装置である。   As shown in FIG. 1A, a chip 12 such as a memory IC is attached to one side of a die pad 11. The chip 12 and the lead 13 are electrically connected by a wire 14. Further, these are entirely sealed with a resin 15. As shown in FIG. 1B, a plurality of leads 13 are provided side by side along two opposing sides of the semiconductor device. As described above, the semiconductor device shown in FIG. 1 is a resin-encapsulated semiconductor device using a lead for external connection.

ここで、リード１３の片面（図１（ａ）では上面）は樹脂１５により覆われている。これにより、リード１３の強度を確保することができる。一方、リード１３の逆面（図１（ａ）では下面）の一部は露出している。このリード１３の露出した部分は、半導体装置の逆面の他の部分と比べて窪んでいる。   Here, one surface (the upper surface in FIG. 1A) of the lead 13 is covered with the resin 15. Thereby, the strength of the lead 13 can be ensured. On the other hand, a part of the reverse surface of the lead 13 (the lower surface in FIG. 1A) is exposed. The exposed portion of the lead 13 is recessed as compared with other portions on the opposite surface of the semiconductor device.

更に詳細に説明すると、リード１３は、半導体素子全体よりも薄い平行平板であり、厚み方向において半導体装置の中央寄りに存在する。そして、半導体装置の逆面は、リード１３が露出した部分以外は樹脂により覆われている。そのため、半導体装置の逆面（図１（ａ）では下面）とリード１３の逆面（図１（ａ）では下面）との差により、段差が形成されている。   More specifically, the lead 13 is a parallel flat plate that is thinner than the entire semiconductor element, and exists near the center of the semiconductor device in the thickness direction. The reverse surface of the semiconductor device is covered with resin except for the portion where the lead 13 is exposed. Therefore, a step is formed by the difference between the reverse surface of the semiconductor device (the lower surface in FIG. 1A) and the reverse surface of the lead 13 (the lower surface in FIG. 1A).

図２は、図１に示す半導体装置を実装した実装基板を示す断面図（ａ）及び上面図（ｂ）である。   2 is a cross-sectional view (a) and a top view (b) showing a mounting board on which the semiconductor device shown in FIG. 1 is mounted.

基板１６上に、図１に示す半導体装置１７がリード１３の露出した部分を上にして実装されている。そして、基板１６に設けられたボンディングパッド１８とリード１３が、金線等のワイヤ１９により電気的に接続されている。さらに、ワイヤ１９周辺が樹脂２０で覆われている。   A semiconductor device 17 shown in FIG. 1 is mounted on the substrate 16 with the exposed portions of the leads 13 facing upward. The bonding pad 18 provided on the substrate 16 and the lead 13 are electrically connected by a wire 19 such as a gold wire. Further, the periphery of the wire 19 is covered with the resin 20.

上記の半導体装置ならば、大容量化及び小型化に伴いリードピッチが狭くなっても、リード１３の露出した部分と基板１６をワイヤ１９で接続することができる。従って、大容量化及び小型化を図ることができる   In the case of the semiconductor device described above, the exposed portion of the lead 13 and the substrate 16 can be connected by the wire 19 even if the lead pitch becomes narrow as the capacity and size are reduced. Accordingly, it is possible to increase the capacity and reduce the size.

また、リード１３の露出した部分と基板１６とを接続するワイヤ１９のループ高さをリード１３の逆面（図２（ａ）では上面）と半導体装置１７の逆面（図２（ａ）では上面）の差だけ削減できるため、薄型化を図ることができる。   Further, the loop height of the wire 19 connecting the exposed portion of the lead 13 and the substrate 16 is set so that the reverse surface of the lead 13 (upper surface in FIG. 2A) and the reverse surface of the semiconductor device 17 (in FIG. 2A). Since only the difference in the upper surface can be reduced, the thickness can be reduced.

なお、上記の例では、半導体装置が１つのチップを内部に有する場合について説明したが、これに限らず、積層された２以上のチップ内部に有するようにしてもよい。これにより、半導体装置の高機能化が図れる。また、チップを立体的に取り付けるため、パッケージサイズを小さくすることができる。   In the above example, the case where the semiconductor device includes one chip is described. However, the present invention is not limited thereto, and the semiconductor device may be included in two or more stacked chips. As a result, higher functionality of the semiconductor device can be achieved. Further, since the chip is three-dimensionally attached, the package size can be reduced.

実施の形態２．
図３は、本発明の実施の形態２に係る半導体装置の断面図である。図１と同じ構成要素には同じ番号を付し、説明を省略する。 Embodiment 2. FIG.
FIG. 3 is a cross-sectional view of the semiconductor device according to the second embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted.

この半導体装置では、ダイパッド１１の裏面にもメモリＩＣ等のチップ２１が取り付けられている。例えば、チップ１２としてＳＲＡＭ、チップ２１としてＦｌａｓｈが用いられる。そして、チップ２１とリード１３がワイヤ２２により電気的に接続されている。なお、図３では、ダイパッドの両面に１つのチップを取り付けているが、これに限らず、ダイパッドの両面に２以上のチップを実装してもよい。その他の構成は実施の形態１と同様である。   In this semiconductor device, a chip 21 such as a memory IC is also attached to the back surface of the die pad 11. For example, SRAM is used as the chip 12 and Flash is used as the chip 21. The chip 21 and the lead 13 are electrically connected by a wire 22. In FIG. 3, one chip is attached to both sides of the die pad. However, the present invention is not limited to this, and two or more chips may be mounted on both sides of the die pad. Other configurations are the same as those of the first embodiment.

また、この実施の形態２に係る半導体装置は、実施の形態１と同様にワイヤを用いて基板上に実装することができる。   Further, the semiconductor device according to the second embodiment can be mounted on a substrate using a wire as in the first embodiment.

上記の実施の形態２に係る半導体装置は、実施の形態１と同様の効果を奏する。そして、ダイパッドの片面だけでなく、両面にチップを積層することで、チップ組み合わせの自由度が向上する。さらに、ダイパッドの両面にチップを実装しているため、チップが同サイズの場合でも、ワイヤ接続のためにスペーサ等を用いてチップ間隙を確保する必要がなく、パッケージを薄型化を図れると共にコスト低減が図れる。   The semiconductor device according to the second embodiment has the same effect as that of the first embodiment. And the degree of freedom of chip combination is improved by stacking chips on both sides of the die pad. In addition, since the chip is mounted on both sides of the die pad, even if the chip is the same size, there is no need to secure a chip gap using a spacer or the like for wire connection, and the package can be reduced in thickness and cost can be reduced. Can be planned.

実施の形態３．
図４は、本発明の実施の形態３に係る半導体装置の断面図である。図１と同じ構成要素には同じ番号を付し、説明を省略する。 Embodiment 3 FIG.
FIG. 4 is a cross-sectional view of the semiconductor device according to the third embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted.

この半導体装置では、ダイパッド１１の表面上に、チップ１２とチップ２１が表裏反転して積層されている。例えば、チップ１２としてＳＲＡＭ、チップ２１としてＦｌａｓｈが用いられる。なお、図４では２つのチップを積層しているが、これに限らず、３以上のチップを積層してもよい。即ち、この半導体装置は、表裏反転して積層された２以上のチップを内部に有する。その他の構成は実施の形態２と同様である。   In this semiconductor device, the chip 12 and the chip 21 are laminated on the surface of the die pad 11 so as to be reversed. For example, SRAM is used as the chip 12 and Flash is used as the chip 21. In FIG. 4, two chips are stacked. However, the present invention is not limited to this, and three or more chips may be stacked. In other words, this semiconductor device has two or more chips laminated inside out. Other configurations are the same as those of the second embodiment.

また、この実施の形態３に係る半導体装置は、実施の形態１と同様にワイヤを用いて基板上に実装することができる。   Further, the semiconductor device according to the third embodiment can be mounted on a substrate using a wire as in the first embodiment.

上記の実施の形態３に係る半導体装置は、実施の形態１と同様の効果を奏する。そして、２つのチップを表裏反転して積層しているため、チップが同サイズの場合でも、ワイヤ接続のためにスペーサ等を用いてチップ間隙を確保する必要がなく、パッケージを薄型化を図れると共にコスト低減が図れる。   The semiconductor device according to the third embodiment has the same effect as that of the first embodiment. And since the two chips are turned upside down and stacked, even if the chips are the same size, there is no need to secure a chip gap using a spacer or the like for wire connection, and the package can be thinned. Cost reduction can be achieved.

実施の形態４．
図５は、本発明の実施の形態４に係る半導体装置の上面図である。図１と同じ構成要素には同じ番号を付し、説明を省略する。 Embodiment 4 FIG.
FIG. 5 is a top view of the semiconductor device according to the fourth embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted.

実施の形態１では、図１（ｂ）に示すように、リードは半導体装置の２辺に設けられている。これに対し、実施の形態４では、図５に示すように、リードは半導体装置の４辺に設けられている。その他の構成は実施の形態１と同様である。また、実施の形態４に係る半導体装置も、実施の形態１と同様にワイヤを用いて基板上に実装することができる。   In the first embodiment, as shown in FIG. 1B, the leads are provided on two sides of the semiconductor device. On the other hand, in the fourth embodiment, as shown in FIG. 5, the leads are provided on the four sides of the semiconductor device. Other configurations are the same as those of the first embodiment. Also, the semiconductor device according to the fourth embodiment can be mounted on a substrate using a wire as in the first embodiment.

上記の実施の形態４に係る半導体装置は、実施の形態１と同様の効果を奏する。そして、リードを半導体装置の４辺に設けたことにより、実施の形態１よりも更なる大容量化を図ることができる。   The semiconductor device according to the fourth embodiment has the same effects as those of the first embodiment. Further, by providing the leads on the four sides of the semiconductor device, the capacity can be further increased as compared with the first embodiment.

実施の形態５．
図６は、本発明の実施の形態５に係る実装基板を示す断面図である。図２と同じ構成要素には同じ番号を付し、説明を省略する。 Embodiment 5 FIG.
FIG. 6 is a cross-sectional view showing a mounting board according to Embodiment 5 of the present invention. The same components as those in FIG. 2 are denoted by the same reference numerals, and description thereof is omitted.

実施の形態５では、実施の形態１〜４の何れかに係る半導体装置１７上に、同様の半導体装置２３がリードの露出した部分を上にして実装されている。そして、基板１６に設けられたボンディングパッド１８とリードが、金線等のワイヤ２４により電気的に接続されている。   In the fifth embodiment, the same semiconductor device 23 is mounted on the semiconductor device 17 according to any one of the first to fourth embodiments with the exposed portion of the lead facing up. The bonding pad 18 provided on the substrate 16 and the lead are electrically connected by a wire 24 such as a gold wire.

上記の実施の形態５に係る半導体装置は、実施の形態１〜４と同様の効果を奏する。そして、半導体装置を積層することにより、更なる大容量化、高機能化を図ることができる。また、半導体装置を立体的に実装するため、実装面積が小さくなる。   The semiconductor device according to the fifth embodiment has the same effects as the first to fourth embodiments. Further, by stacking semiconductor devices, it is possible to further increase the capacity and function. Further, since the semiconductor device is mounted three-dimensionally, the mounting area is reduced.

また、リード１３の露出した部分と基板１６とを接続するワイヤ１９のループ高さをリード１３の逆面（図６では上面）と半導体装置１７の逆面（図６では上面）の差だけ削減できるため、ワイヤ接続のためにスペーサ等を用いて半導体装置の間隙を確保する必要がなく、薄型化を図れると共にコスト低減が図れる。   Further, the loop height of the wire 19 connecting the exposed portion of the lead 13 and the substrate 16 is reduced by the difference between the reverse surface of the lead 13 (upper surface in FIG. 6) and the reverse surface of the semiconductor device 17 (upper surface in FIG. 6). Therefore, it is not necessary to secure a gap between the semiconductor devices by using a spacer or the like for wire connection, so that the thickness can be reduced and the cost can be reduced.

なお、図６では、２個の半導体装置を積層しているが、３以上の半導体装置を積層しても良い。また、積層される各半導体装置の積層方向を軸として９０ずつ回転させても良い。   In FIG. 6, two semiconductor devices are stacked, but three or more semiconductor devices may be stacked. Further, it may be rotated by 90 around the stacking direction of each semiconductor device to be stacked.

実施の形態６．
図７は、本発明の実施の形態６に係る実装基板を示す側面図である。図２と同じ構成要素には同じ番号を付し、説明を省略する。 Embodiment 6 FIG.
FIG. 7 is a side view showing a mounting board according to Embodiment 6 of the present invention. The same components as those in FIG. 2 are denoted by the same reference numerals, and description thereof is omitted.

実施の形態６では、図７に示すように、実施の形態１〜５の何れかに係る半導体装置１７がリード１３の露出した部分を下にして基板１６上に設けられ、半導体装置１７のリード１３の露出した部分と基板１６が半田ボール２５により電気的に接続されている。   In the sixth embodiment, as shown in FIG. 7, the semiconductor device 17 according to any one of the first to fifth embodiments is provided on the substrate 16 with the exposed portion of the lead 13 facing down. The exposed portion 13 and the substrate 16 are electrically connected by solder balls 25.

上記の半導体装置ならば、大容量化及び小型化に伴いリードピッチが狭くなっても、リード１３の露出した部分と基板１６を半田ボール２５で接続することができる。従って、大容量化及び小型化を図ることができる   In the case of the semiconductor device described above, the exposed portion of the lead 13 and the substrate 16 can be connected by the solder ball 25 even if the lead pitch becomes narrow as the capacity and size are reduced. Accordingly, it is possible to increase the capacity and reduce the size.

また、リード１３の露出した部分と基板１６とを接続する半田ボール２５の厚みをリード１３の逆面（図７では下面）と半導体装置１７の逆面（図７では下面）の差だけ削減できるため、薄型化を図ることができる。   Further, the thickness of the solder ball 25 connecting the exposed portion of the lead 13 and the substrate 16 can be reduced by the difference between the reverse surface of the lead 13 (lower surface in FIG. 7) and the reverse surface of the semiconductor device 17 (lower surface in FIG. 7). Therefore, the thickness can be reduced.

また、半田ボールを用いることで、半導体装置のリードの露出した部分と基板との電気的な接続を容易に行うことができる。   Further, by using the solder balls, electrical connection between the exposed portions of the leads of the semiconductor device and the substrate can be easily performed.

本発明の実施の形態１に係る半導体装置の断面図（ａ）及び上面図（ｂ）である。It is sectional drawing (a) and top view (b) of the semiconductor device which concerns on Embodiment 1 of this invention. 図１に示す半導体装置を基板に実装した状態を示す断面図（ａ）及び上面図（ｂ）である。FIG. 2 is a cross-sectional view (a) and a top view (b) showing a state in which the semiconductor device shown in FIG. 1 is mounted on a substrate. 本発明の実施の形態２に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態３に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on Embodiment 3 of this invention. 本発明の実施の形態４に係る半導体装置の上面図である。It is a top view of the semiconductor device which concerns on Embodiment 4 of this invention. 本発明の実施の形態５に係る実装基板を示す断面図である。It is sectional drawing which shows the mounting substrate which concerns on Embodiment 5 of this invention. 本発明の実施の形態６に係る実装基板を示す側面図である。It is a side view which shows the mounting substrate which concerns on Embodiment 6 of this invention. 従来の半導体装置を示す断面図（ａ）及び上面図（ｂ）である。It is sectional drawing (a) and a top view (b) which show the conventional semiconductor device. 他の従来の半導体装置を示す断面図である。It is sectional drawing which shows another conventional semiconductor device.

符号の説明Explanation of symbols

１１ ダイパッド
１２，２１ チップ
１３ リード
１４，１９，２２，２４ ワイヤ
１５，２０ 樹脂
１６ 基板
１７，２３ 半導体装置
２５ 半田ボール 11 Die pad 12, 21 Chip 13 Lead 14, 19, 22, 24 Wire 15, 20 Resin 16 Substrate 17, 23 Semiconductor device 25 Solder ball

Claims (7)

外部接続用のリードを用いた樹脂封止型の半導体装置であって、
前記リードの片面は樹脂により覆われ、
前記リードの逆面の一部は露出し、
前記リードの露出した部分は、前記半導体装置の前記逆面の他の部分と比べて窪んでいることを特徴とする半導体装置。 A resin-encapsulated semiconductor device using a lead for external connection,
One side of the lead is covered with resin,
A part of the reverse side of the lead is exposed,
The exposed portion of the lead is recessed as compared with other portions of the opposite surface of the semiconductor device. 積層された２以上のチップを内部に有することを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, further comprising two or more stacked chips inside. ダイパッドと、前記ダイパッドの両面に実装された２以上のチップを内部に有することを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, comprising a die pad and two or more chips mounted on both surfaces of the die pad. 表裏反転して積層された２以上のチップを内部に有することを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, further comprising two or more chips laminated inside out in reverse. 前記リードは、前記半導体装置の２辺又は４辺に設けられていることを特徴とする請求項１〜４の何れか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the lead is provided on two or four sides of the semiconductor device. 請求項１〜５の何れか１項に記載の半導体装置が前記リードの露出した部分を上にして基板上に設けられ、
前記半導体装置の前記リードの露出した部分と前記基板がワイヤにより電気的に接続されていることを特徴とする実装基板。 The semiconductor device according to claim 1 is provided on a substrate with an exposed portion of the lead facing up,
The mounting substrate, wherein the exposed portion of the lead of the semiconductor device and the substrate are electrically connected by a wire. 請求項１〜５の何れか１項に記載の半導体装置が前記リードの露出した部分を下にして基板上に設けられ、
前記半導体装置の前記リードの露出した部分と基板が前記半田により電気的に接続されていることを特徴とする実装基板。 The semiconductor device according to claim 1 is provided on a substrate with an exposed portion of the lead down.
The mounting substrate, wherein the exposed portion of the lead of the semiconductor device and the substrate are electrically connected by the solder.
JP2004153041A 2004-05-24 2004-05-24 Semiconductor device and mounting substrate Pending JP2005340245A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004153041A JP2005340245A (en) 2004-05-24 2004-05-24 Semiconductor device and mounting substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004153041A JP2005340245A (en) 2004-05-24 2004-05-24 Semiconductor device and mounting substrate

Publications (1)

Publication Number Publication Date
JP2005340245A true JP2005340245A (en) 2005-12-08

Family

ID=35493506

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004153041A Pending JP2005340245A (en) 2004-05-24 2004-05-24 Semiconductor device and mounting substrate

Country Status (1)

Country Link
JP (1) JP2005340245A (en)

Similar Documents

Publication Publication Date Title
KR100477020B1 (en) Multi chip package
KR102005830B1 (en) Flip-chip, face-up and face-down centerbond memory wirebond assemblies
US7598617B2 (en) Stack package utilizing through vias and re-distribution lines
KR101070913B1 (en) Stacked die package
JP4751351B2 (en) Semiconductor device and semiconductor module using the same
JP5066302B2 (en) Semiconductor device
US7989943B2 (en) Staircase shaped stacked semiconductor package
JP2011101044A (en) Stacked package and method of manufacturing the same
US20060284298A1 (en) Chip stack package having same length bonding leads
JP2015523740A (en) Reconfigured wafer level microelectronic package
JP2008235823A (en) Multiple chip semiconductor device
JP4538830B2 (en) Semiconductor device
JP2006156797A (en) Semiconductor device
US20080093724A1 (en) Stackable Micropackages and Stacked Modules
JP2001358285A (en) Resin sealed semiconductor device
KR100650769B1 (en) Stack type package
JP4343727B2 (en) Semiconductor device
JP2005167286A (en) Semiconductor device and manufacturing method thereof
JP2005340245A (en) Semiconductor device and mounting substrate
JP2014027145A (en) Semiconductor device
JP2006086150A (en) Semiconductor device
JP5096730B2 (en) Semiconductor device
KR100813621B1 (en) Stacked semiconductor device package
KR100747996B1 (en) Semiconductor package
KR101019705B1 (en) Substrate for fabricating semiconductor package and semiconductor package using the same