JP2005327914A - Circuit board and mounting method of electronic component - Google Patents

Circuit board and mounting method of electronic component Download PDF

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JP2005327914A
JP2005327914A JP2004144915A JP2004144915A JP2005327914A JP 2005327914 A JP2005327914 A JP 2005327914A JP 2004144915 A JP2004144915 A JP 2004144915A JP 2004144915 A JP2004144915 A JP 2004144915A JP 2005327914 A JP2005327914 A JP 2005327914A
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resin
circuit board
electronic component
etching
chip
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JP4233486B2 (en
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Fumihiko Matsuda
文彦 松田
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Nippon Mektron KK
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit board, its manufacturing method and a mounting method of electronic components. <P>SOLUTION: The circuit board is constituted, such that material having a conductive layer 2 is prepared for one side of an insulating resin layer 1 of low resistance for resin etching, a circuit wiring pattern 4 is formed in the conductive layer 2 by etching, an adhesive resin layer 5 of high resin etching resistance is stuck to the circuit wiring pattern 4, and a resin projection 7 is formed, by carrying out resin etching of the insulating resin layer 1 of low resin etching resistance. In order to mount a semiconductor device in this circuit board, it is required to prepare a circuit board wherein the resin projection 7 is formed in the vicinity of the electronic-parts connection pad on the circuit board surface, without melting at the solder fusing temperature, and at facedown mounting of the electronic components to a connection pad, the resin projection 7 forms a clearance equal to the height of the resin projection 7 between the circuit board and electronic components. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、回路基板の構造、製造方法及び電子部品の実装方法に関し、特には、半導体装置を実装する回路基板に関する。   The present invention relates to a circuit board structure, a manufacturing method, and an electronic component mounting method, and more particularly to a circuit board on which a semiconductor device is mounted.

近年、携帯電話等の小型電子機器に向け、電子機器に搭載される実装基板の微細化、高密度化の要求が高まっている。それに伴い、ICチップ等のチップ部品の基板への実装方法もより高密度化が可能な方法へ移行しつつある。従来のフェイスアップで実装を行うワイヤーボンディングでは部品実装に要する面積が大きいため、より高密度に実装するためフェイスダウンで実装可能なフリップチップ実装が高密度実装基板の実装方法の主流となりつつある。   In recent years, there has been an increasing demand for miniaturization and higher density of mounting boards mounted on electronic devices for small electronic devices such as mobile phones. Along with this, the mounting method of chip components such as IC chips on a substrate is also shifting to a method capable of achieving higher density. In the conventional wire bonding in which mounting is performed face-up, the area required for component mounting is large. Therefore, flip-chip mounting that can be mounted face-down for mounting at higher density is becoming the mainstream mounting method for high-density mounting substrates.

また、フリップチップ実装に際しては半田バンプをICチップ側に形成し、基板へフリップチップボンダーで実装した後、リフローにより半田を溶融し、接続を得る。このときの半田バンプの高さでICチップと接続パッドの隙間の量、すなわちICチップの高さを制御している。   In flip chip mounting, solder bumps are formed on the IC chip side, mounted on a substrate with a flip chip bonder, and then solder is melted by reflow to obtain connection. The height of the solder bump at this time controls the amount of gap between the IC chip and the connection pad, that is, the height of the IC chip.

ICチップの高さを制御する理由を以下に示す。ICチップと実装基板は線熱膨張係数が異なるので、このストレスが半田に加わり、実装基板側の接続パッドから剥がれるのを防止するために、ICチップと実装基板の間にアンダーフィルと呼ばれる熱硬化性樹脂を注入する工程が必要である。この熱硬化樹脂は毛管現象を利用しているため、ICチップの高さを制御する必要がある。   The reason for controlling the height of the IC chip is shown below. Since the thermal expansion coefficient of the IC chip and the mounting board are different, in order to prevent this stress from being applied to the solder and peeling off from the connection pad on the mounting board side, a thermosetting called underfill is used between the IC chip and the mounting board. A step of injecting the functional resin is required. Since this thermosetting resin utilizes capillary action, it is necessary to control the height of the IC chip.

特に、近年普及してきている鉛フリー半田はリフロー温度も共晶半田に比べ高いため、ICチップの高さの制御が困難になってきている。特許文献1によれば、最近では素子の多ピン化のために、半田バンプや実装基板の接続パッドのピッチはどんどん狭くなり、高さも低くなっている。このためICチップと接続パッドの距離も狭くなり、熱硬化樹脂の注入が困難、場合によっては不可能となるという問題があり、ICチップと実装基板の間の接続信頼性が確保できない場合があった。   In particular, lead-free solder, which has become popular in recent years, has a higher reflow temperature than eutectic solder, making it difficult to control the height of the IC chip. According to Patent Document 1, recently, the pitch of solder bumps and connection pads of a mounting board is becoming narrower and lower in height due to the increase in the number of pins of the element. For this reason, the distance between the IC chip and the connection pad is also narrowed, and there is a problem that injection of thermosetting resin is difficult and sometimes impossible, and connection reliability between the IC chip and the mounting substrate may not be ensured. It was.

この問題に対して、特許文献1ではチップ側にリフローで溶融しない金属のバンプをめっきで形成することが記されている。また、特許文献2には基板側の接続パッド側にリフローで溶融しない金属のバンプをめっきで形成することが記されている。しかしながら、これらの方法はいずれも工数が多く、煩雑であることと、ICチップまたは基板の接続パッド上にめっきをつけるため、ICチップのバンプおよび接続パッドのピッチの微細化が困難であった。   With respect to this problem, Patent Document 1 describes that a metal bump that does not melt by reflow is formed on the chip side by plating. Patent Document 2 describes that a metal bump that does not melt by reflow is formed on a connection pad side on the substrate side by plating. However, each of these methods has many man-hours and is complicated, and since plating is performed on the connection pads of the IC chip or the substrate, it is difficult to reduce the pitches of the bumps of the IC chip and the connection pads.

さらに、特許文献3には基板側の接続パッド側にリフローで溶融しない金属のバンプをエッチングで形成することが記されているが、ICチップの高さを確保するためには金属バンプの高さ、すなわち出発材料の厚さが厚くなることから、バンプを狭ピッチで形成することは困難であり、基板の接続パッドの微細化には対応できない方法であった。   Further, Patent Document 3 describes that a metal bump that does not melt by reflow is formed by etching on the connection pad side on the substrate side. However, in order to ensure the height of the IC chip, the height of the metal bump is described. That is, since the thickness of the starting material is increased, it is difficult to form the bumps at a narrow pitch, and the method cannot cope with the miniaturization of the connection pads of the substrate.

図4は、従来の回路基板の製造方法および回路基板に対するチップ実装方法を示す工程図であって、先ず、同図(1)に示す様に、絶縁ベース材12の片面に銅箔層13を有する、所謂、片面銅張積層板14を用意する。   FIG. 4 is a process diagram showing a conventional circuit board manufacturing method and chip mounting method for a circuit board. First, as shown in FIG. 4A, a copper foil layer 13 is formed on one surface of an insulating base material 12. A so-called single-sided copper-clad laminate 14 is prepared.

次に、同図(2)に示す様に、この片面型銅張積層板14の銅箔層13に対し、通常のフォトファブリケーション手法によるエッチング手法を用いて、回路配線パターン5を形成し、必要に応じソルダーレジスト層を設けたり、NiやAuを表面処理層として無電解めっき等の手法で形成し、金型による打ち抜き等により外形加工を行い、回路基板15を得る。   Next, as shown in FIG. 2 (2), a circuit wiring pattern 5 is formed on the copper foil layer 13 of the single-sided copper clad laminate 14 by using an etching method based on a normal photofabrication method. A circuit board 15 is obtained by providing a solder resist layer as necessary, forming Ni or Au as a surface treatment layer by a method such as electroless plating, and performing external processing by punching with a mold or the like.

次に、同図(3)に示す様に、半田バンプ9を有するICチップ10を用意し、フリップチップボンダーを用いて、前記回路基板上にフェイスダウン実装する。その後、リフローを行い、前記ICチップ10の半田ボール9を溶融させ、ICチップ10と回路基板15の接続を得る。   Next, as shown in FIG. 3C, an IC chip 10 having solder bumps 9 is prepared and mounted face-down on the circuit board using a flip chip bonder. Thereafter, reflow is performed to melt the solder balls 9 of the IC chip 10 to obtain a connection between the IC chip 10 and the circuit board 15.

次に、同図(4)に示す様に、アンダーフィルとして熱硬化樹脂11をICチップ10と回路基板15の間に注入することで回路基板15にICチップ10がフェースダウン実装される。
特開2001−284380号公報 特開平5−74778号公報 特開2001−53189号公報 特開2003−129259号公報 特開平10−97081号公報
Next, as shown in FIG. 4 (4), the thermosetting resin 11 is injected between the IC chip 10 and the circuit board 15 as an underfill, so that the IC chip 10 is mounted on the circuit board 15 face down.
JP 2001-284380 A JP-A-5-74778 JP 2001-53189 A JP 2003-129259 A JP-A-10-97081

ICチップ等の電子部品と接続パッドの距離も狭くなり、熱硬化樹脂の注入が困難、場合によっては不可能となるという問題があり、ICチップ等の電子部品と実装基板の間の接続信頼性が確保できない場合がある。   The distance between electronic components such as IC chips and connection pads is also narrowed, and there is a problem that injection of thermosetting resin is difficult and sometimes impossible. May not be secured.

この問題に対して、特許文献1ではICチップ側にリフローで溶融しない金属のバンプをめっきで形成することが記されている。また、特許文献2には基板側の接続パッド側にリフローで溶融しない金属のバンプをめっきで形成することが記されている。   With respect to this problem, Patent Document 1 describes that a metal bump that does not melt by reflow is formed on the IC chip side by plating. Patent Document 2 describes that a metal bump that does not melt by reflow is formed on a connection pad side on the substrate side by plating.

しかしながら、これらの方法はいずれも工数が多く、煩雑であることと、ICチップまたは基板の接続パッド上にめっきをつけるため、ICチップのバンプおよび接続パッドのピッチの微細化が困難であった。さらに、特許文献3には基板側の接続パッド側にリフローで溶融しない金属のバンプをエッチングで形成することが記されているが、ICチップの高さを確保するためには金属バンプの高さ、すなわち出発材料の厚さが厚くなることから、バンプを狭ピッチで形成することは困難であり、基板の接続パッドの微細化には対応できない方法であった。   However, each of these methods has many man-hours and is complicated, and since plating is performed on the connection pads of the IC chip or the substrate, it is difficult to reduce the pitches of the bumps of the IC chip and the connection pads. Further, Patent Document 3 describes that a metal bump that does not melt by reflow is formed by etching on the connection pad side on the substrate side. However, in order to ensure the height of the IC chip, the height of the metal bump is described. That is, since the thickness of the starting material is increased, it is difficult to form the bumps at a narrow pitch, and the method cannot cope with the miniaturization of the connection pads of the substrate.

すなわち、発明が解決しようとする課題は、ICチップ等の電子部品実装後に適性なICチップ等の電子部品の高さを確保することと、接続パッドの微細化を両立することである。   That is, the problem to be solved by the present invention is to ensure the height of an appropriate electronic component such as an IC chip after mounting the electronic component such as an IC chip and to make the connection pads finer.

上記課題を解決するため発明によれば、回路基板の製造方法において、樹脂エッチング液耐性の低い絶縁樹脂層の片面に導電層を有する材料を用意し、前記導電層にエッチングにより回路配線パターンを形成し、前記回路配線パターン上に樹脂エッチング耐性の高い接着性樹脂層を接着し、前記樹脂エッチング耐性の低い絶縁樹脂層を樹脂エッチングすることで突起を形成することを特徴とする回路基板の製造方法が採用される。   According to the invention for solving the above-mentioned problems, in a method for manufacturing a circuit board, a material having a conductive layer is prepared on one side of an insulating resin layer having a low resistance to a resin etching solution, and a circuit wiring pattern is formed on the conductive layer by etching. And forming a protrusion by bonding an adhesive resin layer having a high resin etching resistance on the circuit wiring pattern and etching the insulating resin layer having a low resin etching resistance. Is adopted.

また、発明によれば、回路基板表面に半田が溶融する温度においても溶融しない樹脂突起を電子部品接続パッド近傍に形成した回路基板を準備し、電子部品を接続パッドにフェイスダウン実装する際に前記樹脂突起で前記回路基板と前記電子部品の間に樹脂突起の高さに等しい隙間を形成することを特徴とする電子部品の実装方法が採用される。   Further, according to the invention, when preparing a circuit board having a resin protrusion formed in the vicinity of the electronic component connection pad on the surface of the circuit board that does not melt even at a temperature at which the solder melts, An electronic component mounting method is employed, wherein a gap equal to the height of the resin protrusion is formed between the circuit board and the electronic component by the resin protrusion.

さらに、発明によれば、回路基板において、回路基板表面の電子部品実装部に電子部品接続パッドよりも高い樹脂突起を電子部品接続パッド近傍に有することを特徴とする回路基板の構造が採用される。   Furthermore, according to the invention, the circuit board structure is characterized in that the circuit board has a resin protrusion higher than the electronic component connection pad in the vicinity of the electronic component connection pad on the electronic component mounting portion on the surface of the circuit board. .

これらの特徴により、本発明は次のような効果を奏する。   Due to these features, the present invention has the following effects.

本発明による回路基板は樹脂エッチング液耐性の低い絶縁樹脂層の片面に導電層を有する材料を用意し、前記導電層にエッチングにより回路配線パターンを形成し、前記回路配線パターン上に樹脂エッチング耐性の高い接着性樹脂層を接着し、前記樹脂エッチング耐性の低い絶縁樹脂層を樹脂エッチングすることで突起を形成することで製造され、電子部品を接続パッドにフェイスダウン実装する際に前記樹脂突起で前記回路基板と前記電子部品の間に樹脂突起の高さに等しい隙間を形成することで実装されるからリフロープロファイルに影響されることなく、電子部品の高さを一定にすることができるばかりか、電子部品をフェイスダウン実装する際に前記樹脂突起が変形し、リフロー時に電子部品の半田ボールが溶融する時に前記樹脂突起の変形が開放されることで半田ボールのフィレット形状を良好にすることも可能である。   A circuit board according to the present invention is prepared by preparing a material having a conductive layer on one side of an insulating resin layer having a low resistance to a resin etching solution, forming a circuit wiring pattern on the conductive layer by etching, and having a resin etching resistance on the circuit wiring pattern. It is manufactured by bonding a high adhesive resin layer and forming a protrusion by resin etching the insulating resin layer having a low resin etching resistance, and when the electronic component is face-down mounted on a connection pad, the resin protrusion Since it is mounted by forming a gap equal to the height of the resin protrusion between the circuit board and the electronic component, the height of the electronic component can be made constant without being affected by the reflow profile, When the electronic component is mounted face down, the resin protrusion is deformed, and the solder bump of the electronic component is melted during reflow. It is also possible to deform the can to improve the fillet shape of the solder balls by being opened.

さらに接続パッド上にめっきを厚付けする必要がないため接続パッドの狭ピッチ化に対応できるばかりか、接続パッドを絶縁ベース材に埋め込む構造になるため、基板の薄型化も計れる。このため、微細かつ高密度な実装回路基板および安価にかつ安定的に提供することおよび電子部品の実装を安価にかつ安定的に行うことができる。   Further, since it is not necessary to thicken the plating on the connection pad, not only can the pitch of the connection pad be reduced, but also the connection pad is embedded in the insulating base material, so that the substrate can be made thinner. For this reason, it is possible to provide a fine and high-density mounting circuit board and an inexpensive and stable manner and to mount electronic components at a low cost and stably.

以下、図示の実施例を参照しながら本発明をさらに説明する。   Hereinafter, the present invention will be further described with reference to the illustrated embodiments.

図1は、本発明の回路基板の製造方法を示す工程図であって、先ず、同図(1)に示す様に、特許文献5に記載されている樹脂エッチング液に対する耐性の低い絶縁樹脂1に銅箔2を有する片面銅張り板3を用意する。ここで、樹脂エッチング液としては特許文献5に記載のアルカリ金属およびアミン系化合物および水からなる液が好ましい。   FIG. 1 is a process diagram showing a method of manufacturing a circuit board according to the present invention. First, as shown in FIG. 1A, an insulating resin 1 having low resistance to a resin etching solution described in Patent Document 5 is shown. A single-sided copper-clad plate 3 having a copper foil 2 is prepared. Here, the resin etching solution is preferably a solution composed of an alkali metal, an amine compound and water described in Patent Document 5.

前記絶縁樹脂1の種類としてはピロメリット酸二無水物と芳香族ジアミンとの重縮合により得られるポリイミドフィルム(例えば米国デュポン社製のカプトン、鐘淵化学株式会社のアピカル)あるいは、これに類する構造の熱可塑性ポリイミドおよびこれらの前駆体が好適である。   As the kind of the insulating resin 1, a polyimide film obtained by polycondensation of pyromellitic dianhydride and an aromatic diamine (for example, Kapton manufactured by DuPont of the United States, Apical manufactured by Kanae Chemical Co., Ltd.) or a similar structure is used. These thermoplastic polyimides and their precursors are preferred.

次に、同図(2)に示す様に、前記片面銅張り板3の銅箔2に対し、通常のフォトファブリケーション手法によるエッチング手法を用いて、回路配線パターン4を形成する。   Next, as shown in FIG. 2B, a circuit wiring pattern 4 is formed on the copper foil 2 of the single-sided copper-clad plate 3 by using an etching method based on a normal photofabrication method.

次に、同図(3)に示す様に、前記回路配線パターン4上に樹脂エッチング液に対する耐性の高い絶縁樹脂5を形成する。前記絶縁樹脂5の形成手法としてはキャスト、ラミネート、コーティング等が適用可能で、絶縁樹脂の種類、形態(ワニス、フィルム)によって最適な手法を選択する。   Next, as shown in FIG. 3C, an insulating resin 5 having a high resistance to a resin etching solution is formed on the circuit wiring pattern 4. Casting, laminating, coating, or the like can be applied as a method for forming the insulating resin 5. An optimum method is selected depending on the type and form (varnish, film) of the insulating resin.

ここでは熱硬化性のポリイミドフィルムをラミネートにより熱圧着した。前記樹脂エッチング液耐性の高い絶縁樹脂5は接着層であって、アクリル系、エポキシ系、熱可塑性ポリイミド等、樹脂エッチング液耐性が前記樹脂エッチング液耐性の低い絶縁樹脂1よりも、高いものが選択可能である。ポリイミドの場合にはビフェニルテトラカルボン酸二無水物とジアミノベンゼンの重縮合により得られるポリイミドフィルム(例えば宇部興産株式会社製のユーピレックス)およびこれらの前駆体が好適である。   Here, a thermosetting polyimide film was thermocompression bonded by lamination. The insulating resin 5 having a high resistance to the resin etching solution is an adhesive layer, and an acrylic resin, an epoxy resin, a thermoplastic polyimide, or the like having a higher resistance to the resin etching solution than the insulating resin 1 having a low resistance to the resin etching solution is selected. Is possible. In the case of polyimide, a polyimide film obtained by polycondensation of biphenyltetracarboxylic dianhydride and diaminobenzene (for example, Upilex manufactured by Ube Industries, Ltd.) and a precursor thereof are suitable.

次に、同図(4)に示す様に、前記絶縁樹脂1上に樹脂突起を形成するためのレジスト層6を形成する。   Next, a resist layer 6 for forming resin protrusions is formed on the insulating resin 1 as shown in FIG.

次に、同図(5)に示す様に、樹脂エッチングを行い、絶縁樹脂突起7を形成する。選択的に樹脂エッチング耐性の低い絶縁樹脂1のみが樹脂エッチングされる。   Next, as shown in FIG. 5 (5), resin etching is performed to form insulating resin protrusions 7. Only the insulating resin 1 having low resin etching resistance is selectively etched.

次に、同図(6)に示す様に、レジスト層6を剥離し、必要に応じソルダーレジスト層を設けたり、NiやAuを表面処理層として無電解めっき等の手法で形成し、金型による打ち抜き等により外形加工を行い、回路基板8を得る。尚、図には示さないが、定法によりViaホール接続等で両面基板とすることも可能である。   Next, as shown in FIG. 6 (6), the resist layer 6 is peeled off, and a solder resist layer is provided if necessary, or Ni or Au is used as a surface treatment layer by a method such as electroless plating, External processing is performed by punching or the like to obtain the circuit board 8. Although not shown in the drawing, a double-sided board can be formed by via hole connection or the like by a conventional method.

図2は、本発明の電子部品の実装方法を示す工程図であって、先ず、同図(1)に示す様に、半田バンプ9を有するICチップ10を用意し、フリップチップボンダーを用いて、図1に示した工程で製造した回路基板8上にフェイスダウン実装する。その後、リフローを行い、前記ICチップ10の半田ボール9を溶融させ、ICチップ10と回路基板8の接続を得る。このとき回路基板8上の樹脂突起7によりICチップの高さは規定されるとともに半田のフィレット形状を得ることができる。   FIG. 2 is a process diagram showing a method for mounting an electronic component according to the present invention. First, as shown in FIG. 2A, an IC chip 10 having solder bumps 9 is prepared and a flip chip bonder is used. Then, face-down mounting is performed on the circuit board 8 manufactured in the process shown in FIG. Thereafter, reflow is performed to melt the solder balls 9 of the IC chip 10 to obtain a connection between the IC chip 10 and the circuit board 8. At this time, the height of the IC chip is defined by the resin protrusions 7 on the circuit board 8, and a solder fillet shape can be obtained.

次に、同図(2)に示す様に、アンダーフィルとして熱硬化樹脂11をICチップ10と回路基板8の間に注入することで回路基板8にICチップ10がフェースダウン実装される。   Next, as shown in FIG. 2B, the thermosetting resin 11 is injected between the IC chip 10 and the circuit board 8 as an underfill so that the IC chip 10 is mounted face-down on the circuit board 8.

図3は、本発明の回路基板の構造を示す概念的断面構成図であって、同図(1)のようにICチップの高さを規定する樹脂突起7を有する回路基板8であって、回路配線パターン4が絶縁層5に埋め込まれた構造を有している。この回路基板8に対して、同図(2)のようにICチップ10をフェースダウン実装した際のICチップ10の回路基板8からの高さは樹脂突起7によって規定される。   FIG. 3 is a conceptual cross-sectional view showing the structure of the circuit board of the present invention, which is a circuit board 8 having a resin protrusion 7 that defines the height of the IC chip as shown in FIG. The circuit wiring pattern 4 has a structure embedded in the insulating layer 5. The height of the IC chip 10 from the circuit board 8 when the IC chip 10 is face-down mounted on the circuit board 8 as shown in FIG.

本発明の回路基板の製造方法を示す工程図。Process drawing which shows the manufacturing method of the circuit board of this invention. 本発明の電子部品の実装方法を示す工程図。Process drawing which shows the mounting method of the electronic component of this invention. 本発明の回路基板の構造を示す概念的断面構成図。1 is a conceptual cross-sectional configuration diagram illustrating a structure of a circuit board according to the present invention. 従来の手法による回路基板の製造方法および電子部品の実装方法を示す工程図。Process drawing which shows the manufacturing method of the circuit board by the conventional method, and the mounting method of an electronic component.

符号の説明Explanation of symbols

1 樹脂エッチング耐性の低い絶縁樹脂
2 銅箔
3 片面銅張り板
4 回路配線パターン
5 樹脂エッチング液耐性の高い絶縁樹脂
6 レジスト層
7 樹脂突起
8 本発明による回路基板
9 半田バンプ
10 ICチップ
11 熱硬化樹脂
12 絶縁ベース材
13 銅箔層
14 片面銅張り板
15 従来工法による回路基板
DESCRIPTION OF SYMBOLS 1 Insulation resin with low resin etching resistance 2 Copper foil 3 Single-sided copper-clad board 4 Circuit wiring pattern 5 Insulation resin with high resistance to resin etching solution 6 Resist layer 7 Resin protrusion 8 Circuit board 9 according to the present invention Solder bump 10 IC chip 11 Thermosetting Resin 12 Insulating base material 13 Copper foil layer 14 Single-sided copper-clad board 15 Circuit board by conventional method

Claims (3)

回路基板の製造方法において、樹脂エッチング液耐性の低い絶縁樹脂層の片面に導電層を有する材料を用意し、前記導電層にエッチングにより回路配線パターンを形成し、前記回路配線パターン上に樹脂エッチング耐性の高い接着性樹脂層を接着し、前記樹脂エッチング耐性の低い絶縁樹脂層を樹脂エッチングすることにより突起を形成することを特徴とする回路基板の製造方法。   In a circuit board manufacturing method, a material having a conductive layer is prepared on one side of an insulating resin layer having a low resin etchant resistance, a circuit wiring pattern is formed by etching on the conductive layer, and the resin etching resistance is formed on the circuit wiring pattern. A method of manufacturing a circuit board, comprising: bonding a high adhesive resin layer and etching the insulating resin layer having low resin etching resistance to form a protrusion. 回路基板表面に半田が溶融する温度においても溶融しない樹脂突起を電子部品接続パッド近傍に形成した回路基板を準備し、電子部品を接続パッドにフェイスダウン実装する際に前記樹脂突起で前記回路基板と前記電子部品の間に樹脂突起の高さに等しい隙間を形成することを特徴とする半導体装置の実装方法。   A circuit board having a resin protrusion that is not melted even at a temperature at which solder is melted on the surface of the circuit board is prepared in the vicinity of the electronic component connection pad, and when the electronic component is face-down mounted on the connection pad, the resin protrusion A method of mounting a semiconductor device, wherein a gap equal to the height of a resin protrusion is formed between the electronic components. 回路基板において、回路基板表面の電子部品実装部に電子部品接続パッドよりも高い樹脂突起を電子部品接続パッド近傍に有することを特徴とする回路基板。   A circuit board having a resin protrusion higher than an electronic component connection pad on an electronic component mounting portion on the surface of the circuit board in the vicinity of the electronic component connection pad.
JP2004144915A 2004-05-14 2004-05-14 Circuit board manufacturing method and electronic component mounting method Expired - Fee Related JP4233486B2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013171967A1 (en) * 2012-05-18 2013-11-21 富士電機機器制御株式会社 Method for mounting electronic component on surface-mounting substrate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013171967A1 (en) * 2012-05-18 2013-11-21 富士電機機器制御株式会社 Method for mounting electronic component on surface-mounting substrate
JP2013243222A (en) * 2012-05-18 2013-12-05 Fuji Electric Fa Components & Systems Co Ltd Electronic component mounting method on surface mounting substrate
US9144186B2 (en) 2012-05-18 2015-09-22 Fuji Electric Fa Components & Systems Co., Ltd. Method of mounting electronic parts on surface mounting substrate using a film resist standoff

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